JP7254930B2 - パッケージング基板及びこれを含む半導体装置 - Google Patents
パッケージング基板及びこれを含む半導体装置 Download PDFInfo
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- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
Claims (9)
- コア層及び上部層を含むものであって、
前記コア層は、互いに向かい合う第1面及び第2面を有するガラス基板と、前記第1面及び前記第2面を貫通するコアビアと、を含む支持体基板;及び
前記第1面及び第2面の少なくとも一部上にそれぞれ位置する電気伝導性層と、これらを前記コアビアを介して互いに電気的に連結する電気伝導性層と、を含むコア分配層;を含み、
前記上部層は、前記第1面上に位置し、前記コア分配層と素子部とを電気的に連結する電気伝導性層を含み、
前記ガラス基板に形成されたコアビアのうち最小内径を有する部分の平均内径は50μm~95μmであって、下記の式1-1の条件を満足する、パッケージング基板;
[式1-1]
前記式1-1において、D50は、前記最小内径の直径分布のうち50%に該当する値で、D90は、前記最小内径の直径分布のうち90%に該当する値で、D10は、前記最小内径の直径分布のうち10%に該当する値である。 - 前記コアビアは、前記ガラス基板の単位面積(1cm2)を基準にして100個~3000個が位置する、請求項1に記載のパッケージング基板。
- 前記最小内径を有する部分は、前記コアビアの長さ全体を100%としたとき、前記第1面と接する開口部を基準にして40%~60%の地点に位置する、請求項1に記載のパッケージング基板。
- 前記コアビアは、前記ガラス基板に1.2mm以下のピッチで位置する、請求項1に記載のパッケージング基板。
- 前記コア分配層は、前記ガラス基板の第1面と第2面とを貫通ビアを介して電気的に連結する電気伝導性層であるコア分配パターン;及び
前記コア分配パターンを覆うコア絶縁層;を含む、請求項1に記載のパッケージング基板。 - 前記パッケージング基板の厚さは約2000μm以下である、請求項1に記載のパッケージング基板。
- 1以上の半導体素子が位置する半導体素子部;前記半導体素子と電気的に連結されるパッケージング基板;及び前記パッケージング基板と電気的に連結され、前記半導体素子に外部の電気的信号を伝達し、前記半導体素子を互いに連結するマザーボード;を含み、
前記パッケージング基板は、請求項1によるパッケージング基板である、半導体装置。
Applications Claiming Priority (3)
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US201962816984P | 2019-03-12 | 2019-03-12 | |
US62/816,984 | 2019-03-12 | ||
PCT/KR2020/003481 WO2020185021A1 (ko) | 2019-03-12 | 2020-03-12 | 패키징 기판 및 이를 포함하는 반도체 장치 |
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JP2022523897A JP2022523897A (ja) | 2022-04-27 |
JP7254930B2 true JP7254930B2 (ja) | 2023-04-10 |
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US (1) | US11967542B2 (ja) |
EP (1) | EP3916772A4 (ja) |
JP (1) | JP7254930B2 (ja) |
KR (1) | KR102528166B1 (ja) |
CN (1) | CN113272951B (ja) |
WO (1) | WO2020185021A1 (ja) |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2016034030A (ja) | 2015-09-29 | 2016-03-10 | 大日本印刷株式会社 | 貫通電極基板および貫通電極基板の製造方法 |
JP2017510531A (ja) | 2013-12-17 | 2017-04-13 | コーニング インコーポレイテッド | ガラスおよびガラス製品への高速レーザ穴あけ方法 |
JP2018107256A (ja) | 2016-12-26 | 2018-07-05 | 凸版印刷株式会社 | ガラス配線板、半導体パッケージ基板、半導体装置、及び半導体装置の製造方法 |
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