JP4891235B2 - 回路基板とその製造方法及びこれを用いた電子部品 - Google Patents
回路基板とその製造方法及びこれを用いた電子部品 Download PDFInfo
- Publication number
- JP4891235B2 JP4891235B2 JP2007518827A JP2007518827A JP4891235B2 JP 4891235 B2 JP4891235 B2 JP 4891235B2 JP 2007518827 A JP2007518827 A JP 2007518827A JP 2007518827 A JP2007518827 A JP 2007518827A JP 4891235 B2 JP4891235 B2 JP 4891235B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- hole
- filling member
- circuit board
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 89
- 239000011521 glass Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 22
- 230000007423 decrease Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 38
- 238000007789 sealing Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 7
- 239000012790 adhesive layer Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000004576 sand Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000700 radioactive tracer Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
- H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
- H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
- H03H9/1021—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device the BAW device being of the cantilever type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1147—Sealing or impregnating, e.g. of pores
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
- Y10T428/24612—Composite web or sheet
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Acoustics & Sound (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
前記スルーホールの内壁と前記第1及び第2主面における前記スルーホールの開口部周囲とに形成された導電膜と、
前記スルーホールに充填された充填部材とを含み、
前記充填部材が非発泡状態で充填されており、
前記絶縁基板は、ガラス基板であり、
前記充填部材は、ガラスからなり、
前記充填部材の軟化点が前記絶縁基板の軟化点より低く、
前記絶縁基板の主面に平行な方向において、前記絶縁基板の熱膨張係数を前記充填部材の熱膨張係数で除した値が、1.4〜2.0であることを特徴とする。
絶縁基板の厚さ方向に、前記絶縁基板の第1主面と前記絶縁基板の第2主面とを接続するためのスルーホールを形成し、
前記スルーホールの内壁と前記第1及び第2主面における前記スルーホールの開口部周囲とに導電膜を形成し、
前記スルーホールに充填部材を充填する回路基板の製造方法であって、
前記絶縁基板は、ガラス基板であり、
前記充填部材は、ガラスからなり、
前記充填部材の軟化点が前記絶縁基板の軟化点より低く、
前記絶縁基板の主面に平行な方向において、前記絶縁基板の熱膨張係数を前記充填部材の熱膨張係数で除した値が、1.4〜2.0であり、
前記充填部材を充填した後に、前記充填部材を加熱・加圧して、焼成することを特徴とする。
絶縁基板と、前記絶縁基板の厚さ方向に形成された、前記絶縁基板の第1主面と前記絶縁基板の第2主面とを接続するためのスルーホールとを含む回路基板と、
前記回路基板に搭載された電子素子と、
前記電子素子を覆う蓋体とを含む電子部品であって、
前記回路基板は、前記スルーホールの内壁と前記第1及び第2主面における前記スルーホールの開口部周囲とに形成された導電膜と、前記スルーホールに充填された充填部材とを含み、
前記充填部材が非発泡状態で充填されており、
前記絶縁基板は、ガラス基板であり、
前記充填部材は、ガラスからなり、
前記充填部材の軟化点が前記絶縁基板の軟化点より低く、
前記絶縁基板の主面に平行な方向において、前記絶縁基板の熱膨張係数を前記充填部材の熱膨張係数で除した値が、1.4〜2.0であることを特徴とする。
まず、本発明の第1実施形態について図面を参照して説明する。参照する図1は、本発明の第1実施形態に係る回路基板の断面図である。
次に、本発明の第2実施形態について図面を参照して説明する。参照する図3は、本発明の第2実施形態に係る電子部品の断面図である。第2実施形態に係る電子部品は、上述した第1実施形態に係る回路基板1を含む。なお、図3において、図1と同一の構成要素には同一の符号を付し、その説明を省略する場合がある。
2 電子部品
10 絶縁基板
10a 第1主面
10b 第2主面
11 スルーホール
12 第1導電膜
12a 電子素子接続電極
12b 接続導電膜
12c 外部接続電極
13 第2導電膜
14 充填部材
15 導電膜
16 プレス治具
20 電子素子
21 蓋体
21a 凹部
22 導電性接着剤
23 接着層
Claims (7)
- 絶縁基板と、前記絶縁基板の厚さ方向に形成された、前記絶縁基板の第1主面と前記絶縁基板の第2主面とを接続するためのスルーホールとを含む回路基板であって、
前記スルーホールの内壁と前記第1及び第2主面における前記スルーホールの開口部周囲とに形成された導電膜と、
前記スルーホールに充填された充填部材とを含み、
前記充填部材が非発泡状態で充填されており、
前記絶縁基板は、ガラス基板であり、
前記充填部材は、ガラスからなり、
前記充填部材の軟化点が前記絶縁基板の軟化点より低く、
前記絶縁基板の主面に平行な方向において、前記絶縁基板の熱膨張係数を前記充填部材の熱膨張係数で除した値が、1.4〜2.0であることを特徴とする回路基板。 - 前記スルーホールに充填された前記充填部材は、空孔率が20%以下である請求項1に記載の回路基板。
- 前記スルーホールは、前記第1主面から前記第2主面にかけてその径が漸次小さくなっている請求項1に記載の回路基板。
- 絶縁基板の厚さ方向に、前記絶縁基板の第1主面と前記絶縁基板の第2主面とを接続するためのスルーホールを形成し、
前記スルーホールの内壁と前記第1及び第2主面における前記スルーホールの開口部周囲とに導電膜を形成し、
前記スルーホールに充填部材を充填する回路基板の製造方法であって、
前記絶縁基板は、ガラス基板であり、
前記充填部材は、ガラスからなり、
前記充填部材の軟化点が前記絶縁基板の軟化点より低く、
前記絶縁基板の主面に平行な方向において、前記絶縁基板の熱膨張係数を前記充填部材の熱膨張係数で除した値が、1.4〜2.0であり、
前記充填部材を充填した後に、前記充填部材を加熱・加圧して、焼成することを特徴とする回路基板の製造方法。 - 前記スルーホールに、略球状の前記充填部材を充填する請求項4に記載の回路基板の製造方法。
- 前記スルーホールを形成する際、前記第1主面から前記第2主面にかけて前記スルーホールの径が漸次小さくなるように形成する請求項4に記載の回路基板の製造方法。
- 絶縁基板と、前記絶縁基板の厚さ方向に形成された、前記絶縁基板の第1主面と前記絶縁基板の第2主面とを接続するためのスルーホールとを含む回路基板と、
前記回路基板に搭載された電子素子と、
前記電子素子を覆う蓋体とを含む電子部品であって、
前記回路基板は、前記スルーホールの内壁と前記第1及び第2主面における前記スルーホールの開口部周囲とに形成された導電膜と、前記スルーホールに充填された充填部材とを含み、
前記充填部材が非発泡状態で充填されており、
前記絶縁基板は、ガラス基板であり、
前記充填部材は、ガラスからなり、
前記充填部材の軟化点が前記絶縁基板の軟化点より低く、
前記絶縁基板の主面に平行な方向において、前記絶縁基板の熱膨張係数を前記充填部材の熱膨張係数で除した値が、1.4〜2.0であることを特徴とする電子部品。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/010045 WO2006129354A1 (ja) | 2005-06-01 | 2005-06-01 | 回路基板とその製造方法及びこれを用いた電子部品 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006129354A1 JPWO2006129354A1 (ja) | 2008-12-25 |
JP4891235B2 true JP4891235B2 (ja) | 2012-03-07 |
Family
ID=37481291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007518827A Expired - Fee Related JP4891235B2 (ja) | 2005-06-01 | 2005-06-01 | 回路基板とその製造方法及びこれを用いた電子部品 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20090117336A1 (ja) |
JP (1) | JP4891235B2 (ja) |
CN (1) | CN101189921A (ja) |
WO (1) | WO2006129354A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5023738B2 (ja) * | 2007-02-28 | 2012-09-12 | 富士通株式会社 | プリント配線板の製造方法 |
JP4665959B2 (ja) | 2007-11-30 | 2011-04-06 | 日本電気株式会社 | 真空パッケージ |
JP5189378B2 (ja) * | 2008-02-18 | 2013-04-24 | セイコーインスツル株式会社 | 圧電振動子の製造方法 |
JP4809410B2 (ja) * | 2008-09-29 | 2011-11-09 | 日本電波工業株式会社 | 圧電デバイスとその製造方法 |
JP2010171536A (ja) * | 2009-01-20 | 2010-08-05 | Seiko Instruments Inc | 圧電振動子 |
WO2011073393A2 (en) * | 2009-12-18 | 2011-06-23 | Aerocrine Ab | Method for plugging a hole and a plugged hole |
JP5471987B2 (ja) * | 2010-09-07 | 2014-04-16 | 株式会社大真空 | 電子部品パッケージ用封止部材、電子部品パッケージ、及び電子部品パッケージ用封止部材の製造方法 |
JP5746352B2 (ja) * | 2010-09-23 | 2015-07-08 | クゥアルコム・メムス・テクノロジーズ・インコーポレイテッドQUALCOMM MEMS Technologies, Inc. | 集積化された受動素子と電力増幅器 |
US20120192928A1 (en) * | 2011-01-27 | 2012-08-02 | Mark Francis Krol | Laminated pv module package |
US8816505B2 (en) * | 2011-07-29 | 2014-08-26 | Tessera, Inc. | Low stress vias |
JP5705062B2 (ja) * | 2011-08-08 | 2015-04-22 | タイコエレクトロニクスジャパン合同会社 | コネクタ |
KR20150033979A (ko) * | 2013-09-25 | 2015-04-02 | 삼성전기주식회사 | 인터포저 기판 및 인터포저 기판 제조 방법 |
IT201700073501A1 (it) * | 2017-06-30 | 2018-12-30 | St Microelectronics Srl | Prodotto a semiconduttore e corrispondente procedimento |
US11152294B2 (en) * | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
US11760682B2 (en) | 2019-02-21 | 2023-09-19 | Corning Incorporated | Glass or glass ceramic articles with copper-metallized through holes and processes for making the same |
KR102653023B1 (ko) | 2019-03-12 | 2024-03-28 | 앱솔릭스 인코포레이티드 | 패키징 기판 및 이를 포함하는 반도체 장치 |
WO2020185020A1 (ko) | 2019-03-12 | 2020-09-17 | 에스케이씨 주식회사 | 유리를 포함하는 기판의 적재 카세트 및 이를 적용한 기판의 적재방법 |
US11967542B2 (en) | 2019-03-12 | 2024-04-23 | Absolics Inc. | Packaging substrate, and semiconductor device comprising same |
WO2020204473A1 (ko) | 2019-03-29 | 2020-10-08 | 에스케이씨 주식회사 | 반도체용 패키징 유리기판, 반도체용 패키징 기판 및 반도체 장치 |
EP3905323B1 (en) * | 2019-08-23 | 2024-08-14 | Absolics Inc. | Packaging substrate and semiconductor device comprising same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283834A (ja) * | 1992-03-10 | 1993-10-29 | Nec Toyama Ltd | 印刷配線板及びその製造方法 |
JPH07162132A (ja) * | 1993-12-07 | 1995-06-23 | Rohm Co Ltd | 絶縁層の形成方法 |
JPH0924500A (ja) * | 1995-07-13 | 1997-01-28 | Sumitomo Special Metals Co Ltd | 熱伝導複合材料の製造方法 |
JP2000299541A (ja) * | 1999-04-15 | 2000-10-24 | Ibiden Co Ltd | プリント配線基板 |
JP2000323843A (ja) * | 1999-03-09 | 2000-11-24 | Ngk Spark Plug Co Ltd | スルーホール充填用ペースト及びそれを用いた多層プリント配線板 |
WO2003007370A1 (en) * | 2001-07-12 | 2003-01-23 | Hitachi, Ltd. | Wiring glass substrate and method of manufacturing the wiring glass substrate, conductive paste and semiconductor module used for wiring glass substrate, and method of forming wiring substrate and conductor |
JP2003101181A (ja) * | 2001-09-26 | 2003-04-04 | Citizen Watch Co Ltd | 回路基板及びその製造方法ならびに電子装置 |
JP2003115658A (ja) * | 2001-10-05 | 2003-04-18 | Advantest Corp | 配線基板の製造方法、充填物挿入方法、配線基板、及び素子パッケージ |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4217837B4 (de) * | 1991-05-29 | 2006-04-27 | Mitsubishi Denki K.K. | Hermetisch abgeschlossenes Gehäuse |
KR0158469B1 (ko) * | 1992-10-15 | 1999-03-20 | 모리시타 요이찌 | 발진자 |
US5490965A (en) * | 1994-01-24 | 1996-02-13 | Hewlett-Packard Company | Method for closing holes in ceramic substrates |
US5660781A (en) * | 1994-06-28 | 1997-08-26 | Sumitomo Metal Industries, Ltd. | Process for preparing glass ceramic green sheets |
US5565262A (en) * | 1995-01-27 | 1996-10-15 | David Sarnoff Research Center, Inc. | Electrical feedthroughs for ceramic circuit board support substrates |
US5514451A (en) * | 1995-01-27 | 1996-05-07 | David Sarnoff Research Center, Inc. | Conductive via fill inks for ceramic multilayer circuit boards on support substrates |
JP3756041B2 (ja) * | 1999-05-27 | 2006-03-15 | Hoya株式会社 | 多層プリント配線板の製造方法 |
JP3594894B2 (ja) * | 2000-02-01 | 2004-12-02 | 新光電気工業株式会社 | ビアフィリングめっき方法 |
US6518514B2 (en) * | 2000-08-21 | 2003-02-11 | Matsushita Electric Industrial Co., Ltd. | Circuit board and production of the same |
US6429527B1 (en) * | 2001-01-17 | 2002-08-06 | International Business Corporation | Method and article for filling apertures in a high performance electronic substrate |
US6498381B2 (en) * | 2001-02-22 | 2002-12-24 | Tru-Si Technologies, Inc. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
US7345350B2 (en) * | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
JP4138641B2 (ja) * | 2003-12-16 | 2008-08-27 | 松下電器産業株式会社 | 回路基板とその製造方法 |
-
2005
- 2005-06-01 CN CN200580049959.3A patent/CN101189921A/zh active Pending
- 2005-06-01 WO PCT/JP2005/010045 patent/WO2006129354A1/ja active Application Filing
- 2005-06-01 JP JP2007518827A patent/JP4891235B2/ja not_active Expired - Fee Related
- 2005-06-01 US US11/916,210 patent/US20090117336A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283834A (ja) * | 1992-03-10 | 1993-10-29 | Nec Toyama Ltd | 印刷配線板及びその製造方法 |
JPH07162132A (ja) * | 1993-12-07 | 1995-06-23 | Rohm Co Ltd | 絶縁層の形成方法 |
JPH0924500A (ja) * | 1995-07-13 | 1997-01-28 | Sumitomo Special Metals Co Ltd | 熱伝導複合材料の製造方法 |
JP2000323843A (ja) * | 1999-03-09 | 2000-11-24 | Ngk Spark Plug Co Ltd | スルーホール充填用ペースト及びそれを用いた多層プリント配線板 |
JP2000299541A (ja) * | 1999-04-15 | 2000-10-24 | Ibiden Co Ltd | プリント配線基板 |
WO2003007370A1 (en) * | 2001-07-12 | 2003-01-23 | Hitachi, Ltd. | Wiring glass substrate and method of manufacturing the wiring glass substrate, conductive paste and semiconductor module used for wiring glass substrate, and method of forming wiring substrate and conductor |
JP2003101181A (ja) * | 2001-09-26 | 2003-04-04 | Citizen Watch Co Ltd | 回路基板及びその製造方法ならびに電子装置 |
JP2003115658A (ja) * | 2001-10-05 | 2003-04-18 | Advantest Corp | 配線基板の製造方法、充填物挿入方法、配線基板、及び素子パッケージ |
Also Published As
Publication number | Publication date |
---|---|
US20090117336A1 (en) | 2009-05-07 |
CN101189921A (zh) | 2008-05-28 |
WO2006129354A1 (ja) | 2006-12-07 |
JPWO2006129354A1 (ja) | 2008-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4891235B2 (ja) | 回路基板とその製造方法及びこれを用いた電子部品 | |
KR100545928B1 (ko) | 용량식 진공 측정 셀 | |
JP2008028297A (ja) | 静電チャック | |
US6689984B2 (en) | Susceptor with built-in electrode and manufacturing method therefor | |
WO1988005959A1 (en) | Ceramic substrate with conductively-filled vias and method for producing | |
JP5187148B2 (ja) | 半導体装置及びその製造方法 | |
JPWO2006025139A1 (ja) | 回路基板とその製造方法及びこれを用いた電子部品 | |
CN109979827A (zh) | 一种功率器件芯片封装方法 | |
JP2008218978A (ja) | 静電チャックとその製造方法 | |
JP6388274B2 (ja) | 電子部品装置の製造方法、及び電子部品装置 | |
JP4214068B2 (ja) | 多層ガラス基板の製造方法 | |
WO2004077632A1 (ja) | サージアブソーバ及びその製造方法 | |
WO2018190226A1 (ja) | 貫通孔の封止構造及び封止方法、並びに、貫通孔を封止するための転写基板 | |
JP2002208650A (ja) | 電子素子収容装置 | |
JP2015122413A (ja) | パッケージおよびその製造方法 | |
KR102102755B1 (ko) | 관통 구멍의 밀봉 구조 및 밀봉 방법, 그리고 관통 구멍을 밀봉하기 위한 전사 기판 | |
JP2006102876A (ja) | ウェハ封止部材 | |
JP2015080108A (ja) | パッケージの製造方法 | |
JP2002134659A (ja) | 電子素子用基板とその製造方法並びに電子素子とその製造方法 | |
JP2001326002A (ja) | 気密端子 | |
JP4138641B2 (ja) | 回路基板とその製造方法 | |
WO2006129848A1 (ja) | ガラス貫通配線基板の製造方法、ガラス貫通配線基板、並びにガラス貫通配線基板を用いたプローブカード及びパッケージング素子 | |
CN114163145B (zh) | 带金属电极的石英基底的封接方法及其专用夹具 | |
JP2004207539A (ja) | 電子部品収納用容器および電子装置 | |
CN110035629A (zh) | 采用纳米银浆对微波模块进行气密封盖的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110208 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110330 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110510 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110629 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111129 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111215 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141222 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |