JP5904556B2 - 無機インターポーザ上のパッケージ貫通ビア(tpv)構造およびその製造方法 - Google Patents
無機インターポーザ上のパッケージ貫通ビア(tpv)構造およびその製造方法 Download PDFInfo
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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Description
前述のように、ガラスインターポーザはシリコンに対して複数の優位点を有する。TSV(シリコン貫通ビア)およびTPV(ガラス貫通ビア)の電気挙動をシミュレーションによって研究した。TSVおよびTPVに対してシミュレーションした挿入損失描画から、ガラスインターポーザのTPVはシリコンインターポーザのTSVと比較すると、ごくわずかな電気信号損失しか有しないことが観測された。シリコンの伝導率はガラスよりも多少高いため、TPVに比べてTSVにおいてはるかに高い基板損失が生じる。ガラス上に作成したTPVの電気モデリングの結果を以下に示す。
4種類のTPVを研究、比較し、以下の表2に要約した。
ポリマ素材の役割は、ガラスインターポーザ表面の金属層と、ビアのコアの金属との間の応力除去バリアとしても作用することである。さらに、応力除去バリアはまた、アブレーション処理中に、ガラス表面に対するレーザの物理的影響を低減するのにも役立つ。従来のシステムでは、レーザまたは、酸などの他の素材除去手段を用いて貫通ビアを作成するときには、基板の上部は基板の下部よりも長時間にわたって、除去手段によって作用を受ける。この意図しない長時間の反応時間の結果として、基板の上部層の一部が継続して除去される。それにより、低ピッチビア、つまり、基板面に対して垂直未満の角度となる側壁を有するビアが生じる。低ピッチビアは、ビアを埋めるために多量の金属化を必要とし、したがってコストが高くなるだけではなく、低ピッチビアの寸法によって、基板の区域に配置できる貫通ビアの数が減少する。
175μmおよび500μm厚のBSG試料をCO2レーザアブレーションで処理した。CO2レーザの最初の結果によって、ビア端部に沿って微細な亀裂を有し、大きなビア直径(125μm直径)および先細りが強いビアプロファイルが示された。CO2レーザアブレーションによるビアの光学像および走査型電子顕微鏡(SEM)像を10(a)、(b)、(c)、(d)に示す。ビアの入口直径は、一般的に125μmであり、出口直径は一般的に50μmであり、TPVピッチは175μmであった。微細な亀裂はCO2Tレーザを用いることによって最小限となり、ピッチはわずかに大きくなり、欠損は減少した。図11aおよび11bはCO2TレーザでアブレーションしたBSGガラス試料におけるレーザの入口および出口の光学像である。
Claims (31)
- 上部部分を有するガラスインターポーザ内に壁を有する複数の貫通ビアと、
前記ガラスインターポーザの前記上部部分の少なくとも一部分上の応力除去バリアと、
前記応力除去層の少なくとも一部分上の金属化シード層と、
前記金属化シード層の少なくとも一部分上の伝導体であって、複数の金属化パッケージ貫通ビアを形成する前記複数の貫通ビアの少なくとも一部分を貫通する伝導体と、
を備えるマイクロ電子パッケージであって、
前記貫通ビアの少なくとも一部分は前記応力除去層または前記金属化シード層によって充填され、
前記貫通ビアの前記壁の側壁に前記応力除去層を形成した
ことを特徴とするマイクロ電子パッケージ。 - 前記応力除去バリアはポリマ膜を備える、請求項1に記載のマイクロ電子パッケージ。
- 前記ポリマ膜は、薄い乾燥膜を積層した誘電体を備える、請求項2に記載のマイクロ電子パッケージ。
- 前記ポリマ膜は、乾燥膜、液状被覆、または気相堆積薄膜として堆積する、請求項2に記載のマイクロ電子パッケージ。
- 前記応力除去バリアは、前記ガラスインターポーザの熱膨張係数と前記伝導体の熱膨張係数との間の熱膨張係数を有する、請求項1に記載のマイクロ電子パッケージ。
- 前記応力除去バリアは、前記ガラスインターポーザの底部部分の少なくとも一部分上にある、請求項1に記載のマイクロ電子パッケージ。
- 前記応力除去バリアは、前記ガラスインターポーザの前記貫通ビアの前記壁の少なくとも一部分上にある、請求項1に記載のマイクロ電子パッケージ。
- 前記応力除去バリアおよび前記金属化層は同一の素材を備える、請求項1に記載のマイクロ電子パッケージ。
- 前記応力除去バリアおよび前記金属化層は、パラジウム、ニッケル、ニッケル合金、および銅合金からなる群から選択される、請求項8に記載のマイクロ電子パッケージ。
- 前記応力除去バリアまたは前記金属化シード層によって充填されていない前記貫通ビアの残りの部分の少なくとも一部分は、充填剤によって充填される、請求項1に記載のマイクロ電子パッケージ。
- 前記充填剤は、空気、ポリマ、金属合金、およびそれらの任意の組み合わせからなる群から選択される、請求項10に記載のマイクロ電子パッケージ。
- 前記伝導体は少なくとも1つの連結装置を形成する、請求項1に記載のマイクロ電子パッケージ。
- ガラスインターポーザの上面の少なくとも一部分上のポリマと、
積層層の少なくとも一部分上の金属化シード層と、
を備えるマイクロ電子パッケージであって、
前記ポリマおよび前記ガラスインターポーザの少なくとも一部分を除去して貫通ビアを形成し、
前記貫通ビアの少なくとも一部分は、金属化層を形成する金属導体で充填され、前記金属化層の一部分を選択的に除去し、金属化パッケージ貫通ビアを形成する構成において、
前記貫通ビアの前記壁の側壁にポリマの層を形成した、マイクロ電子パッケージ。 - 前記インターポーザの底面の少なくとも一部分上に前記ポリマをさらに備える、請求項13に記載のマイクロ電子パッケージ。
- 側壁の少なくとも一部分上に前記金属化層をさらに備える、請求項13に記載のマイクロ電子パッケージ。
- 前記ポリマは樹脂で被膜した銅を備える、請求項13に記載のマイクロ電子パッケージ。
- 前記ポリマは、薄い乾燥膜を積層した誘電体を備える、請求項13に記載のマイクロ電子パッケージ。
- パッケージ貫通ビアをガラスインターポーザに製造する方法であって、
ポリマをガラスインターポーザの上面の少なくとも一部分上に積層し、
前記ポリマおよび前記ガラスインターポーザの少なくとも一部分を除去して貫通ビアを形成し、
前記貫通ビアの少なくとも一部分を金属導体で充填して金属化層を形成し、
前記金属化層の一部分を選択的に除去して金属化パッケージ貫通ビアを形成すること、
を備える構成において
前記貫通ビアの前記壁の側壁にポリマの層を形成することを含む、方法。 - 前記貫通ビアの少なくとも一部分を金属導体で充填する前に、前記積層層の少なくとも一部分上に金属化シード層を堆積することをさらに備える、請求項18に記載の方法。
- 前記インターポーザの底面の少なくとも一部分上に前記ポリマを積層することをさらに備える、請求項18に記載の方法。
- 前記上面の少なくとも一部分上に前記ポリマを積層することと、前記底面の少なくとも一部分上に前記ポリマを積層することを同時に行う、請求項20に記載の方法。
- 前記側壁の少なくとも一部分上に前記金属化層を堆積することをさらに備える、請求項18に記載の方法。
- 前記貫通ビアの少なくとも一部分を金属導体で充填して金属化層を形成することは、前記貫通ビアの上部部分を閉鎖することを含む、請求項18に記載の方法。
- 前記ポリマは樹脂で被膜された銅を備える、請求項18に記載の方法。
- 前記ポリマが誘電体層である、請求項18に記載の方法。
- 前記誘電体層が、当該誘電体を複数積層した層である、請求項25に記載の方法。
- 前記インターポーザおよび積層の少なくとも一部分の除去は、レーザまたは機械穿孔を用いることを備える、請求項18に記載の方法。
- 前記レーザは二酸化炭素レーザ、紫外線レーザまたはエキシマレーザである、請求項27に記載の方法。
- 前記金属化層の一部分を選択的に除去して金属化パッケージ貫通ビアを形成することは、少なくとも1つの連結装置を形成することをさらに備える、請求項18に記載の方法。
- インターポーザの少なくとも一部分を除去してくぼみを形成し、
前記くぼみを誘電体で充填し、
前記誘電体の少なくとも一部分を除去して少なくとも1つの高密度貫通ビアを形成し、
金属化シード層を積層層の少なくとも一部分に適用すること、
を備える方法であって、
金属化層は、少なくとも1つの貫通ビアの少なくとも一部分も充填し、
前記金属化層の一部分を選択的に除去して金属化パッケージ貫通ビアを形成する構成において
前記貫通ビアの前記壁の側壁にポリマの層を形成することを含む、方法。 - ポリマをインターポーザの上面および底面の少なくとも一部分に積層して誘電体層を形成し、
前記インターポーザおよび積層層の少なくとも一部分を除去してビアを形成し、
前記誘電体層を前記インターポーザの少なくとも一部分および前記ビアの少なくとも1つの側壁に適用し、
金属化シード層を前記積層層の少なくとも一部分および前記ビアの少なくとも1つの側壁に適用し、
前記ビアの少なくとも一部分を金属導体で充填して金属化層を形成し、
前記金属化層の一部分を選択的に除去してパッケージ貫通ビアを形成する方法。
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CN107663442A (zh) * | 2016-07-27 | 2018-02-06 | 株式会社Lg化学 | 光固化树脂组合物及其用途 |
CN107663442B (zh) * | 2016-07-27 | 2020-09-18 | 株式会社Lg化学 | 光固化树脂组合物及其用途 |
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JP2016154240A (ja) | 2016-08-25 |
JP2013521663A (ja) | 2013-06-10 |
US9275934B2 (en) | 2016-03-01 |
EP2543065A1 (en) | 2013-01-09 |
US20130119555A1 (en) | 2013-05-16 |
KR101825149B1 (ko) | 2018-02-02 |
KR20130038825A (ko) | 2013-04-18 |
WO2011109648A1 (en) | 2011-09-09 |
US20160141257A1 (en) | 2016-05-19 |
EP2543065A4 (en) | 2018-01-24 |
CN102947931A (zh) | 2013-02-27 |
US10672718B2 (en) | 2020-06-02 |
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