JP5451812B2 - Cvdエッチングおよび堆積シーケンスによりmosトランジスタ接合領域を形成する方法、および当該方法で形成されたトランジスタ - Google Patents
Cvdエッチングおよび堆積シーケンスによりmosトランジスタ接合領域を形成する方法、および当該方法で形成されたトランジスタ Download PDFInfo
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- Crystallography & Structural Chemistry (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
になされる。先ず、反応器を摂氏650度に保ったまま、チャンバに純粋塩素を一分につき5標準立方センチメータ(SCCM)〜10SCCMの速度で一時間にわたり流して基板120の箇所を除去あるいはエッチングすることで、接合領域270および280を形成する。接合領域270および280は1000オングストロームの深さまで形成される。
1.切子面220および230は、高い純度のせいで、接合位置においてエピタキシャル材料のよく定義された高品質界面となりうる。例えば、領域270および280の形成(切子面220および230を含む)および材料370および380の形成が上述のように単一のチャンバ内でなされることで、当初の基板のエピ層界面位置において(切子面220、230および材料370、380の間)不純物による汚染により(炭素、窒素、酸素の量が界面で減ることにより)界面抵抗が減ることがあり、これが、よりよい界面制御、より低いRexternalおよびより高い駆動電流に繋がることがある。同様に、このような形成により、材料370および380で界面不純物汚染が減り、材料370および380で、より高いドーパント汚染を起こすことがあり(例えば、ホウ素、アルミニウム、リン、ヒ素、および/またはアンチモン)、またソース/ドレイン領域自身内の抵抗が減ることがあり、故に、よりよい界面制御、より低いRexternalおよびより高い駆動電流に繋がることがある。
2.略54度の角度の切子面220および230を持つソース―ドレイン窪みの形状は、最適な電流波及を提供する。例えば、上述のように形成された切子面220および230の角度、配置、および平面特徴は、切子面および先端を通じて電流をより均等に容易に(より大きな総体規模および量で)波及させるのに(例えば、電流が材料370および380およびチャネル領域の間を流れること)最適な先端形状および配置を提供することがあり、チャネル領域および材料370、380間の領域の抵抗を低くし、より低いRexternalおよびより高い駆動電流に繋がる。
3.また略54度の角度の切子面220および230は、チャネル下で短絡、および短絡チャネル効果を引き起こしかねないドーパントのオーバーランに対して最大抵抗を提供する。窪みおよび先端領域376および486は、短絡チャネル効果あるいは短絡の惧れなく、チャネルのより近傍に配置することができる。
4.ミスフィット転位の形成によるひずみ緩和は、界面汚染が存在する場合に強化される。この発明は、緩和なしに堆積フィルムで、より高いひずみ利用ができる。例えば、領域270および280の形成(切子面220および230を含む)、および材料370および380の形成を上述のように単一のチャンバでなすことにより、材料370および380内でゲルマニウムあるいは炭素の濃度がより高くなり、チャネル内のひずみ量がより多くなり、トランジスタとして利用される間により高いキャリア移動性および駆動電流を生じる。
Claims (14)
- エッチングおよびデポジションによりMOSトランジスタの接合領域を形成する方法であって、
第1接合領域を形成すべくゲート電極の隣の基板の第1箇所と、前記基板に第2接合領域を形成すべく前記ゲート電極を介して前記第1箇所とは反対側に位置する前記基板の第2箇所とを除去する工程と、
前記第1接合領域と前記第2接合領域とに結晶質材料のエピタキシャル厚みを有する層を形成する工程とを含み、
前記除去する工程と前記形成する工程は同一のチャンバ内で前記チャンバの封止を破ることなく起こり、
前記除去する工程は、前記ゲート電極の隣の前記基板の第1側壁を前記第1接合領域内の前記基板の第1ベース表面に対して128度〜123度の間の一の角度で形成すべく、および、前記ゲート電極の隣の前記基板の第2側壁を前記第2接合領域内の前記基板の第2ベース表面に対して128度〜123度の間の一の角度で形成すべく、純粋塩素ガスで、エッチングすることを含む、方法。 - 前記除去する工程は、塩素ガス、塩酸ガス、水素ガス、および窒素ガスのうちの少なくともひとつでエッチングすることを含む、請求項1に記載の方法。
- 前記形成する工程は、前記第1側壁の表面および前記第2側壁の表面、および前記第1ベース表面および前記第2ベース表面に対してシリコン合金あるいはシリコン元素材料の厚みを有する層を化学結合すべく、シランガス、ジシランガス、ジクロロシランガス、ゲルマンガス、およびメチルシランガスのうちの少なくともひとつで選択的堆積を行うことを含む、請求項1または2に記載の方法。
- 前記除去する工程および前記形成する工程は、化学気相成長法(CVD)チャンバ、バッチ高真空(UHV)CVDチャンバ、コールド・ウォールUHVCVDチャンバ、低圧(LP)CVDチャンバ、高速熱的(RT)CVDチャンバ、減圧(RP)CVDチャンバ、大気圧(AP)CVDチャンバのうちのひとつの中で、前記チャンバが摂氏500〜800度の間の温度を持つとき、および1E−4Torr〜1000Torrの間の圧力である期間内に起こる、請求項1から3のいずれか一項に記載の方法。
- 前記除去する工程は、
前記ゲート電極の底面に対して略54.7度の角度を持つ第1切子面を規定する第1先端領域を形成する工程と、
前記底面に対して略54.7度の角度を持つ第2切子面を規定する第2先端領域を形成する工程と
を含む請求項1から4のいずれか一項に記載の方法。 - 前記第1切子面および第2切子面は、通例のミラー指数命名法(Miller index nomenclature)の面{1,1,1}を形成する、請求項5に記載の方法。
- 前記除去する工程は、前記ゲート電極と前記基板の頂面との間に形成されるゲート誘電体の底面の下にあり接触している前記第1切子面を形成することと、前記ゲート誘電体の前記底面の下にあり接触している前記第2切子面を形成することとを含む、請求項5または6に記載の方法。
- 前記第1切子面は、前記ゲート電極と前記基板の頂面との間に形成されるゲート誘電体の底面の下に形成される堆積材料から製造される第1先端を含み、前記第2切子面は、前記底面の下に形成される堆積材料から製造される第2先端を含む、請求項5から7のいずれか一項に記載の方法。
- 前記基板は、シリコン、多結晶シリコン、単結晶シリコンのうちひとつの材料を含み、
前記形成する工程は、基板材料の格子間隔よりも大きい格子間隔を持つホウ素でドープされたシリコンゲルマニウム、および、基板材料の前記格子間隔よりも小さい格子間隔を持つリンでドープされたシリコンカーボン合金のうちのひとつの厚みを有する層を形成することを含む、請求項5から8のいずれか一項に記載の方法。 - 前記形成する工程は、前記第1切子面と前記第2切子面との間の、前記基板のチャネルに圧縮性のひずみを生じさせるべく、ホウ素でドープされたシリコンゲルマニウムの十分な厚みを有する層を形成すること、および、前記第1切子面と前記第2切子面との間の、前記基板のチャネルに伸張性のひずみを生じさせるべく、リンでドープされたシリコンカーボン合金の一の十分な厚みを有する層を形成することのうちのひとつを含む、請求項9に記載の方法。
- 前記第1接合領域および前記第2接合領域は、前記第1接合領域および前記第2接合領域の間の前記基板の頂面の下方の深さを規定し、
前記形成する工程は、前記第1接合領域および前記第2接合領域内に配置される材料を形成する工程を含み、前記材料は前記深さの10〜50パーセントの間の距離で、前記頂面よりも前記基板の垂直方向における高さ位置が高い表面を持つ、請求項1から10のいずれか一項に記載の方法。 - 請求項1から11のいずれか一項に記載の方法で形成されたトランジスタであって、
基板と、
前記基板上のデバイスとを含み、前記デバイスは、
ゲート電極の隣の単結晶シリコン基板内の第1接合領域と、
前記ゲート電極の隣の前記基板中の異なる第2接合領域と、
前記第1接合領域と前記第2接合領域との間の前記シリコン基板の頂面の上のゲート誘電体層とを含み、
前記ゲート電極の隣の前記第1接合領域の第1切子面は、前記ゲート誘電体の底面に対して52度〜57度の間の一の角度を規定し、前記ゲート電極の隣の前記第2接合領域の第2切子面は、前記ゲート誘電体の前記底面に対して52度〜57度の間の一の角度を規定し、
前記第1切子面は、前記第1接合領域内の前記基板の第1ベース表面に対して128度〜123度の間の一の角度で形成される前記ゲート電極の隣の前記基板の第1側壁を形成し、
前記第2切子面は、前記第2接合領域内の前記基板の第1ベース表面に対して128度〜123度の間の一の角度で形成される前記ゲート電極の隣の前記基板の第2側壁を形成する、
トランジスタ。 - 前記第1接合領域および前記第2接合領域は、前記頂面の下方の深さを規定し、
前記トランジスタは、前記第1接合領域および前記第2接合領域内に配置される材料をさらに含み、前記材料は前記深さの10〜50パーセントの間の距離で、前記頂面よりも前記基板の垂直方向における高さ位置が高い表面を持つ、請求項12に記載のトランジスタ。 - 前記第1切子面および前記第2切子面は、前記ゲート電極と前記基板の頂面との間に形成されるゲート誘電体の底面の下に、接触して形成される請求項12または13に記載のトランジスタ。
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US7195985B2 (en) | 2007-03-27 |
TW200634987A (en) | 2006-10-01 |
DE112006000151T5 (de) | 2008-04-24 |
CN102709248A (zh) | 2012-10-03 |
DE112006000151B4 (de) | 2010-01-21 |
TWI297927B (en) | 2008-06-11 |
KR20070100787A (ko) | 2007-10-11 |
JP2012199557A (ja) | 2012-10-18 |
GB2437461B (en) | 2010-11-24 |
GB0714625D0 (en) | 2007-09-05 |
US7479432B2 (en) | 2009-01-20 |
CN102282657B (zh) | 2016-06-01 |
US20070105331A1 (en) | 2007-05-10 |
CN105895531A (zh) | 2016-08-24 |
US20060148151A1 (en) | 2006-07-06 |
GB2437461A (en) | 2007-10-24 |
CN102282657A (zh) | 2011-12-14 |
US7812394B2 (en) | 2010-10-12 |
WO2006104529A2 (en) | 2006-10-05 |
CN102709248B (zh) | 2016-01-20 |
JP5145049B2 (ja) | 2013-02-13 |
JP2008533695A (ja) | 2008-08-21 |
US20090039390A1 (en) | 2009-02-12 |
WO2006104529A3 (en) | 2010-09-02 |
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