JP5798477B2 - 半導体装置、及び半導体装置の作製方法 - Google Patents
半導体装置、及び半導体装置の作製方法 Download PDFInfo
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- JP5798477B2 JP5798477B2 JP2011281554A JP2011281554A JP5798477B2 JP 5798477 B2 JP5798477 B2 JP 5798477B2 JP 2011281554 A JP2011281554 A JP 2011281554A JP 2011281554 A JP2011281554 A JP 2011281554A JP 5798477 B2 JP5798477 B2 JP 5798477B2
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- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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- Semiconductor Integrated Circuits (AREA)
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Description
本実施の形態では、酸化物半導体をチャネルに用いたトランジスタ及びその作製方法について、図1乃至図4を用いて説明する。
(a―A)2+(b―B)2+(c―C)2≦r2
を満たすことをいい、rは、例えば、0.05とすればよい。他の酸化物でも同様である。
本実施の形態では、実施の形態1で開示したトランジスタとは異なる構成を有するトランジスタの例について説明する。
本実施の形態では、CAAC−OSからなる酸化物半導体膜の形成方法について、実施の形態1で開示した以外の方法について、以下に説明する。
本実施の形態では、実施の形態1及び実施の形態2に示した酸化物半導体を用いたトランジスタの電気特性への影響について、バンド図を用いて説明する。
図10(A)に半導体装置を構成する記憶素子(以下、メモリセルとも記す)の回路図の一例を示す。メモリセルは、酸化物半導体以外の材料をチャネル形成領域に用いたトランジスタ1160と酸化物半導体をチャネル形成領域に用いたトランジスタ1162によって構成される。
本実施の形態では、容量素子を有するメモリセルの回路図の一例を示す。図12(A)に示すメモリセル1170は、第1の配線SL、第2の配線BL、第3の配線S1、第4の配線S2と、第5の配線WLと、トランジスタ1171(第1のトランジスタ)と、トランジスタ1172(第2のトランジスタ)と、容量素子1173とから構成されている。トランジスタ1171は、酸化物半導体以外の材料をチャネル形成領域に用いており、トランジスタ1172はチャネル形成領域に酸化物半導体を用いている。
本実施の形態では、先の実施の形態に示すトランジスタを用いた半導体装置の例について、図13を参照して説明する。
酸化物半導体をチャネル形成領域に用いたトランジスタを少なくとも一部に用いてCPU(Central Processing Unit)を構成することができる。
101 基板
102 下地層
103 酸化物半導体層
104 ゲート絶縁層
105 ゲート電極
106 ドーパント
107 絶縁層
108 絶縁層
109 コンタクトホール
111 サイドウォール
112 チャネル保護層
113 絶縁層
115 バックゲート電極
140 トランジスタ
150 トランジスタ
160 トランジスタ
170 トランジスタ
180 トランジスタ
1100 メモリセル
1110 メモリセルアレイ
1111 配線駆動回路
1112 回路
1113 配線駆動回路
1120 メモリセルアレイ
1130 メモリセル
1131 トランジスタ
1132 容量素子
1140 メモリセルアレイ
1141 スイッチング素子
1142 記憶素子
1143 記憶素子群
1150 メモリセル
1151 トランジスタ
1152 トランジスタ
1153 トランジスタ
1154 トランジスタ
1155 トランジスタ
1156 トランジスタ
1160 トランジスタ
1161 トランジスタ
1162 トランジスタ
1163 トランジスタ
1164 トランジスタ
1170 メモリセル
1171 トランジスタ
1172 トランジスタ
1173 容量素子
1180 メモリセル
1181 トランジスタ
1182 トランジスタ
1183 容量素子
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
103a ソース領域
103b ドレイン領域
103c チャネル形成領域
103d 低濃度領域
103e 低濃度領域
105a ゲート電極
105b ゲート電極
110a ソース電極
110b ドレイン電極
Claims (15)
- 第1のゲート電極と、
前記第1のゲート電極上の、第1の絶縁膜と、
前記第1の絶縁膜上の、酸化物半導体層と、
前記酸化物半導体層上の、第2の絶縁膜と、
前記第2の絶縁膜上の、第2のゲート電極とを有し、
前記第1のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記第1のゲート電極と重なる領域を有し、
前記酸化物半導体層は、
第1の領域と、
第2の領域と、
前記第1の領域と、前記第2の領域との間のチャネル形成領域と、を有し、
前記第1の領域は、前記チャネル形成領域よりも高い濃度で窒素を有し、
前記第2の領域は、前記チャネル形成領域よりも高い濃度で窒素を有し、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、窒素を含むインジウムガリウム亜鉛酸化物、窒素を含むインジウム錫酸化物、窒素を含むインジウムガリウム酸化物、窒素を含むインジウム亜鉛酸化物、窒素を含む酸化錫、窒素を含むインジウム酸化物、又は金属窒化物を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置。 - 第1のゲート電極と、
前記第1のゲート電極上の、第1の絶縁膜と、
前記第1の絶縁膜上の、酸化物半導体層と、
前記酸化物半導体層上の、第2の絶縁膜と、
前記第2の絶縁膜上の、第2のゲート電極とを有し、
前記第1のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記第1のゲート電極と重なる領域を有し、
前記酸化物半導体層は、
第1の領域と、
第2の領域と、
前記第1の領域と、前記第2の領域との間のチャネル形成領域と、を有し、
前記第1の領域は、前記チャネル形成領域よりも高い濃度で窒素を有し、
前記第2の領域は、前記チャネル形成領域よりも高い濃度で窒素を有し、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、5eV以上の仕事関数を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置。 - 第1のゲート電極と、
前記第1のゲート電極上の、第1の絶縁膜と、
前記第1の絶縁膜上の、酸化物半導体層と、
前記酸化物半導体層上の、第2の絶縁膜と、
前記第2の絶縁膜上の、第2のゲート電極とを有し、
前記第1のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記第1のゲート電極と重なる領域を有し、
前記酸化物半導体層は、
第1の領域と、
第2の領域と、
前記第1の領域と、前記第2の領域との間のチャネル形成領域と、を有し、
前記第1の領域は、前記チャネル形成領域よりも高い濃度で窒素を有し、
前記第2の領域は、前記チャネル形成領域よりも高い濃度で窒素を有し、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、前記酸化物半導体層が有する窒素より高い濃度で窒素を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置。 - 第1のゲート電極と、
前記第1のゲート電極上の、第1の絶縁膜と、
前記第1の絶縁膜上の、酸化物半導体層と、
前記酸化物半導体層上の、第2の絶縁膜と、
前記第2の絶縁膜上の、第2のゲート電極とを有し、
前記第1のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記第1のゲート電極と重なる領域を有し、
前記酸化物半導体層は、
第1の領域と、
第2の領域と、
前記第1の領域と、前記第2の領域との間のチャネル形成領域と、を有し、
前記第1の領域は、前記チャネル形成領域よりも高い濃度で燐を有し、
前記第2の領域は、前記チャネル形成領域よりも高い濃度で燐を有し、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、窒素を含むインジウムガリウム亜鉛酸化物、窒素を含むインジウム錫酸化物、窒素を含むインジウムガリウム酸化物、窒素を含むインジウム亜鉛酸化物、窒素を含む酸化錫、窒素を含むインジウム酸化物、又は金属窒化物を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置。 - 第1のゲート電極と、
前記第1のゲート電極上の、第1の絶縁膜と、
前記第1の絶縁膜上の、酸化物半導体層と、
前記酸化物半導体層上の、第2の絶縁膜と、
前記第2の絶縁膜上の、第2のゲート電極とを有し、
前記第1のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記酸化物半導体層と重なる領域を有し、
前記第2のゲート電極は、前記第1のゲート電極と重なる領域を有し、
前記酸化物半導体層は、
第1の領域と、
第2の領域と、
前記第1の領域と、前記第2の領域との間のチャネル形成領域と、を有し、
前記第1の領域は、前記チャネル形成領域よりも高い濃度で燐を有し、
前記第2の領域は、前記チャネル形成領域よりも高い濃度で燐を有し、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、5eV以上の仕事関数を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記酸化物半導体層は、Inと、Gaと、Znとを有することを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記酸化物半導体層は、前記酸化物半導体層の表面の法線ベクトルに概略平行な方向にc軸が揃った結晶を有することを特徴とする半導体装置。 - 請求項7において、
前記酸化物半導体層は、前記結晶を複数有し、
透過型電子顕微鏡では、前記結晶の粒界は確認されないことを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一において、
前記第1の領域の厚さは、前記チャネル形成領域の厚さより薄く、
前記第2の領域の厚さは、前記チャネル形成領域の厚さより薄いことを特徴とする半導体装置。 - 第1のゲート電極を形成し、
前記第1のゲート電極上に、第1の絶縁膜を形成し、
前記第1の絶縁膜上であって、前記第1のゲート電極と重なる領域に、酸化物半導体層を形成し、
前記酸化物半導体層上に、第2の絶縁膜を形成し、
前記第2の絶縁膜上であって、前記酸化物半導体層と重なる領域に、第2のゲート電極を形成し、
前記第2のゲート電極をマスクとして、前記酸化物半導体層に窒素、又は燐を導入して、第1の領域、第2の領域、及びチャネル形成領域を形成する半導体装置の作製方法であって、
前記導入する手段に、イオンドーピング法又はイオンインプランテーション法を用い、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、窒素を含むインジウムガリウム亜鉛酸化物、窒素を含むインジウム錫酸化物、窒素を含むインジウムガリウム酸化物、窒素を含むインジウム亜鉛酸化物、窒素を含む酸化錫、窒素を含むインジウム酸化物、又は金属窒化物を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置の作製方法。 - 第1のゲート電極を形成し、
前記第1のゲート電極上に、第1の絶縁膜を形成し、
前記第1の絶縁膜上であって、前記第1のゲート電極と重なる領域に、酸化物半導体層を形成し、
前記酸化物半導体層上に、第2の絶縁膜を形成し、
前記第2の絶縁膜上であって、前記酸化物半導体層と重なる領域に、第2のゲート電極を形成し、
前記第2のゲート電極をマスクとして、前記酸化物半導体層に窒素、又は燐を導入して、第1の領域、第2の領域、及びチャネル形成領域を形成する半導体装置の作製方法であって、
前記導入する手段に、イオンドーピング法又はイオンインプランテーション法を用い、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、5eV以上の仕事関数を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置の作製方法。 - 第1のゲート電極を形成し、
前記第1のゲート電極上に、第1の絶縁膜を形成し、
前記第1の絶縁膜上であって、前記第1のゲート電極と重なる領域に、酸化物半導体層を形成し、
前記酸化物半導体層上に、第2の絶縁膜を形成し、
前記第2の絶縁膜上であって、前記酸化物半導体層と重なる領域に、第2のゲート電極を形成し、
前記第2のゲート電極をマスクとして、前記酸化物半導体層に窒素、又は燐を導入して、第1の領域、第2の領域、及びチャネル形成領域を形成する半導体装置の作製方法であって、
前記導入する手段に、プラズマ処理を用い、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、窒素を含むインジウムガリウム亜鉛酸化物、窒素を含むインジウム錫酸化物、窒素を含むインジウムガリウム酸化物、窒素を含むインジウム亜鉛酸化物、窒素を含む酸化錫、窒素を含むインジウム酸化物、又は金属窒化物を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置の作製方法。 - 第1のゲート電極を形成し、
前記第1のゲート電極上に、第1の絶縁膜を形成し、
前記第1の絶縁膜上であって、前記第1のゲート電極と重なる領域に、酸化物半導体層を形成し、
前記酸化物半導体層上に、第2の絶縁膜を形成し、
前記第2の絶縁膜上であって、前記酸化物半導体層と重なる領域に、第2のゲート電極を形成し、
前記第2のゲート電極をマスクとして、前記酸化物半導体層に窒素、又は燐を導入して、第1の領域、第2の領域、及びチャネル形成領域を形成する半導体装置の作製方法であって、
前記導入する手段に、プラズマ処理を用い、
前記第2のゲート電極は、第1の層と、前記第1の層上の第2の層とを有し、
前記第1の層は、5eV以上の仕事関数を有し、
前記第2の層は、アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステン、ネオジム、又はスカンジウムを有することを特徴とする半導体装置の作製方法。 - 請求項12又は請求項13において、
前記第1のゲート電極を形成する基板を用意し、
前記基板にバイアスを印加しながら、前記窒素、又は前記燐を導入することを特徴とする半導体装置の作製方法。 - 請求項10乃至請求項14のいずれか一において、
前記第1の領域上の第2の絶縁膜、及び前記第2の領域上の第2の絶縁膜を除去した後に、前記窒素、又は前記燐を導入することを特徴とする半導体装置の作製方法。
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TW201717405A (zh) | 2017-05-16 |
JP2019024136A (ja) | 2019-02-14 |
US20120161126A1 (en) | 2012-06-28 |
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TW201234598A (en) | 2012-08-16 |
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JP2017130691A (ja) | 2017-07-27 |
US20150053977A1 (en) | 2015-02-26 |
JP2023133401A (ja) | 2023-09-22 |
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JP2022111185A (ja) | 2022-07-29 |
JP7083881B2 (ja) | 2022-06-13 |
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