CN110993695B - Gsd tft器件及其制作方法 - Google Patents

Gsd tft器件及其制作方法 Download PDF

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CN110993695B
CN110993695B CN201911092698.3A CN201911092698A CN110993695B CN 110993695 B CN110993695 B CN 110993695B CN 201911092698 A CN201911092698 A CN 201911092698A CN 110993695 B CN110993695 B CN 110993695B
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layer
gate insulating
disposed
tft device
electrode
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CN110993695A (zh
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唐甲
徐源竣
张晓星
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Abstract

一种GSD TFT器件包含一基板,一遮光金属层设置于所述基板上,一缓冲层设置于所述遮光金属层和所述基板上,一有源层设置于所述缓冲层上,且所述有源层包含一导体化有源区,一栅极绝缘层设置于所述有源层和所述缓冲层上,且所述栅极绝缘层包含多个栅极绝缘开口,所述多个栅极绝缘开口的宽度小于所述导体化有源区的宽度,一第一栅极设置于所述遮光金属层和所述栅极绝缘层上,一第二栅极设置于所述栅极绝缘层上,一源极设置于所述遮光金属层、所述缓冲层、所述导体化有源区和所述栅极绝缘层上,一漏极设置于所述栅极绝缘层和所述导体化有源区上。

Description

GSD TFT器件及其制作方法
【技术领域】
本揭示涉及显示技术领域,特别涉及一种GSD TFT器件及其制作方法。
【背景技术】
目前上闸极结构薄膜电晶体(Top-gate Thin Film Transistor,Top-gate TFT)的制程由于结构复杂,层数较多。每增加一道阵列制程,不仅增加了时间成本、物料成本,也同时降低良率。因此需减少制程,提出栅极、源极、漏极同层(Gate Source Drain oneLayer Thin Film Transistor,GSD one Layer TFT)的新制程。
虽然与Top-gate TFT制程差异较大,特别是有源层在制程中受到环境的挑战,GSD材料为低阻抗金属,一般是厚度在3000至6000埃的铜或其合金,无法干蚀刻。然而,在湿蚀刻时,金属蚀刻液与铟镓锌氧化物(Indium Gallium Zinc Oxide,IGZO)持续接触,IGZO的膜厚、阻抗等严重受损,导致源极/漏极与IGZO无法导通,从而TFT器件的功能无法达成。
基于以上,本发明主要提出了GSD one Layer TFT中源极/漏极与IGZO边触设计,从而保证GSD TFT新制程能够保证器件功能正常,且能实现氧化薄膜电晶体的量产化。
【发明内容】
为解决上述技术问题,以及栅极绝缘层开孔,即源极/漏极与有源层的搭接,其开孔长度大于导体化有源层的宽度,使得在湿蚀刻时,蚀刻液会破坏有源层,使得有源层阻抗增大且膜层缺失,从而造成TFT功能异常。
本发明提供一种GSD TFT器件及其制作方法。根据本发明的一实施例,揭示一种GSD TFT器件,其特征在于,包含一基板,一遮光金属层,所述遮光金属层设置于所述基板上,一缓冲层,所述缓冲层设置于所述遮光金属层和所述基板上,一有源层,所述有源层设置于所述缓冲层上,且所述有源层包含一导体化有源区,一栅极绝缘层,所述栅极绝缘层设置于所述有源层和所述缓冲层上,且所述栅极绝缘层包含多个栅极绝缘开口,所述多个栅极绝缘开口的宽度小于所述导体化有源区的宽度,一第一栅极,所述第一栅极设置于所述遮光金属层和所述栅极绝缘层上,一第二栅极,所述第二栅极设置于所述栅极绝缘层上,一源极,所述源极设置于所述遮光金属层、所述缓冲层、所述导体化有源区和所述栅极绝缘层上,一漏极,所述漏极设置于所述栅极绝缘层和所述导体化有源区上。
根据本发明的其中一个方面,所述GSD TFT器件包含一塑胶层,所述塑胶层设置于所述缓冲层、所述有源层、所述导体化有源区、所述栅极绝缘层、所述第一栅极、所述第二栅极、所述源极和所述漏极。
根据本发明的其中一个方面,所述GSD TFT器件包含一彩色滤光片,所述彩色滤光片设置于所述塑胶层上。
根据本发明的其中一个方面,所述GSD TFT器件包含一有机材料层,所述有机材料层设置于所述塑胶层和所述彩色滤光片上。
根据本发明的其中一个方面,所述GSD TFT器件包含一阳极电极,所述阳极电极设置于所述源极、所述塑胶层和所述有机材料层上。
根据本发明的其中一个方面,所述GSD TFT器件包含一像素界定层,所述像素界定层设置于所述有机材料层和所述阳极电极上。
根据本发明的其中一个方面,所述GSD TFT器件包含一透明电容,所述透明电容设置于所述基板上,且其材质为氧化铟锡或氧化铟镓锌,增加开口率。
根据本发明的其中一个方面,所述GSD TFT器件包含一非透明电容,所述非透明电容设置于所述基板上,且其材质为遮光金属,降低开口率。
根据本发明的其中一个方面,所述像素界定层110其为疏水性,其材质为光阻胶,和非疏水性,其材质为氧化硅、氮化硅或氮氧化硅。
根据本发明的一实施例,揭示一种GSD TFT器件的制作方法,其特征在于,包含提供一基板,设置一遮光金属层于所述基板上,设置一缓冲层于所述遮光金属层和所述基板上,沉积一有源层于所述缓冲层上,并导体化部份所述有源层形成一导体化有源区,沉积一栅极绝缘层于所述有源层和所述缓冲层上。
进一步,蚀刻所述栅极绝缘层形成多个栅极绝缘开口,所多个述栅极绝缘开口宽度小于所述导体化有源区的宽度,沉积一金属层于所述遮光金属层、所述栅极绝缘层和所述导体化有源区上,蚀刻所述金属层形成一第一栅极、一第二栅极、一源极和一漏极,蚀刻所述栅极绝缘层,并导体化所述栅极绝缘层周围部份的所述有源层。
根据上述发明内容,本发明提出了一种GSD TFT器件及其制作方法,由于所述栅极绝缘层开口的宽度小于导体化的有源区的宽度,使得GSD金属层在进行湿蚀刻时,虽然部份的IGZO被破坏,但栅极绝缘层开口附近的IGZO依然存在,从而达到源极/漏极与IGZO形成边触。
因此,本发明主要提出了GSD one Layer TFT中源极/漏极与IGZO边触设计,从而保证GSD TFT新制程能够保证器件功能正常,且与Top-gate TFT制程相比,节省一次金属成膜、光刻、蚀刻及介电质层,大大节省成本,实现氧化薄膜电晶体的量产化。
【附图说明】
图1为本发明的GSD TFT器件的结构示意图;
图2为本发明的栅极绝缘层蚀刻示意图;
图3为本发明图2的A区域的俯视图;
图4(a)至图4(b)为本发明的GSD制作流程图;
图5为本发明图4(b)的B区域的俯视图。
【具体实施方式】
在一实施例中,如图1所示,一种GSD TFT器件包含一基板10,一遮光金属层20,所述遮光金属层20设置于所述基板10上,一缓冲层30,所述缓冲层30设置于所述遮光金属层20和所述基板10上,一有源层40,所述有源层40设置于所述缓冲层30上,且所述有源层40包含一导体化有源区41,一栅极绝缘层50,所述栅极绝缘层50设置于所述有源层40和所述缓冲层30上,且所述栅极绝缘层50包含多个栅极绝缘开口51。所述多个栅极绝缘开口51的宽度小于所述导体化有源区41的宽度。一第一栅极61,所述第一栅极61设置于所述遮光金属层20和所述栅极绝缘层50上,一第二栅极62,所述第二栅极62设置于所述栅极绝缘层50上,一源极63,所述源极63设置于所述遮光金属层20、所述缓冲层30、所述导体化有源区41和所述栅极绝缘层50上,一漏极64,所述漏极64设置于所述栅极绝缘层50上和所述导体化有源区41上。
在一实施例中,如图1所示,所述GSD TFT器件包含一塑胶层70,所述塑胶层70设置于所述缓冲层30、所述有源层40、所述导体化有源区41、所述栅极绝缘层50、所述第一栅极61、所述第二栅极62、所述源极63和所述漏极64。
在一实施例中,如图1所示,所述GSD TFT器件包含一彩色滤光片90,所述彩色滤光片90设置于所述塑胶层70上。
在一实施例中,如图1所示,所述GSD TFT器件包含一有机材料层80,所述有机材料层80设置于所述塑胶层70和所述彩色滤光片90上。
在一实施例中,如图1所示,所述GSD TFT器件包含一阳极电极100,所述阳极电极100设置于所述源极63、所述塑胶层70和所述有机材料层80上。
在一实施例中,如图1所示,所述GSD TFT器件包含一像素界定层110,所述像素界定层110设置于所述有机材料层80和所述阳极电极100上。
在一实施例中,如图1所示,所述GSD TFT器件包含一透明电容120,所述透明电容120设置于所述基板10上,且其材质为氧化铟锡或氧化铟镓锌,增加开口率。
在一实施例中,如图1所示,所述GSD TFT器件包含一非透明电容120,所述非透明电容120设置于所述基板10上,且其材质为遮光金属,降低开口率。
在一实施例中,所述像素界定层110其为疏水性,其材质为光阻胶,和非疏水性,其材质为氧化硅、氮化硅或氮氧化硅。
在一实施例中,如图2所示,揭示一种GSD TFT器件的制作方法包含提供一基板10,设置一遮光金属层20于所述基板10上,设置一缓冲层30于所述遮光金属层20和所述基板10上,沉积一有源40层于所述缓冲层30上,并导体化部份所述有源层形成一导体化有源区41,沉积一栅极绝缘层50于所述有源层40和所述缓冲层30上。
进一步,如图3所示,蚀刻所述栅极绝缘层50形成多个栅极绝缘开口51,所述多个栅极绝缘开口51的宽度小于所述导体化有源区41的宽度。
进一步,如图4(a)所示,沉积一金属层60于所述遮光金属层20、所述栅极绝缘层50、所述导体化有源区41上。
进一步,如图4(b)所示,湿蚀刻所述金属层60形成一第一栅极61、一第二栅极62、一源极63和一漏极64,同时部分的IGZO被破坏,但所述多个栅极绝缘开口51周围仍存在部分的IGZO。
进一步,如图5所示,进行自我对准,完成一具有奈米线信道之场效晶体管组件,干蚀刻所述多个栅极绝缘开口51周围的栅极绝缘层50,并导体化所述多个栅极绝缘开口51周围仍存在部分的所述有源层40。
所述多个栅极绝缘开口51存在部分导体化的IGZO,实现源极/漏极与IGZO形成边触,是本发明的关键技术,此外,使作为透明电容一极的IGZO阻抗降低。
以上仅是本揭示的优选实施方式,应当指出,对于本领域普通技术人员,在不脱离本揭示原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本揭示的保护范围。

Claims (10)

1.一种栅极及源漏极同层的TFT器件,其特征在于,包含:
一基板;
一遮光金属层,所述遮光金属层设置于所述基板上;
一缓冲层,所述缓冲层设置于所述遮光金属层和所述基板上;
一有源层,所述有源层设置于所述缓冲层上,且所述有源层包含一导体化有源区;
一栅极绝缘层,所述栅极绝缘层设置于所述有源层和所述缓冲层上,且所述栅极绝缘层包含多个栅极绝缘开口;
所述多个栅极绝缘开口的宽度小于所述导体化有源区的宽度;
一第一栅极,所述第一栅极设置于所述遮光金属层和所述栅极绝缘层上;
一第二栅极,所述第二栅极设置于所述栅极绝缘层上;
一源极,所述源极设置于所述遮光金属层、所述缓冲层、所述导体化有源区和所述栅极绝缘层上;
一漏极,所述漏极设置于所述栅极绝缘层和所述导体化有源区上;
其中,所述多个栅极绝缘开口的周围设置有部分导体化的有源层,所述源极和所述漏极与所述栅极绝缘开口周围的导体化的有源层接触。
2.如权利要求1所述的TFT器件,其特征在于,包含一塑胶层,所述塑胶层设置于所述缓冲层、所述有源层、所述导体化有源区、所述栅极绝缘层、所述第一栅极、所述第二栅极、所述源极和所述漏极。
3.如权利要求2所述的TFT器件,其特征在于,包含一彩色滤光片,所述彩色滤光片设置于所述塑胶层上。
4.如权利要求3所述的TFT器件,其特征在于,包含一有机材料层,所述有机材料层设置于所述塑胶层和所述彩色滤光片上。
5.如权利要求4所述的TFT器件,其特征在于,包含一阳极电极,所述阳极电极设置于所述源极、所述塑胶层和所述有机材料层上。
6.如权利要求5所述的TFT器件,其特征在于,包含一像素界定层,所述像素界定层设置于所述有机材料层和所述阳极电极上。
7.如权利要求6所述的TFT器件,其特征在于,所述像素界定层的材料为疏水性材料或非疏水性材料。
8.如权利要求1所述的TFT器件,其特征在于,包含一透明电容,所述透明电容设置于所述基板和所述缓冲层上,且其材质为氧化铟锡或氧化铟镓锌。
9.如权利要求1所述的TFT器件,其特征在于,包含一非透明电容,所述非透明电容设置于所述基板和所述缓冲层上,且其材质为遮光金属。
10.一种栅极及源漏极同层的TFT器件的制作方法,其特征在于,包含:
提供一基板;
设置一遮光金属层于所述基板上;
设置一缓冲层于所述遮光金属层和所述基板上;
沉积一有源层于所述缓冲层上,并导体化部份所述有源层形成一导体化有源区;
沉积一栅极绝缘层于所述有源层和所述缓冲层上;
蚀刻所述栅极绝缘层形成多个栅极绝缘开口;
所多个述栅极绝缘开口宽度小于所述导体化有源区的宽度;
沉积一金属层于所述遮光金属层、所述栅极绝缘层和所述导体化有源区上;
蚀刻所述金属层形成一第一栅极、一第二栅极、一源极和一漏极,同时蚀刻与所述栅极绝缘开口对应的所述有源层;
蚀刻所述栅极绝缘开口周围的所述栅极绝缘层,并导体化所述栅极绝缘层周围部份的所述有源层,以使所述源极和所述漏极与所述栅极绝缘开口周围的导体化的有源层接触。
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