CN112420741B - 一种阵列基板及其制备方法、显示面板 - Google Patents

一种阵列基板及其制备方法、显示面板 Download PDF

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CN112420741B
CN112420741B CN202011223897.6A CN202011223897A CN112420741B CN 112420741 B CN112420741 B CN 112420741B CN 202011223897 A CN202011223897 A CN 202011223897A CN 112420741 B CN112420741 B CN 112420741B
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卓毅
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Abstract

本发明公开了一种阵列基板及其制备方法、显示面板，阵列基板包括基板；遮光金属层，设于所述基板上；缓冲层，设于所述基板上且覆盖所述遮光金属层；有源层，设于所述缓冲层上，且对应所述遮光金属层，有源层包括导体化有源区；绝缘层，间隔设于所述基板上，且部分覆盖所述有源层；有源层开孔，设于所述有源层上；以及若干金属单元，设于所述绝缘层上，且与所述有源层连接；其中，所述有源层开孔与所述金属单元之间具有一间隙。

Description

一种阵列基板及其制备方法、显示面板
技术领域
本申请涉及显示领域，具体涉及一种阵列基板及其制备方法、显示面板。
背景技术
Top-gate Self-align结构的Oxide TFT技术中，为了避免TFT器件短路，自对准工艺中需要栅极金属与栅极绝缘层的线宽存在一定的偏移(offset)，另外栅电极和源极/漏极电极会通过2道光罩制程实现。为了缩短制程时间，降低成本，可以通过1道光罩制程制作栅极，源极，漏极电极(可称为GSD技术)，但采用这种技术时，除了栅极，源极/漏极电极同时经历了自对准工艺，上述Offset的存在使得氧化物层导体化区域变小，容易导致源漏电极与氧化物沟道之间存在电阻较高的氧化物部分。
发明内容
为了解决上述技术问题，本发明提供了一种阵列基板及其制备方法、显示面板，用以解决现有技术中由于自对准工艺导致有源层导体化区域过小，从而造成源漏极与沟道之间电阻变大的技术问题。
解决上述问题的技术方案是：本发明提供了一种阵列基板，包括基板；遮光金属层，设于所述基板上；缓冲层，设于所述基板上且覆盖所述遮光金属层；有源层，设于所述缓冲层上，且对应所述遮光金属层，所述有源层包括导体化有源区；绝缘层，间隔设于所述基板上，且部分覆盖所述有源层；有源层开孔，设于所述有源层上；以及若干金属单元，设于所述绝缘层上，且与所述有源层连接；其中，所述有源层开孔与所述金属单元之间具有一间隙。
进一步的，所述金属单元包括栅极，设于绝缘层上；以及源漏极，设于一绝缘层上，位于所述栅极两侧，且与所述有源层连接。
进一步的，还包括缓冲层凹槽，下凹于所述缓冲层，且对应所述有源层开孔；所述缓冲层凹槽位于所述栅极与源漏极之间。
进一步的，所述缓冲层凹槽尺寸与有源层开孔尺寸的相等。
进一步的，所述导体化有源区面积占所述有源层面积的60％～90％。
本发明还提供了一种阵列基板的制备方法，包括以下步骤：提供一基板；在所述基板上制备遮光金属层；在所述基板上制备缓冲层，所述缓冲层覆盖所述遮光金属层；在所述缓冲层上沉积一层半导体材料，形成有源层；在所述缓冲层上沉积一层绝缘材料，形成覆盖所述半导体层的绝缘层；在所述绝缘层对应所述有源层的位置刻蚀绝缘层开孔；将所述基板进行整面等离子处理，绝缘层开孔对应的有源层形成第一导体化区；在所述绝缘层上沉积一层金属材料，形成金属层；通过黄光工艺刻蚀所述金属层形成栅极和源漏极，其中所述源漏极与所述第一导体化区连接，刻蚀所述第一导体化区形成有源层开孔；采用自对准工艺，保留栅极和源漏极下方的绝缘层，去除绝缘层其他裸露的部分；将所述基板进行整面等离子处理，部分有源层形成导体化有源区。
进一步的，所述金属材料包括Mo，Al，Cu，Ti中的至少一种。
进一步的，采用酸性刻蚀液刻蚀所述金属层，其中，所述酸性刻蚀液的PH值大于5.0。
进一步的，阵列基板的制备方法还包括以下步骤：在所述栅极、源漏极、和所述有源层上制备钝化层；在所述钝化层对应所述源漏极处刻蚀通孔；在所述钝化层上制备像素电极，所述像素电极填充所述通孔并连接至所述源漏极。
本发明还提供了一种显示面板，包括所述阵列基板。
本发明的有益效果在于，本发明的一种阵列基板及其制备方法、显示面板，有源层开孔与源漏电极之间具有一间隙，即源漏电极与有源层开孔之间仍具有一定宽度的导体化有源区，使得电流能够通过电阻较低的导体化有源区传输，避免电流经过电阻值较高区域，采用两次等离子处理，使得有源层导体化区域增大，减少其非导体化区域，降低了源漏极与非导体化区域的阻值。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是实施例中阵列基板结构示意图。
图2是实施例中遮光金属层结构示意图。
图3是实施例中有源层结构示意图。
图4是实施例中绝缘层结构示意图。
图5是实施例中第一开孔结构示意图。
图6是实施例中栅极和源漏极结构示意图。
图7是实施例中第一开孔平面结构图。
图8是实施例中有源层开孔结构图。
图9是实施例中自对准工艺步骤后的阵列基板结构图。
图10是实施例中阵列基板制备步骤流程图。
图中标号
基板110； 遮光金属层120；
缓冲层130； 有源层140；
绝缘层150； 栅极160；
源漏极170； 钝化层180；
像素电极190； 第一开孔151；
导体化有源区141； 有源层开孔142。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
实施例
图1是实施例中阵列基板结构示意图。如图1所示，本实施例提供了一种显示面板，包括阵列基板，所述阵列基板包括基板110、遮光金属层120、缓冲层130、有源层140、绝缘层150、栅极160、源漏极170、钝化层180以及像素电极190。
基板110为硬质基板，一般为玻璃基板，起到支撑作用及衬底作用，同时可以隔绝外界水汽。
图2是实施例中遮光金属层结构示意图。如图2所示，遮光金属层120设于基板110的上表面，遮光金属层120的材质为遮光材料，所述遮光材料为金属，包括：钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)等，或者是合金，遮光金属层120的厚度为500埃米～2000埃米，遮光金属层120起到遮光作用。
缓冲层130设于遮光层120及基板1的上表面，起到缓冲的作用，缓冲层130的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物，或是多层结构，缓冲层130的厚度为1000埃米～5000埃米。
图3是实施例中有源层结构示意图。如图3所示，有源层140设于缓冲层130的上表面，有源层140的材质为半导体材料，所述半导体材料包括铟镓锌氧化物(IGZO)、铟镓钛氧化物(IZTO)，铟镓锌钛氧化物(IGZTO)，有源层140的厚度为100埃米～1000埃米。有源层140设于遮光层120的上方，即有源层140与遮光层120相对设置，有源层140给显示面板提供电路支持。
图4是实施例中绝缘层结构示意图。如图4所示，绝缘层150设于有源层140的上表面，绝缘层150的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构，绝缘层150的厚度为1000埃米～3000埃米。绝缘层150与有源层140相对设置，绝缘层150起到绝缘的作用，防止显示面板内部的各线路之间短路。
本实施例中，通过GSD技术同时制备栅极160和源漏极170，即将栅极160和源漏极170制备在同一层上，为了防止栅极160和源漏极170相互串扰，需要将栅极160和源漏极170彼此隔离。
图5是实施例中第一开孔结构示意图，图7是实施例中第一开孔平面结构图。如图5和图7所示，本实施例中，在绝缘层150上设有第一开孔151，第一开孔151为一矩形孔，其对应有源层140位置使得部分有源层裸露于第一开孔151，有源层140裸露的部分为导体化有源区141，用以与后续的源漏极170连接。所述导体化有源区141占所述有源层面积的60％～90％。
栅极160设于绝缘层150上表面，栅极160的材质为金属材料，所述金属材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)等，或者是合金，或者是多层薄膜结构。栅极160的厚度为2000埃米～8000埃米，栅极160与绝缘层150相对设置，且对应所述有源层140的中部。
图6是实施例中栅极和源漏极结构示意图。如图6所示，源漏极170设于绝缘层150的上表面，且设于栅极160两侧，源漏极170的材质包括金属材料，所述金属材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)等，或者是合金，或者是多层薄膜结构。部分金属材料设于第一开孔151内，源漏极170通过第一开孔151电连接至导体化有源区141，形成电路导通。源漏极170的厚度为2000埃米～8000埃米。
图8是实施例中有源层开孔结构图。如图8所示，由于本实施例中，需要先在绝缘层150上开孔形成第一开孔151，再采用自对准工艺根据栅极160和源漏极170的位置刻蚀掉其余裸露的绝缘层150，而现有技术中，一般采用酸性刻蚀液刻蚀金属形成栅极160和源漏极170图案，酸性溶液在刻蚀完金属层时，不可避免的会有部分残留至有源层140上，导致第一开孔151对应的有源层140部分被刻蚀，从而形成有源层开孔142。
在自对准工艺中，栅极160、源漏极170与其下方的绝缘层150边缘存在一定偏移量(offset)，这会使得该偏移量所对应区域的电阻值较大，不利于后续通电后的电流传输。
图9是实施例中自对准工艺步骤后的阵列基板结构图。如图8和图9所示，本实施例中，有源层开孔142距离源漏极170仍有一端距离，由于导体化有源区141的电阻率较小，由电流优先传输低电阻路线可知，电流会优先经过低电阻路段，即导体化有源区141，从而有效避免了自对准工艺中由于偏移导致的电流传输电压过高的问题。
钝化层180设于缓冲层130上，且覆盖有源层140、栅极160和源漏极170。钝化层180的材质包括硅的氧化物材料，钝化层180的厚度为1000埃米～5000埃米。钝化层180起到绝缘作用及隔绝外界水氧的作用。
像素电极190设于钝化层180的上表面，像素电极190的材质为氧化铟锡材料，贯穿钝化层180且与源漏极170电性连接，为后续发光材料的发光提供电路支持。
为了更好的解释本发明，本实施例还提供了所述阵列基板10的制备方法，如图10所示，图10是实施例中阵列基板制备步骤流程图。其具体步骤包括：
步骤S1)基板清洗步骤：提供一基板，所述基板为玻璃基板，清洗所述玻璃基板。
步骤S2)遮光层制备步骤：在所述基板上沉积一层500-2000A厚度的金属材料，金属材料包括Mo，Al，Cu，Ti等，或者是合金。通过蚀刻处理，蚀刻出图案，形成所述遮光金属层，遮光金属层的厚度为500埃米～2000埃米，遮光金属层起到遮光作用，同时也可以与后续的金属层共同形成储存电容。
步骤S3)缓冲层制备步骤：在遮光金属层及基板的上表面沉积一层无机材料，所述无机材料包括SiOx或SiNx，无机材料经固化后形成缓冲层，起到缓冲的作用，缓冲层的厚度优选1000-5000A。
步骤S4)有源层制备步骤：在所述缓冲层上沉积一层金属氧化物半导体材料(Oxide)，金属氧化物半导体材料包括IGZO，IZTO或IGZTO，其厚度100-1000A，图案化处理所述半导体材料形成有源层。
步骤S5)绝缘层制备步骤：在有源层和缓冲层上沉积一层SiOx或是SiNx或是多层结构薄膜，形成绝缘层，其厚度1000-3000A。
步骤S6)第一开孔刻蚀步骤：刻蚀绝缘层形成第一开孔，并露出第一开孔对应的有源层。
步骤S7)初次导体化步骤：进行整面的等离子(Plasma)处理，第一开孔处的有源层经历处理以后电阻明显降低，形成第一导体化区。
步骤S8)金属材料沉积步骤：在绝缘层和所述第一开孔内沉积一层金属材料，金属材料包括Mo，Al，Cu，Ti中的至少一种，其厚度为2000-8000A。
步骤S9)金属材料刻蚀步骤：通过一道黄光工艺，使用对金属材料和氧化物有足够刻蚀选择比的酸性刻蚀液，同时蚀刻出栅极和源漏极的图形，源漏极与第一导体化区连接。由于酸性刻蚀液会对金属材料下方的有源层也进行刻蚀从而在第一导体化区形成有源层开孔，为了在第一开孔内残留部分第一导体化区，本实施例中，酸性刻蚀液采用酸度较弱的刻蚀液，使得第一开孔内仍然具有一定宽度的第一导体化区，从而减少电流传输经过的电阻。
步骤S10)自对准刻蚀步骤：图9是实施例中自对准工艺步骤后的阵列基板结构图。如图9所示，利用栅极160和源漏极170自对准，蚀刻除栅极160和源漏极170对应区域的其他绝缘层，蚀刻后，只有位于栅极160和源漏极170正下方的绝缘层150得以保留，其余位置的绝缘层均被蚀刻掉，此时金属电极与下方绝缘层边缘存在一定偏移量(offset)。
步骤S11)最终导体化步骤：对于阵列基板进行整面的等离子处理(Plasma)，经等离子处理后，所有裸露的有源层形成导体化有源区，栅极下方的有源层没有被处理到，还保持其原本的半导体特性，形成沟道。
本实施例的有益效果在于，本实施例中的一种阵列基板及其制备方法、显示面板，有源层开孔与源漏电极之间具有一间隙，即源漏电极与有源层开孔之间仍具有一定宽度的导体化有源区，使得电流能够通过电阻较低的导体化有源区传输，避免电流经过电阻值较高区域，采用两次等离子处理，使得有源层导体化区域增大，减少其非导体化区域，降低了源漏极与非导体化区域的阻值。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (9)

1.一种阵列基板，其特征在于，包括
基板；
遮光金属层，设于所述基板上；
缓冲层，设于所述基板上且覆盖所述遮光金属层；
有源层，设于所述缓冲层上，且对应所述遮光金属层，所述有源层包括导体化有源区；
绝缘层，间隔设于所述基板上，且部分覆盖所述有源层；
有源层开孔，设于所述有源层上；以及
若干金属单元，设于所述绝缘层上，且与所述有源层连接；
其中，所述有源层开孔与所述金属单元之间具有一间隙；所述有源层包括沟道以及位于所述沟道相对两侧的导体化有源区，所述导体化有源区包括位于所述有源层开孔相对两侧的第一导体化区和第二导体化区，所述金属单元包括设于所述绝缘层上的栅极和源漏极，所述源漏极位于所述栅极两侧，所述源漏极与所述第一导体化区连接，所述第二导体化区未被所述绝缘层遮盖。
2.根据权利要求1所述的阵列基板，其特征在于，还包括
缓冲层凹槽，下凹于所述缓冲层，且对应所述有源层开孔；
所述缓冲层凹槽位于所述栅极与源漏极之间。
3.根据权利要求2所述的阵列基板，其特征在于，
所述缓冲层凹槽尺寸与有源层开孔尺寸的相等。
4.根据权利要求1所述的阵列基板，其特征在于，
所述导体化有源区面积占所述有源层面积的60%～90%。
5.一种阵列基板的制备方法，其特征在于，包括以下步骤：
提供一基板；
在所述基板上制备遮光金属层；
在所述基板上制备缓冲层，所述缓冲层覆盖所述遮光金属层；
在所述缓冲层上沉积一层半导体材料，形成有源层；
在所述缓冲层上沉积一层绝缘材料，形成覆盖所述有源层的绝缘层；
在所述绝缘层对应所述有源层的位置刻蚀绝缘层开孔；
将所述基板进行整面等离子处理，绝缘层开孔对应的有源层形成第一导体化区；
在所述绝缘层上沉积一层金属材料，形成金属层；
通过黄光工艺刻蚀所述金属层形成栅极和源漏极，其中所述源漏极与所述第一导体化区连接，刻蚀所述第一导体化区形成有源层开孔；
采用自对准工艺，保留栅极和源漏极下方的绝缘层，去除绝缘层其他裸露的部分；
将所述基板进行整面等离子处理，部分有源层形成导体化有源区；
其中，所述有源层包括沟道以及位于所述沟道相对两侧的导体化有源区，所述导体化有源区包括位于所述有源层开孔相对两侧的第一导体化区和第二导体化区，所述金属层包括设于所述绝缘层上的栅极和源漏极，所述源漏极位于所述栅极两侧，所述源漏极与所述第一导体化区连接，所述第二导体化区未被所述绝缘层遮盖。
6.根据权利要求5所述的阵列基板的制备方法，其特征在于，
所述金属材料包括Mo，Al，Cu，Ti中的至少一种。
7.根据权利要求5所述的阵列基板的制备方法，其特征在于，
采用酸性刻蚀液刻蚀所述金属层，其中，所述酸性刻蚀液的PH值大于5.0。
8.根据权利要求5所述的阵列基板的制备方法，其特征在于，还包括以下步骤：
在所述栅极、源漏极、和所述有源层上制备钝化层；
在所述钝化层对应所述源漏极处刻蚀通孔；
在所述钝化层上制备像素电极，所述像素电极填充所述通孔并连接至所述源漏极。
9.一种显示面板，其特征在于，包括权利要求1-4中任一项所述的阵列基板。
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