JP2011077521A - 垂直形不揮発性メモリ装置及びその製造方法 - Google Patents
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
【解決手段】半導体基板100上に垂直に備わるフィラー形状の単結晶半導体チャンネルと、単結晶半導体チャンネルの側面に一定間隔を有しながら積層される第1〜第n+1階(nは2以上の自然数)層間絶縁膜(パターン)122a−122eと、層間絶縁膜(パターン)122a−122e上に備わる電荷トラップ膜170と、電荷トラップ膜170上に備わるブロッキング絶縁膜175、ブロッキング絶縁膜175上に備わっている第1〜第n層コントロールゲート電極パターン185a−185dを含む。また、最下位及び最上位層間絶縁膜上に電荷トラップレイヤーのないGSL及びSSLゲートを含む。
【選択図】 図10
Description
GSL、SSLゲートに電荷トラップ膜のない垂直形電荷トラップフラッシュメモリ素子は、電荷トラップ膜のあるセルトランジスタが垂直方向に直列接続された構造を有するため、メモリ素子が高度で集積化される。
前記説明した垂直形電荷トラップフラッシュメモリ素子は電荷トラップ層のないグラウンドソーストランジスタとストリング選択トランジスタ及びセルトランジスタがフィラー形状の単結晶半導体パターンに形成された1つのセルストリングを含む。従って、前記グラウンドソーストランジスタと前記ストリング選択トランジスタの動作による電圧降下を防止してメモリ素子の信頼性を向上させることができる。また、非常に狭い面積でセルストリングを具現することができるため素子の集積度が非常に高い。そして、決定欠陥がほぼない単結晶義半導体パターンにセルトランジスタが具現されるため、セルトランジスタのセル電流及びセル散布特性が非常に良好である。
105 ・・・第1導電形高濃度不純物層
110、215 ・・・下部絶縁膜
115、240 ・・・GSL電極
120a−e、245a−e・・・層間絶縁膜
130、255 ・・・SSL電極
145、265 ・・・トンネル酸化膜
150、270 ・・・シリコン単結晶チャンネル膜
155、276 ・・・フィラー酸化膜
170、285 ・・・電荷トラップ膜
175、290 ・・・ブロッキング絶縁膜
185a−d、295a−d・・・コントロールゲート
195、315 ・・・ビットライン
410 ・・・メモリ
420 ・・・メモリコントローラ
510 ・・・CPU
610 ・・・EDC
620 ・・・表示部材
630 ・・・インタフェース
Claims (10)
- 基板上に備わるライン形状の絶縁膜パターンと、
前記絶縁膜パターンの側壁上に直接接続しながら前記基板上に垂直方向に延長形成されたフィラー形状の単結晶半導体パターンと、
前記単結晶半導体パターン上に形成されたトンネル酸化膜と、
前記基板に近接して前記トンネル酸化膜上に形成される下部電極パターンと、
前記下部電極パターン上に備わる多数個の層間絶縁膜パターンと、
前記層間絶縁膜パターンの間に備わり、前記トンネル酸化膜に次々と積層する電荷トラップ膜及びブロッキング絶縁膜と、
前記層間絶縁膜パターンの間に備わり、前記ブロッキング絶縁膜表面上に形成される多数個のコントロールゲートパターンと、
最上位の前記層間絶縁膜パターン上に備わって、前記トンネル酸化膜上に形成される上部電極パターンと、を含む垂直形不揮発性メモリ装置。 - 前記電荷トラップ膜はシリコン窒化物または、金属酸化物を含むことを特徴とする請求項1に記載の垂直形不揮発性メモリ装置。
- 前記電荷トラップ膜及び前記ブロッキング絶縁膜は、前記トンネル酸化膜の一部表面及び前記層間絶縁膜パターンの上部面及び下部面のプロファイルに従って形成されることを特徴とする請求項1に記載の垂直形不揮発性メモリ装置。
- 前記単結晶半導体パターンは単結晶シリコンで形成されたことを特徴とする請求項1に記載の垂直形不揮発性メモリ装置。
- 垂直形不揮発性メモリ装置のための基板の主な表面に対して垂直した垂直形チャンネルを形成するための物質を含む単結晶半導体パターンと、
前記単結晶半導体パターン上に形成されたトンネル酸化膜と、
前記トンネル酸化膜上に直接形成された下部ゲート電極膜パターンを含むグラウンド選択トランジスタと、
前記トンネル酸化膜上に直接形成された上部ゲート電極膜パターンを含むストリング選択トランジスタと、を含む垂直形不揮発性メモリ装置。 - 半導体基板に不純物領域を形成する段階と、
前記不純物領域上に下部絶縁膜を形成する段階と、
前記下部絶縁膜上に下部電極層を形成する段階と、
前記下部電極層上に犠牲膜及び層間絶縁膜を次々と繰り返して積層する段階と、
最上位の前記層間絶縁膜上に上部電極層を形成する段階と、
多数の層が積層された絶縁膜構造物に前記不純物領域を露出させるチャンネルリセスを形成する段階と、
前記チャンネルリセスの一側壁上にトンネル酸化膜を形成する段階と、
前記チャンネルリセス内の前記トンネル酸化膜上に単結晶半導体パターンを形成する段階と、
前記チャンネルリセス内に絶縁膜パターンを形成する段階と、
前記犠牲膜の犠牲膜パターンを除去して前記トンネル酸化膜を露出させる段階と、
露出した前記トンネル酸化膜上に電荷トラップ層及びブロッキング絶縁膜を形成する段階と、
前記ブロッキング絶縁膜表面上にコントロールゲートパターンを形成する段階と、を含む垂直形不揮発性メモリ装置の製造方法。 - 前記コントロールゲートパターンを形成した後、前記単結晶半導体パターンと接するビットラインを形成する段階をさらに含むことを特徴とする請求項6に記載の垂直形不揮発性メモリ装置の製造方法。
- 前記犠牲膜パターンを除去して前記トンネル酸化膜を露出させる段階は、
前記単結晶半導体パターンの間に位置する前記絶縁膜構造物の一部分を除去して第1開口部を形成する段階と、
湿式食刻工程を利用して前記犠牲膜パターンを除去して前記トンネル酸化膜を露出させる第2開口部を形成する段階と、を含むことを特徴とする請求項6に記載の垂直形不揮発性メモリ装置の製造方法。 - 前記コントロールゲートパターンを形成する段階は、
前記層間絶縁膜の層間絶縁膜パターンの間を満たしながら前記ブロッキング絶縁膜表面上に導電膜を形成する段階と、
前記第1開口部の内部に位置する前記導電膜を食刻する段階と、を含むことを特徴とする請求項8に記載の垂直形不揮発性メモリ装置の製造方法。 - 前記第1開口部に素子分離膜を形成して同一な層のコントロール電極を離隔する段階をさらに含むことを特徴とする請求項9に記載の垂直形不揮発性メモリ装置の製造方法。
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US8344385B2 (en) | 2013-01-01 |
DE102010037434B4 (de) | 2020-03-05 |
CN102034829A (zh) | 2011-04-27 |
DE102010037434B8 (de) | 2020-04-30 |
CN102034829B (zh) | 2015-11-25 |
TW201138070A (en) | 2011-11-01 |
US20110073866A1 (en) | 2011-03-31 |
KR20110034816A (ko) | 2011-04-06 |
KR101603731B1 (ko) | 2016-03-16 |
DE102010037434A1 (de) | 2011-03-31 |
TWI501384B (zh) | 2015-09-21 |
JP5647840B2 (ja) | 2015-01-07 |
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