WO2016046602A1 - 半导体存储器件及其制造方法 - Google Patents

半导体存储器件及其制造方法 Download PDF

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Publication number
WO2016046602A1
WO2016046602A1 PCT/IB2014/064848 IB2014064848W WO2016046602A1 WO 2016046602 A1 WO2016046602 A1 WO 2016046602A1 IB 2014064848 W IB2014064848 W IB 2014064848W WO 2016046602 A1 WO2016046602 A1 WO 2016046602A1
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Prior art keywords
channel
layer
memory device
semiconductor memory
storage
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PCT/IB2014/064848
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English (en)
French (fr)
Inventor
金成吉
南泌旭
延国贤
李圣海
张佑赈
刘东哲
林宪亨
池正根
黃棋鉉
Original Assignee
三星电子株式会社
金成吉
南泌旭
延国贤
李圣海
张佑赈
刘东哲
林宪亨
池正根
黃棋鉉
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Application filed by 三星电子株式会社, 金成吉, 南泌旭, 延国贤, 李圣海, 张佑赈, 刘东哲, 林宪亨, 池正根, 黃棋鉉 filed Critical 三星电子株式会社
Priority to US15/514,239 priority Critical patent/US10685972B2/en
Priority to CN201480082144.4A priority patent/CN106716638B/zh
Priority to PCT/IB2014/064848 priority patent/WO2016046602A1/zh
Publication of WO2016046602A1 publication Critical patent/WO2016046602A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the inventive concept relates to a semiconductor, and more particularly to a semiconductor memory device and a method for fabricating the same.
  • Semiconductor devices are widely used in the electronics industry due to their small size, versatility, and/or low manufacturing cost. With the development of the electronics industry, there is an increasing demand for high performance and low cost semiconductor devices. In order to meet the above needs, semiconductor devices (for example, semiconductor memory devices) have been highly integrated.
  • the degree of integration of conventional two-dimensional (2D) memory devices is primarily determined by the area occupied by the unit memory cells. Therefore, the integration degree of a conventional 2D memory device is greatly affected by the technique for forming a fine pattern.
  • 3D semiconductor devices including three-dimensionally arranged memory cells have been developed to overcome the above limitations.
  • Embodiments of the inventive concept may provide a semiconductor memory device having a three-dimensional (3D) structure with improved electrical characteristics and a method for fabricating the same.
  • a semiconductor memory device may include: a plurality of gates stacked vertically on a substrate; a vertical channel filling a channel hole vertically penetrating the plurality of gates; a storage layer at The inner side wall of the channel extends vertically.
  • the vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling the upper region of the channel hole and contacting the lower channel.
  • the upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.
  • the storage layer may extend vertically along the inner sidewall of the upper region of the channel aperture and may extend horizontally along the top surface of the lower channel to include a bottom end portion having an L shape.
  • the top surface of the lower channel may be flat or may be convex toward the direction away from the substrate.
  • the upper channel may extend curvedly along the bottom end portion of the L shape of the storage layer.
  • a portion of the top surface of the lower channel may be recessed and a bottom end portion of the upper channel may be disposed in a recessed region of the top surface of the lower channel.
  • the lower channel may have a cylindrical shape that completely fills the lower region of the channel hole
  • the upper channel may have a U-shaped cylindrical structure that partially fills the upper region of the channel hole and has a uniform thickness.
  • the semiconductor memory device may further include: an insulating filling layer filling an inner space of the cylindrical structure of the upper channel.
  • a memory layer may be disposed between the upper channel and a gate adjacent to the upper channel, and a gate insulating layer may be disposed between the lower channel and the gate adjacent to the lower channel.
  • the substrate below the lower channel may be recessed and the bottom end portion of the lower channel may be disposed in a recessed region of the substrate.
  • a semiconductor memory device can include: a gate stack including at least one lower non-storage gate, a plurality of memory gates, and at least one upper non-storage gate vertically stacked on a substrate; a channel extending vertically through the at least one upper non-storage gate and the plurality of memory gates; a lower channel vertically penetrating through the at least one lower non-storage gate; a memory layer disposed on the upper trench And between the at least one upper non-storage gate and between the upper channel and the plurality of storage gates.
  • the memory layer may have a bottom end portion that contacts the L shape of the lower channel, and the upper channel may extend along the top surface of the memory layer and the lower channel and may have a uniform thickness.
  • the lower portion of the upper channel may have a curved shape that extends along the bottom end portion of the L shape of the storage layer.
  • the upper and lower channels may be connected to each other to form a vertical channel that vertically penetrates the gate stack, and the vertical channel may be electrically connected to the substrate.
  • the vertical channel can fill the via holes that vertically penetrate the gate stack.
  • the lower channel may have a cylindrical shape that completely fills a lower region of the channel hole
  • the upper channel may have a cylindrical shape that continuously extends along an inner sidewall of the upper region of the channel hole and a top surface of the lower channel Single layer.
  • the inner space of the cylindrical shape may be filled with an insulating layer.
  • the memory layer may not be disposed between the lower channel and the at least one lower non-storage gate.
  • the memory layer may include: a first storage layer disposed between the upper channel and the at least one upper non-storage gate and between the upper channel and the plurality of storage gates; a memory layer disposed between the lower channel and the at least one lower non-storage gate.
  • the second storage layer may also be disposed between the first storage layer and the at least one upper non-storage gate and between the first storage layer and the plurality of storage gates.
  • a method for fabricating a semiconductor memory device may include: forming a channel hole vertically penetrating through a plurality of layers stacked on a substrate, the channel hole exposing the substrate; forming a portion partially filling the channel hole a lower channel; a memory layer extending along a top surface of the channel hole and a top surface of the lower channel; a spacer extending vertically along the inner sidewall of the channel hole is formed on the memory layer; and the spacer is utilized by an etching process Etching the memory layer as an etch mask to expose a portion of the top surface of the lower trench; removing the spacer to expose the memory layer; forming an extension along the exposed portion of the exposed memory layer and the top surface of the lower trench Channel.
  • the step of removing the spacers can include selectively removing the spacers by providing a gaseous etchant that is capable of selectively etching the spacers relative to the storage layer.
  • the storage layer and the spacer may respectively include an insulating layer and a silicon layer
  • the gaseous etchant may include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), any of them or Any combination of them.
  • the method can also include trimming the upper channel.
  • the step of trimming the upper channel may include thinning the upper channel by providing a solution comprising ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and deionized water. .
  • the semiconductor layer is conformally formed, an upper channel having a uniform thickness can be formed. Further, even if the trimming process for forming a thin channel is performed, the contact characteristics between the upper channel and the lower channel are excellent. Therefore, the electrical characteristics of the 3D semiconductor memory device can be improved.
  • FIG. 1 is a plan view illustrating a semiconductor memory device according to example embodiments of the inventive concepts
  • FIG. 2A through 2R are cross-sectional views taken along line A1-A2 of FIG. 1 to illustrate a method for fabricating a semiconductor memory device in accordance with some embodiments of the inventive concept;
  • Figure 2I is an enlarged cross-sectional view of a portion of Figure 2H;
  • Figure 2K is an enlarged cross-sectional view of a portion of Figure 2J;
  • Figure 2R is an enlarged cross-sectional view of a portion of Figure 2Q;
  • FIG. 3A is a cross-sectional view showing a comparative example of FIG. 2I;
  • FIG. 3B is a cross-sectional view showing a comparative example of FIG. 2K;
  • FIG. 4A to 4C are cross-sectional views showing a modified example of Fig. 2R;
  • 5A to 5D are cross-sectional views taken along line A1-A2 of FIG. 1 to illustrate a method for fabricating a semiconductor memory device according to other embodiments of the inventive concepts;
  • Figure 5E is an enlarged cross-sectional view of a portion of Figure 5D;
  • FIG. 6A is a schematic block diagram illustrating a memory card including a semiconductor memory device in accordance with an embodiment of the inventive concepts
  • FIG. 6B is a schematic block diagram illustrating an information processing system including a semiconductor memory device in accordance with an embodiment of the inventive concepts.
  • a semiconductor memory device includes: a plurality of gates vertically stacked on a substrate; a vertical channel filling a channel hole vertically penetrating the plurality of gates; and storing a layer extending vertically on an inner sidewall of the channel, wherein the vertical channel includes: a lower channel filling a lower region of the channel hole and electrically connected to the substrate; and an upper channel filling the upper region of the channel hole And contacting the lower channel, and wherein the upper channel extends along the memory layer and the lower channel in the upper region of the channel hole and has a uniform thickness.
  • inventive concept will now be described more fully hereinafter with reference to the accompanying drawings.
  • the advantages and features of the inventive concept and the method of implementing the same will be apparent from the following exemplary embodiments, which will be described in more detail with reference to the accompanying drawings.
  • inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concepts and the scope of the inventive concept. The embodiments of the inventive concept are not limited to the specific examples provided herein, and are exaggerated for clarity.
  • devices and methods of forming devices in accordance with various embodiments described herein can be implemented in microelectronic devices, such as integrated circuits, in which a plurality of devices in accordance with various embodiments described herein are implemented. Integrated in the same microelectronic device. Thus, the cross-sectional views shown herein can be repeated in two different directions that do not need to be orthogonal in a microelectronic device. Accordingly, a plan view of a microelectronic device embodying devices in accordance with various embodiments described herein can include a plurality of devices in an array and/or in a two-dimensional pattern based on the functionality of the microelectronic device.
  • microelectronic devices in accordance with various embodiments described herein can be inserted into other devices depending on the functionality of the microelectronic device. Moreover, microelectronic devices in accordance with various embodiments described herein can be repeated in a third direction that can be orthogonal to the two different directions to provide a three-dimensional integrated circuit.
  • the cross-sectional views shown herein provide support for a plurality of devices extending in three different directions in a plan view and/or in three different directions in a perspective view in accordance with various embodiments described herein.
  • the device/structure may include multiple active regions and transistor structures on the active region ( Or, where appropriate, the memory cell structure, gate structure, etc.).
  • FIG. 1 is a plan view illustrating a semiconductor memory device according to example embodiments of the inventive concepts.
  • the semiconductor memory device 1 may include a plurality of vertical channels 140 vertically on the substrate 101, a plurality of gates 160 stacked along the vertical channel 140, and bits electrically connected to the vertical channel 140. Line 180.
  • the semiconductor memory device 1 may be a vertical NAND flash memory device that further includes a memory layer 150 disposed between the vertical channel 140 and the gate 160, as shown in FIG. 2Q.
  • the gate 160 may constitute a ground selection line GSL adjacent to the substrate 101, a string selection line SSL, and a word line WL between the ground selection line GSL and the character selection line SSL.
  • the ground selection line GSL may have a single layer structure or a multilayer structure
  • the string selection line SSL may have a single layer structure or a multilayer structure.
  • the bottom end of each vertical channel 140 may be electrically connected to the substrate 101, and the top end of each vertical channel 140 may be electrically connected to the bit line 180.
  • the gates 160 may be stacked in a pyramid form such that the two sidewalls or four sidewalls of the stacked gates 160 may form a stepped structure 111.
  • the string selection line SSL may have a linear shape extending in a direction crossing the extending direction of the bit line 180.
  • the direction in which the bit line 180 extends may be parallel to the line A1-A2.
  • the direction in which the string selection line SSL extends may be perpendicular to the lines A1-A2.
  • the word line WL and the ground selection line GSL may have a plate shape having a word line cutting portion extending in a direction crossing the line A1-A2 (word Line cut) 107.
  • the word line cutting portion 107 may expose the substrate 101.
  • the vertical channel 140 of the semiconductor memory device 1 may include a lower channel 141 and an upper channel 145 stacked on the lower channel 141 as shown in FIG. 2Q.
  • the upper channel 145 may be in contact with the lower channel 141.
  • the vertical channel 140 can have a macaroni shape. Further, the vertical channel 140 can sufficiently ensure the current path, so that even if the vertical channel 140 is thinned, there is no interruption between the lower channel 141 and the upper channel 145 (cut Phenomenon).
  • FIG. 2A through 2R are cross-sectional views taken along line A1-A2 of FIG. 1 to illustrate a method for fabricating a semiconductor memory device in accordance with some embodiments of the inventive concept.
  • Figure 2I is an enlarged cross-sectional view of a portion of Figure 2H.
  • 2K is an enlarged cross-sectional view of a portion of FIG. 2J.
  • 2R is an enlarged cross-sectional view of a portion of FIG. 2Q.
  • Fig. 3A is a cross-sectional view showing a comparative example of Fig. 2I.
  • Fig. 3B is a cross-sectional view showing a comparative example of Fig. 2K.
  • a forming stack 10 can be formed on the substrate 101.
  • the substrate 101 may include a semiconductor substrate such as a single crystal silicon wafer.
  • the plurality of insulating layers 110 and the plurality of sacrificial layers 120 may be alternately and repeatedly stacked to form the molded stack 10.
  • the insulating layer 110 may be a silicon oxide layer or a silicon nitride layer.
  • Each of the sacrificial layers 120 may be formed of a material having an etch selectivity with respect to the insulating layer 110 and selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, silicon, and silicon-germanium.
  • the insulating layer 110 may be a silicon oxide (eg, SiO x ) layer, and the sacrificial layer 120 may be a silicon nitride (SiN x ) layer.
  • the thickness of the sacrificial layer 120 may be substantially equal to each other.
  • the thickness of the insulating layer 110 may be substantially equal to each other.
  • the thickness of the at least one insulating layer 110 may be different from the thickness of the other insulating layers 110.
  • the third insulating layer 110c and the seventh insulating layer 110g in the insulating layer 110 may be relatively thick.
  • the insulating layer 110 may include first to ninth insulating layers 110a to 110i.
  • the sacrificial layer 120 may include first to eighth sacrificial layers 120a to 120h.
  • the molding stack 10 can be patterned to form vertical channel holes 103.
  • the vertical channel hole 103 that vertically penetrates the molding stack 10 can be formed by a dry etching process.
  • the vertical channel hole 103 may expose the substrate 101.
  • the substrate 101 may be recessed due to over etching.
  • the width of the vertical channel holes 103 may be substantially uniform regardless of the vertical height from the substrate 101.
  • the width of the vertical channel hole 103 may vary according to the vertical height from the substrate 101.
  • a vertical channel hole 103 having a substantially uniform width will be described.
  • a lower channel 141 may be formed to fill a portion of the vertical channel hole 103.
  • the lower channel 141 may be in contact with the substrate 101 and may have a column shape.
  • the lower channel 141 may be formed of a semiconductor having the same conductivity type as the substrate 101 or formed of an intrinsic semiconductor.
  • the lower channel 141 may include P-type silicon or intrinsic silicon.
  • the lower channel 141 may be formed of a polycrystalline semiconductor by a deposition technique, or may be formed of a single crystal semiconductor by an epitaxial growth technique or a laser crystallization technique. In some embodiments, the lower channel 141 may be formed by epitaxial growth of single crystal P-type silicon or intrinsic silicon.
  • the lower channel 141 may be in contact with a sidewall of the first sacrificial layer 120a and a sidewall of the second sacrificial layer 120b. Further, the lower channel 141 may also be in contact with a portion of the sidewall of the third insulating layer 110c.
  • the top surface 141s of the lower channel 141 may be flat. If the substrate 101 is recessed during the formation of the vertical channel hole 103, the bottom end portion of the lower channel 141 may be disposed in the recessed region of the substrate 101, and thus, the bottom surface of the lower channel 141 may be larger than the substrate 101 The top surface 101s is low.
  • a memory layer 150 and a first semiconductor layer 143 may be formed on the substrate 101.
  • the memory layer 150 may extend along the inner sidewall of the vertical channel hole 103 to cover the molding stack 10.
  • the first semiconductor layer 143 may cover the memory layer 150.
  • the memory layer 150 may include an insulating layer deposited using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process and in contact with the lower channel 141.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a blocking insulating layer eg, SiO 2 or SiO 2 /Al 2 O 3
  • a trapping insulating layer eg, SiN or SiON
  • a tunnel insulating layer eg, SiO 2
  • the first semiconductor layer 143 may be formed of a semiconductor (for example, polysilicon or single crystal silicon) by a CVD process or an ALD process.
  • the first semiconductor layer 143 may be formed of polysilicon by a CVD process.
  • the insulating layer 190 may also be formed by depositing a dielectric material (eg, SiO x ) to cover the first semiconductor layer 143.
  • the first semiconductor layer 143 may be etched by an etching process (eg, a dry etching process) to form the first semiconductor layer 143 to have a vertical interval covering the memory layer 150 in the vertical channel hole 103.
  • an etching process eg, a dry etching process
  • a portion of the storage layer 150 formed on the bottom surface of the vertical channel hole 103 may be exposed by a spacer etching process.
  • the memory layer 150 formed on the ninth insulating layer 110i may also be exposed by a spacer etching process.
  • the memory layer 150 may be etched to expose a portion of the lower channel 141.
  • the storage layer 150 may be wet etched or dry etched into a vertical shape having an inner sidewall covering the vertical channel hole 103.
  • a portion of the storage layer 150 covering the lower channel 141 may be removed by etching of the memory layer 150 to expose the lower channel 141.
  • the first semiconductor layer 143 may serve as a mask covering the memory layer 150 during the etching process of the memory layer 150, so that another portion of the memory layer 150 covering the lower channel 141 may not be removed.
  • the bottom end portion 150b of the etched memory layer 150 may have an L shape.
  • the first semiconductor layer 143 may be removed.
  • the first semiconductor layer 143 can be selectively removed with an etchant.
  • the etching rate of the composition of the memory layer 150 (for example, SiO 2 , SiN, SiON) may be greater than the etching rate of the composition of the first semiconductor layer 143 (eg, polysilicon) during the removal process using the etchant.
  • the etchant may include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), any of them, or any combination thereof.
  • the etchant may include at least one of NF 3 , SF 6 , Cl 2 , HCl, CCl 4 , HBr, HI, ClF 3 , and CF 3 Cl in the gas phase. Since the lower channel 141 is a crystal, the lower channel 141 is not etched while the first semiconductor layer 143 is etched by the etchant.
  • a second semiconductor layer 145 may be formed to extend along the inner sidewall of the vertical channel hole 103 and cover the molding stack 10.
  • the second semiconductor layer 145 may be formed of amorphous silicon by a CVD process. It is also possible to further perform a heat treatment process to convert amorphous silicon into crystalline silicon.
  • the second semiconductor layer 145 may have a cylindrical shape conformally formed along the side in the vertical channel hole 103.
  • the second semiconductor layer 145 may have a vertical end portion 150b extending vertically along the memory layer 150 in the vertical channel hole 103 and along the L-shaped bottom end portion 150b of the memory layer 150 on the lower channel 141. Cylindrical shape. Since the second semiconductor layer 145 extends along the memory layer 150 and the lower channel 141 and is bent along the bottom end portion 105b of the memory layer 150, the second semiconductor layer 145 may have a substantially uniform thickness T1 regardless of its formation position. . The second semiconductor layer 145 may be in contact with the lower channel 141 to serve as an upper channel. The lower channel 141 and the upper channel may constitute the vertical channel 140, which will be described below in FIG. 2L.
  • the first semiconductor layer 143 and the second semiconductor layer 145 can be used as the contact lower channel 141.
  • Upper channel the sum of the thicknesses of the first semiconductor layer 143 and the second semiconductor layer 145 may vary depending on their formation positions.
  • the first semiconductor 143 and the second semiconductor layer 145 may have a first thickness T1a on the inner sidewall of the vertical channel hole 103, but have a smaller thickness than the first thickness T1a on the bottom end portion 150b of the memory layer 150.
  • Two thicknesses T1b may be very small depending on the deposition thickness of the second semiconductor layer 145. Therefore, the contact characteristics between the lower channel and the upper channels 143 and 145 are deteriorated.
  • the second semiconductor layer 145 can be formed to have a uniform thickness T1, and therefore, the lower channel 141 and the second semiconductor layer 145 The contact characteristics between the two will be excellent.
  • the second semiconductor layer 145 can be thinly trimmed.
  • the second semiconductor layer 145 can be thinned by using a solution of SCl (standard cleaner 1) including ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and deionized water.
  • SCl standard cleaner 1 including ammonia (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and deionized water.
  • the second semiconductor layer 145 may have a thickness T2 that is smaller than the initial thickness T1 by the trimming process.
  • the trimmed second semiconductor layer 145 may have a uniform thin thickness T2, and formation thereof Position is irrelevant.
  • the upper channels 143 and 145 may have holes in the vertical channel.
  • the second trim thickness T2b may be further smaller than the first trim thickness T2a.
  • the contact characteristics between the lower channel 141 and the upper channels 143 and 145 are further deteriorated by the second trimming thickness T2b which is further reduced.
  • the lower channel 141 may not be connected to the upper channels 143 and 145.
  • the second semiconductor layer 145 has a uniform initial thickness T1 as described with reference to FIG. 2I, and therefore, even if the second semiconductor layer 145 is trimmed as shown in FIG. 2K, the lower channel 141 and the second semiconductor layer The contact characteristics between 145 will also be excellent.
  • a filling layer 191 may be formed on the second semiconductor layer 145.
  • a silicon oxide layer or a silicon nitride layer may be deposited on the second semiconductor layer 145 to fill the vertical channel holes 103, and the deposited silicon oxide layer or silicon nitride layer may be planarized with the second semiconductor layer 145 until The molding stack 10 is exposed to form a filling layer 191. Therefore, the second semiconductor layer 145 can be formed into a cylindrical structure having a U shape in the vertical channel hole 103.
  • the second semiconductor layer 145 having a cylindrical structure is defined as an upper channel 145.
  • the upper channel 145 may surround the sidewall of the filling layer 191 within the vertical channel hole 103.
  • the filling layer 191 can be utilized to fill the inner space of the upper channel 145 having a cylindrical structure.
  • the upper channel 145 may be in contact with the top surface of the lower channel 141.
  • the lower channel 141 and the upper channel 145 may constitute a vertical channel 140.
  • the upper channel 145 is formed of a single semiconductor layer (i.e., the second semiconductor layer), and thus there is no interface in the upper channel 145.
  • the upper channel is composed of the first semiconductor layer 143 and the second semiconductor layer 145 as shown in FIG. 3B, an interface exists in the upper channel. In this case, the flow or current of the carriers may be uneven in the upper channel due to the interface.
  • the upper channel 145 according to the present embodiment does not have an interface, the flow or current of carriers in the upper channel 145 of the present embodiment may be substantially uniform. As a result, the semiconductor memory device according to the inventive concept can have excellent electrical characteristics.
  • a word line cut 107 that exposes the substrate 101 may be formed between the vertical channels 140.
  • the stack 10 can be dry etched to form a wordline cut 107 through the molded stack 10.
  • the substrate 101 located under the word line cutting portion 107 may be recessed due to over etching.
  • the sidewall of the sacrificial layer 120 and the sidewall of the insulating layer 110 may be exposed by the word line cutting portion 107.
  • an etchant may be provided through the word line cutout 107 to selectively remove the sacrificial layer 120.
  • the shaped wing member 15 including the insulating layer 110 vertically separated from each other along the vertical channel 140 may be formed by selective removal of the sacrificial layer 120.
  • the etchant may include phosphoric acid (H 3 PO 4 ).
  • the recessed regions 108 exposing the lower channel 141 and the memory layer 150 may be formed by selective removal of the sacrificial layer 120.
  • a deposition process of an insulating material or an oxidation process may be performed on the lower channel 141 exposed by the recessed region 108 to form the gate insulating layer 113.
  • a gate 160 including first to eighth gate electrodes 161 to 168 may be separately formed to fill the recessed regions 108, thereby forming gate electrodes 161 to 168 including vertically separated from each other by the insulating layer 110.
  • Gate stack 20 A conductive material (eg, silicon, metal, metal nitride, and/or metal silicide) may be deposited on the substrate 101, and then the conductive material outside the recessed region 108 may be removed to form the gates 161 to 168.
  • a dopant may be implanted into the substrate 101 exposed by the word line cutting portion 107 to form a common source 104s.
  • the common source 104s may be doped with a dopant of a conductivity type different from the conductivity type of the substrate 101.
  • the substrate 101 may be doped with a P-type dopant, and the common source 104s may be doped with an N-type dopant.
  • a filling insulating layer 171 may be formed to fill the word line cutting portion 107.
  • an insulating material may be deposited to cover the gate stack 20, and the deposited insulating material may be planarized to form a filled insulating layer 171.
  • the top end portion of the vertical channel 140 may be removed to form the opening 105.
  • the opening 105 may be filled with silicon, and a dopant may be implanted into the silicon to form a drain 104d of the same conductivity type as the common source 104s.
  • an interlayer insulating layer 173 may be formed to cover the gate stack 20, and a plug 182 may be formed to penetrate the interlayer insulating layer 173. Plug 182 can be connected to drain 104d.
  • a bit line 180 connected to the plug 182 may be formed on the interlayer insulating layer 173. Bit line 180 can be electrically connected to vertical channel 140 by plug 182.
  • a three-dimensional (3D) semiconductor memory device 1 such as a vertical NAND flash memory device, can be formed.
  • the gate electrodes 161 to 168 may extend in a first horizontal direction (eg, forward and reverse directions) on the substrate 101, and the bit lines may extend in a second direction (eg, a left direction and a right direction) substantially perpendicular to the first horizontal direction. .
  • the gates 161 to 168 vertically stacked along the vertical channel 140 may constitute a cell string.
  • the first gate 161 and the second gate 162 of the gates 161 to 168 may be adjacent to the lower channel 141, and the third to eighth gates 163 to 168 may be adjacent to the upper channel 145.
  • the first gate 161 and the second gate 162 may be non-storage select gates and may correspond to a ground select line GSL.
  • the third to sixth gates 163 to 166 may be storage gates and may correspond to word lines WL.
  • the seventh gate 167 and the eighth gate 168 may be non-storage select gates and may correspond to string select lines SSL.
  • the semiconductor memory device 1 does not have the memory layer 150 for increasing the current path P between the common source 104s and the lower channel 141, so that the common source 104s and the vertical can be made
  • the current path P between the straight channels 140 is minimized. Further, an increase in resistance due to an increase in the current path P can be suppressed.
  • the upper channel 145 as described with reference to FIGS. 2H to 2K has a uniform thickness along the bottom end portion 150b of the L-shaped memory layer 150, even if the upper channel 145 is trimmed, the lower groove can be sufficiently provided.
  • the body contact 144 of the lower channel 141 and the upper channel 145 can provide sufficient space for current flow from the lower channel 141 to the upper channel 145 (or from the upper channel 145 to the lower channel 141) or
  • the vias enable excellent current flow between the lower channel 141 and the upper channel 145.
  • the short current path and/or excellent current flow can cause the semiconductor memory device 1 to have improved electrical characteristics.
  • FIG. 4A to 4C are cross-sectional views showing a modified example of Fig. 2R.
  • the lower channel 141 may have a top surface protrusion toward a direction away from the substrate 101.
  • the top surface 141s of the lower channel 141 may have a convex shape.
  • the upper channel 145 may be inserted into the lower channel 141.
  • the process of etching the memory layer 150 to expose a portion of the lower channel 141 as described with reference to FIG. 2F and/or the process of removing the first semiconductor layer 143 as described with reference to FIG. 2G may also etch the lower channel.
  • Part of the top surface of 141 As a result, this portion of the top surface of the lower channel 141 can be recessed, and the bottom end portion of the upper channel 145 can extend into the recessed region of the top surface of the lower channel 141.
  • the vertical channel may be composed of a second semiconductor layer 145 that is directly connected to the substrate 101.
  • the formation process of the lower channel 141 described in FIG. 2C can be skipped, so that the vertical channel can be formed to be composed only of the second semiconductor layer 145.
  • the second semiconductor layer 145 may be in contact with the substrate 101 such that the second semiconductor layer 145 and the substrate 101 may constitute the body contact portion 144.
  • FIG. 5A to 5D are cross-sectional views taken along line A1-A2 of Fig. 1 to illustrate a method for fabricating a semiconductor memory device according to other embodiments of the inventive concepts.
  • Figure 5E is an enlarged cross-sectional view of a portion of Figure 5D.
  • the formed wing member 15 may be formed by the same or similar process as the process described with reference to FIGS. 2A through 2N.
  • the first storage layer 151 may be formed to surround the upper channel 145.
  • the first storage layer 151 may include a tunnel insulating layer, or the first storage layer 151 may include a tunnel insulating layer and a capture insulating layer.
  • the gate insulating layer 113 on the sidewall of the lower trench 141 of FIG. 2N may be omitted.
  • a second storage layer 152 may be formed to cover the inner surface of the recessed area 108. If the first storage layer 151 includes a tunnel insulating layer, the second storage layer 152 may include a capture insulating layer and a blocking insulating layer. In another embodiment, if the first storage layer 151 includes a tunnel insulating layer and a trapping insulating layer, the second storage layer 152 may include a blocking insulating layer. The first storage layer 151 and the second storage layer 152 may constitute the storage layer 150.
  • the gate 160 including the first to eighth gate electrodes 161 to 168 may be formed in the recessed region 108 by a deposition process and an etching process of a conductive material. Therefore, the gate stack 20 can be formed.
  • the gate stack 20 can include a gate 160 that is vertically stacked along the vertical channel 140 on the substrate 101. A dopant may be implanted into the substrate 101 exposed by the word line cutting portion 107 to form a common source 104s.
  • the filling insulating layer 171, the interlayer insulating layer 173, the plug 182, and the bit line 180 may be formed by the same or similar processes as described with reference to FIGS. 2P and 2Q.
  • the filling insulating layer 171 may fill the word line cutting portion 107, and the interlayer insulating layer 173 may cover the gate stack 20.
  • the plug 182 may penetrate the interlayer insulating layer 173 to be connected to the drain 104d.
  • the bit line 180 may be disposed on the interlayer insulating layer 173 and may be electrically connected to the vertical channel 140 through the plug 182.
  • a 3D semiconductor memory device 2 for example, a vertical NAND flash memory device can be formed.
  • the planar structure of the semiconductor memory device 2 may be the same as or similar to the planar structure of the semiconductor memory device 1 of FIG.
  • the memory layer 150 may include a first memory layer 151 formed in the vertical channel hole 103 and a second memory layer 152 formed in the recess region 108.
  • Other features of the second memory device 2 may be the same as corresponding features of the semiconductor memory device 1 of FIGS. 2Q and 2R.
  • FIG. 6A is a schematic block diagram illustrating a memory card including a semiconductor memory device in accordance with an embodiment of the inventive concepts.
  • FIG. 6B is a schematic block diagram illustrating an information processing system including a semiconductor memory device in accordance with an embodiment of the inventive concepts.
  • the flash memory 1210 may include at least one of the semiconductor memory device 1 and the semiconductor memory device 2 according to the foregoing embodiments of the inventive concepts.
  • the flash memory 1210 can be applied to the memory card 1200.
  • memory card 1200 can include a memory controller 1220 that controls data communication between host 1230 and flash memory 1210.
  • a static random access memory (SRAM) device 1221 can be used as the working memory of the central processing unit (CPU) 1222.
  • the host interface unit 1223 can be configured to include a data communication protocol between the memory card 1200 and the host 1230.
  • Error checking and correction (ECC) block 1224 can detect and correct errors in data read from storage device 1210.
  • the storage interface unit 1225 can be interfaced with the storage device 1210.
  • CPU 1222 controls the overall operation of memory controller 1220.
  • the information processing system 1300 may include a storage system 1310 having at least one of the semiconductor memory device 1 and the semiconductor memory device 2 according to the foregoing embodiments of the inventive concepts.
  • Information processing system 1300 can include a mobile device or a computer.
  • information handling system 1300 can include a modem 1320, a central processing unit (CPU) 1330, a random access memory (RAM) 1340, and a user interface unit 1350 that is electrically coupled to storage system 1310 via system bus 1360.
  • the storage system 1310 can include a flash memory 1311 and a storage controller 1312.
  • the storage system 1310 may have substantially the same structure as the memory card 1200 illustrated in FIG. 6A.
  • the storage system 1310 can store the CPU 1330 processed data or data input from an external system.
  • Information processing system 1300 can be implemented as a memory card, a solid state disk (SSD) device, a camera image sensor, and another type of application chipset.
  • SSD solid state disk
  • the information processing system 1300 can store a large amount of data stably and reliably.
  • Embodiments of the present invention can be applied to a semiconductor memory device of a three-dimensional structure and a method used in the process of fabricating the semiconductor memory device of the three-dimensional structure.

Abstract

本发明构思提供了半导体存储器件及其制造方法。所述半导体存储器件可以包括：多个栅极，竖直地堆叠在基底上；竖直沟道，填充竖直地贯穿所述多个栅极的沟道孔；存储层，在沟道的内侧壁上竖直地延伸。竖直沟道可以包括：下沟道，填充沟道孔的下部区域并电连接至基底；上沟道，填充沟道孔的上部区域并接触下沟道。上沟道可以在沟道孔的上部区域中沿存储层和下沟道延伸并且可以具有均匀的厚度。

Description

半导体存储器件及其制造方法 技术领域
本发明构思涉及一种半导体，更具体地讲，涉及半导体存储器件和用于制造所述半导体存储器件的方法。
 背景技术
半导体器件因其小尺寸、多功能和/或低制造成本而广泛地用在电子行业。随着电子行业的发展，越来越需要高性能低成本的半导体器件。为了满足上述需要，已经将半导体器件（例如，半导体存储器件）高度集成。
传统的二维（2D）存储器件的集成度主要由单位存储单元占据的面积来确定。因此，传统的2D存储器件的集成度受用于形成精细图案的技术影响很大。然而，因在半导体存储器件的制造中使用的设备的高成本和/或制造工艺的困难，对增大半导体存储器件的集成度会具有一些局限性。已经开发了包括三维布置的存储单元的三维（3D）半导体器件以克服上述局限性。
 技术问题
本发明构思的实施例可以提供具有电气特性改良了的三维（3D）结构的半导体存储器件和用于制造所述半导体存储器件的方法。
 技术解决方案
在一个方面，一种半导体存储器件可以包括：多个栅极，竖直地堆叠在基底上；竖直沟道，填充竖直地贯穿所述多个栅极的沟道孔；存储层，在沟道的内侧壁上竖直地延伸。竖直沟道可以包括：下沟道，填充沟道孔的下部区域并电连接至基底；上沟道，填充沟道孔的上部区域并接触下沟道。上沟道可以在沟道孔的上部区域中沿存储层和下沟道延伸并且可以具有均匀的厚度。
在一些实施例中，存储层可以沿沟道孔的上部区域的内侧壁竖直地延伸并且可以沿下沟道的顶表面水平地延伸，以包括具有L形状的底端部分。
在一些实施例中，下沟道的顶表面可以是平坦的或者可以是朝着远离基底的方向的凸形。
在一些实施例中，上沟道可以沿存储层的L形状的底端部分弯曲地延伸。
在一些实施例中，下沟道的顶表面的一部分可以是凹进的，上沟道的底端部分可以设置在下沟道的顶表面的凹进的区域中。
在一些实施例中，下沟道可以具有完全填充沟道孔的下部区域的柱形形状，上沟道可以具有部分地填充沟道孔的上部区域并且具有均匀的厚度的U型圆柱形结构。
在一些实施例中，所述半导体存储器件还可以包括：绝缘填充层，填充上沟道的圆柱形结构的内空间。
在一些实施例中，存储层可以设置在上沟道和邻近于上沟道的栅极之间，栅极绝缘层可以设置在下沟道和邻近于下沟道的栅极之间。
在一些实施例中，位于下沟道下方的基底可以是凹进的，下沟道的底端部分可以设置在基底的凹进的区域中。
在另一方面，一种半导体存储器件可以包括：栅极堆叠件，包括竖直地堆叠在基底上的至少一个下非存储栅极、多个存储栅极和至少一个上非存储栅极；上沟道，竖直地贯穿所述至少一个上非存储栅极和所述多个存储栅极；下沟道，竖直地贯穿所述至少一个下非存储栅极；存储层，设置在上沟道与所述至少一个上非存储栅极之间以及上沟道与所述多个存储栅极之间。存储层可以具有接触下沟道的L形状的底端部分，上沟道可以沿存储层和下沟道的顶表面延伸并且可以具有均匀的厚度。
在一些实施例中，上沟道的下部分可以具有沿存储层的L形状的底端部分延伸的弯曲形状。
在一些实施例中，上沟道和下沟道可以彼此连接以构成竖直地贯穿栅极堆叠件的竖直沟道，竖直沟道可以电连接至基底。
在一些实施例中，竖直沟道可以填充竖直地贯穿栅极堆叠件的沟道孔。下沟道可以具有完全地填充沟道孔的下部区域的柱形形状，上沟道可以为具有沿沟道孔的上部区域的内侧壁和下沟道的顶表面连续地延伸的圆柱形形状的单层。圆柱形形状的内空间可以填充有绝缘层。
在一些实施例中，存储层可以不设置在下沟道和所述至少一个下非存储栅极之间。
在一些实施例中，存储层可以包括：第一存储层，设置在上沟道与所述至少一个上非存储栅极之间以及上沟道与所述多个存储栅极之间；第二存储层，设置在下沟道与所述至少一个下非存储栅极之间。第二存储层还可以设置在第一存储层与所述至少一个上非存储栅极之间以及第一存储层和所述多个存储栅极之间。
在又一方面，一种用于制造半导体存储器件的方法可以包括：形成竖直地贯穿堆叠在基底上的多个层的沟道孔，沟道孔暴露基底；形成部分地填充沟道孔的下沟道；形成沿沟道孔的内侧壁和下沟道的顶表面延伸的存储层；在存储层上形成沿沟道孔的内侧壁竖直地延伸的间隔件；通过蚀刻工艺利用间隔件作为蚀刻掩模来蚀刻存储层，以暴露下沟道的顶表面的一部分；去除间隔件以暴露存储层；形成沿被暴露的存储层和下沟道的顶表面的被暴露的部分延伸的上沟道。
在一些实施例中，去除间隔件的步骤可以包括：通过提供能够相对于存储层选择性地蚀刻间隔件的气态蚀刻剂来选择性地去除间隔件。
在一些实施例中，存储层和间隔件可以分别包括绝缘层和硅层，气态蚀刻剂可以包括氟（F）、氯（Cl）、溴（Br）、碘（I）、它们的任意化合物或它们的任意组合。
在一些实施例中，所述方法还可以包括：对上沟道进行切边。
在一些实施例中，对上沟道进行切边的步骤可以包括：通过提供包括氨水（NH4OH）、过氧化氢（H2O2）和去离子水的溶液来使上沟道变薄。
 有益效果
根据本发明构思的实施例，由于半导体层共形地形成，因此可以形成具有均匀厚度的上沟道。此外，即使执行用于形成薄沟道的切边工艺，上沟道和下沟道之间的接触特性也会是优异的。因此，能够改善3D半导体存储器件的电气特性。
 附图说明
图1是示出根据本发明构思的示例实施例的半导体存储器件的平面图；
图2A至图2R是沿图1的线A1-A2截取的剖视图，以示出用于制造根据本发明构思的一些实施例的半导体存储器件的方法；
图2I是图2H的一部分的放大的剖视图；
图2K是图2J的一部分的放大的剖视图；
图2R是图2Q的一部分的放大的剖视图；
图3A是示出图2I的比较示例的剖视图；
图3B是示出图2K的比较示例的剖视图；
图4A至图4C是示出图2R的修改示例的剖视图；
图5A至图5D是沿图1的线A1-A2截取的剖视图，以示出用于制造根据本发明构思的其他实施例的半导体存储器件的方法；
图5E是图5D的一部分的放大的剖视图；
图6A是示出包括根据本发明构思的实施例的半导体存储器件的存储卡的示意性框图；以及
图6B是示出包括根据本发明构思的实施例的半导体存储器件的信息处理系统的示意性框图。
 本发明的最佳实施方式
为了解决以上问题，根据本发明的半导体存储器件包括：多个栅极，竖直地堆叠在基底上；竖直沟道，填充竖直地贯穿所述多个栅极的沟道孔；以及存储层，在沟道的内侧壁上竖直地延伸，其中，竖直沟道包括：下沟道，填充沟道孔的下部区域并电连接至基底；上沟道，填充沟道孔的上部区域并接触下沟道，以及其中，上沟道在沟道孔的上部区域中沿存储层和下沟道延伸并具有均匀的厚度。
 本发明的实施方式
现在将参照附图更加充分地描述本发明构思，在附图中示出了本发明构思的示例性实施例。本发明构思的优点和特征以及实现它们的方法将通过下面的示例性实施例而清楚，将参照附图更详细地描述下面的示例性实施例。然而，应该注意的是，本发明构思不限于下面的示例性实施例，并且可以以各种形式来实施。因此，提供示例性实施例，仅为了公开本发明构思并且使本领域技术人员知晓本发明构思的范畴。在附图中，本发明构思的实施例不限于这里提供的具体示例，并且为了清楚而进行了夸大。
这里使用的术语仅出于描述具体实施例的目的，而不意图限制本发明。如这里所使用的，除非上下文另外明确指出，否则单数术语“一个（种）”和“该（所述）”也意图包括复数形式。如这里使用的，术语“和/或”包括一个或更多个相关列出项的任意和所有组合。将理解的是，当元件被称为“连接”或“结合”到另一元件时，它可以直接连接或结合到其他元件，或者可以存在中间元件。
同样地，将理解的是，当诸如层、区域或基底的元件被称为“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者可以存在中间元件。相反，术语“直接”意味着没有中间元件。还将理解的是，术语“包含”和/或“包括”用在本说明书中时说明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除一个或更多个其他特征、整体、步骤、操作、元件、组件和/或它们的组的存在或添加。
此外，将利用作为本发明构思的理想示例性视图的剖视图来描述具体实施方式中的实施例。因此，可根据制造技术和/或允许误差来修改示例性视图的形状。因此，本发明构思的实施例不限于在示例性视图中示出的特定形状，而可包括可根据制造工艺生成的其他形状。附图中举例说明的区域具有一般特性，并用于示出元件的特定形状。因此，这不应该被解释为对本发明构思的范围的限制。
还将理解的是，尽管在这里可使用术语第一、第二、第三等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。因此，在不脱离本发明的教导的情况下，一些实施例中的第一元件可在其他实施例中被命名为第二元件。这里解释并示出的本发明构思的多方面的示例性实施例包括它们的补充相对物。在整个说明书中，相同的标号或相同的标记表示相同的元件。
如通过本发明实体所理解的，根据这里描述的各种实施例的器件和形成器件的方法可以以诸如集成电路的微电子器件来实现，其中，多个根据这里描述的各种实施例的器件集成在同一微电子装置中。因此，这里示出的剖视图可以在微电子器件中沿不需要正交的两个不同的方向重复。因此，使根据这里描述的各种实施例的器件具体化的微电子器件的平面图可以包括基于微电子器件的功能呈阵列和/或呈二维图案的多个器件。
根据这里描述的各个实施例的器件可以根据微电子器件的功能插入在其他器件之中。此外，根据这里描述的各种实施例的微电子器件可以沿可以与所述两个不同的方向正交的第三方向重复，以提供三维集成电路。
因此，这里示出的剖视图对根据这里描述的各种实施例的在平面图中沿两个不同的方向和/或在透视图中沿三个不同的方向延伸的多个器件提供支持。例如，如通过器件/结构的平面图所示出的，当在器件/结构的剖视图中示出单个有源区时，器件/结构可以包括多个有源区和位于有源区上的晶体管结构（或在适当的情况下的存储单元结构、栅极结构等）。
图1是示出根据本发明构思的示例实施例的半导体存储器件的平面图。
参照图1，半导体存储器件1可以包括竖直地位于基底101上的多个竖直沟道140、沿竖直沟道140堆叠的多个栅极160和电连接到竖直沟道140的位线180。半导体存储器件1可以是竖直NAND闪速存储器件，所述竖直NAND闪速存储器件还包括设置在竖直沟道140和栅极160之间的存储层150，如图2Q中所示。
栅极160可以构成邻近于基底101的接地选择线GSL、串选择线SSL以及位于接地选择线GSL和字符选择线SSL之间的字线WL。接地选择线GSL可以具有单层结构或多层结构，串选择线SSL可以具有单层结构或多层结构。每个竖直沟道140的底端可以电连接到基底101，每个竖直沟道140的顶端可以电连接到位线180。
栅极160可以以金字塔形式来堆叠，从而堆叠的栅极160的两个侧壁或四个侧壁可以形成阶梯式结构111。串选择线SSL可以具有沿与位线180的延伸方向交叉的方向延伸的线性形状。位线180的延伸方向可以与线A1-A2平行。例如，串选择线SSL的延伸方向可以与线A1-A2垂直。字线WL和接地选择线GSL可以具有板形状，所述板形状具有沿与线A1-A2交叉的方向延伸的字线切割部（word line cut）107。字线切割部107可以暴露基底101。
半导体存储器件1的竖直沟道140可以包括下沟道141和堆叠在下沟道141上的上沟道145，如图2Q中所示。上沟道145可以与下沟道141接触。在一些实施例中，竖直沟道140可以具有通心粉形状。此外，竖直沟道140可以充分地确保电流通路，从而即使竖直沟道140变薄，在下沟道141和上沟道145之间也没有中断现象（cut phenomenon）。
图2A至图2R是沿图1的线A1-A2截取的剖视图，以示出用于制造根据本发明构思的一些实施例的半导体存储器件的方法。图2I是图2H的一部分的放大的剖视图。图2K是图2J的一部分的放大的剖视图。图2R是图2Q的一部分的放大的剖视图。图3A是示出图2I的比较示例的剖视图。图3B是示出图2K的比较示例的剖视图。
参照图2A，可以在基底101上形成成型堆叠件10。基底101可以包括诸如单晶硅晶片的半导体基底。多个绝缘层110和多个牺牲层120可以交替且重复地堆叠以形成成型堆叠件10。绝缘层110可以是氧化硅层或氮化硅层。每个牺牲层120可以由相对于绝缘层110具有蚀刻选择性并且从由氧化硅、氮化硅、碳化硅、硅和硅-锗组成的组中选择的材料形成。例如，绝缘层110可以是氧化硅（例如，SiOx）层，牺牲层120可以是氮化硅（SiNx）层。牺牲层120的厚度可以彼此基本相等。绝缘层110的厚度可以彼此基本相等。可选择地，至少一个绝缘层110的厚度可以与其他绝缘层110的厚度不同。例如，绝缘层110中的第三绝缘层110c和第七绝缘层110g可以相对厚。绝缘层110可以包括第一绝缘层110a至第九绝缘层110i。牺牲层120可以包括第一牺牲层120a至第八牺牲层120h。
参照图2B，可以将成型堆叠件10图案化以形成竖直沟道孔103。例如，可以通过干法蚀刻工艺形成竖直地贯穿成型堆叠件10的竖直沟道孔103。竖直沟道孔103可以暴露基底101。基底101可能因过度蚀刻而凹进。竖直沟道孔103的宽度可以基本均匀，而与距离基底101的竖直高度无关。可选择地，竖直沟道孔103的宽度可以根据距离基底101的竖直高度而改变。在下文中，作为示例，将描述具有基本均匀宽度的竖直沟道孔103。
参照图2C，可以形成下沟道141，以填充竖直沟道孔103的一部分。下沟道141可以与基底101接触并且可以具有柱形状。下沟道141可以由与基底101具有相同导电类型的半导体形成或由本征半导体形成。例如，下沟道141可以包括P型硅或本征硅。下沟道141可以通过沉积技术由多晶半导体形成，或者可以通过外延生长技术或激光结晶技术由单晶半导体形成。在一些实施例中，下沟道141可以通过单晶P型硅或本征硅的外延生长来形成。下沟道141可以与第一牺牲层120a的侧壁和第二牺牲层120b的侧壁接触。此外，下沟道141还可以与第三绝缘层110c的侧壁的一部分接触。下沟道141的顶表面141s可以是平坦的。如果基底101在竖直沟道孔103的形成期间凹进，则下沟道141的底端部分可以设置在基底101的凹进的区域中，因此，下沟道141的底表面可以比基底101的顶表面101s低。
参照图2D，可以在基底101上形成存储层150和第一半导体层143。存储层150可以沿竖直沟道孔103的内侧壁延伸以覆盖成型堆叠件10。第一半导体层143可以覆盖存储层150。存储层150可以包括利用化学气相沉积（CVD）工艺或原子层沉积（ALD）工艺沉积并且与下沟道141接触的绝缘层。例如，阻挡绝缘层（例如，SiO2或SiO2/Al2O3）、捕获绝缘层（例如，SiN或SiON）和隧道绝缘层（例如，SiO2）可以顺序地沉积以形成存储层150。第一半导体层143可以通过CVD工艺或ALD工艺由半导体（例如，多晶硅或单晶硅）形成。例如，第一半导体层143可以通过CVD工艺由多晶硅形成。在一些实施例中，还可以通过沉积介电材料（例如，SiOx）形成绝缘层190以覆盖第一半导体层143。
参照图2E，可以通过蚀刻工艺（例如，干法蚀刻工艺）来蚀刻第一半导体层143，以将第一半导体层143形成为具有在竖直沟道孔103中覆盖存储层150的竖直间隔件形状。可以通过间隔件蚀刻工艺来暴露存储层150的形成在竖直沟道孔103的底表面上的部分。此外，也可以通过间隔件蚀刻工艺来暴露形成在第九绝缘层110i上的存储层150。
参照图2F，可以蚀刻存储层150以暴露下沟道141的一部分。例如，可以将存储层150湿法蚀刻或干法蚀刻成具有覆盖竖直沟道孔103的内侧壁的竖直形状。可以通过存储层150的蚀刻来去除存储层150的覆盖下沟道141的一部分以暴露下沟道141。第一半导体层143可以在存储层150的蚀刻工艺期间用作覆盖存储层150的掩模，从而可以不去除存储层150的覆盖下沟道141的另一部分。结果，被蚀刻的存储层150的底端部分150b可以具有L形状。
参照图2G，可以去除第一半导体层143。例如，可以用蚀刻剂选择性地去除第一半导体层143。在利用蚀刻剂的去除工艺期间，存储层150的成分（例如，SiO2、SiN、SiON）的蚀刻速率可以比第一半导体层143的成分（例如，多晶硅）的蚀刻速率大。蚀刻剂可以包括氟（F）、氯（Cl）、溴（Br）、碘（I）、它们的任意化合物或它们的任意组合。在一些实施例中，蚀刻剂可以包括处于气相的NF3、SF6、Cl2、HCl、CCl4、HBr、HI、ClF3和CF3Cl中的至少一种。由于下沟道141是晶体，所以在通过蚀刻剂蚀刻第一半导体层143的同时不会蚀刻下沟道141。
参照图2H，可以形成第二半导体层145，以沿竖直沟道孔103的内侧壁延伸并覆盖成型堆叠件10。第二半导体层145可以通过CVD工艺由非晶硅形成。还可以进一步执行热处理工艺以使非晶硅转化为晶体硅。第二半导体层145可以在竖直沟道孔103内具有沿侧面共形地形成的圆柱形形状。
如图2I中所示，第二半导体层145可以具有在竖直沟道孔103内沿存储层150竖直延伸并且在下沟道141上沿存储层150的具有L形状的底端部分150b弯曲的圆柱形形状。由于第二半导体层145沿存储层150和下沟道141延伸并且沿存储层150的底端部分105b弯曲，因此第二半导体层145可以具有基本均匀的厚度T1，而与它的形成位置没有关系。第二半导体层145可以与下沟道141接触，从而用作上沟道。下沟道141和上沟道可以构成下面将在图2L中描述的竖直沟道140。
与本实施例不同，如果没有去除第一半导体层143，然后如图3A中所示形成第二半导体层145，则第一半导体层143和第二半导体层145可以用作接触下沟道141的上沟道。在这种情况下，第一半导体层143和第二半导体层145的厚度之和可以根据它们的形成位置而改变。例如，第一半导体143和第二半导体层145可以在竖直沟道孔103的内侧壁上具有第一厚度T1a，但是在存储层150的底端部分150b上具有比第一厚度T1a小的第二厚度T1b。第二厚度T1b根据第二半导体层145的沉积厚度而会非常小。因此，会使下沟道与上沟道143和145之间的接触特性劣化。
根据本实施例，由于在第二半导体层145的形成之前去除第一半导体层143，因此第二半导体层145可以形成为具有均匀的厚度T1，因此，下沟道141与第二半导体层145之间的接触特性会是优异的。
参照图2J，在一些实施例中，第二半导体层145可以被薄薄地切边。例如，可以利用包括氨水（NH4OH）、过氧化氢（H2O2）和去离子水的SCl（标准清洁剂1）溶液来使第二半导体层145变薄。
如图2K中所示，第二半导体层145可以通过切边工艺具有比初始厚度T1小的厚度T2。在一些实施例中，由于第二半导体层145具有如参照图2I所描述的均匀的初始厚度T1，因此被切边的第二半导体层145可以具有均匀的薄的厚度T2，而与它的形成位置无关。
与本实施例不同，如果形成在第一半导体层143上的第二半导体层145在图3A中示出的状态下被切边，则上沟道143和145可以具有在位于竖直沟道孔103的内侧壁上的第一切边厚度T2a和位于存储层150的底端部分150b上的第二切边厚度T2b。这里，第二切边厚度T2b可以进一步比第一切边厚度T2a小。下沟道141与上沟道143和145之间的接触特性会因进一步变小的第二切边厚度T2b而进一步劣化。另外，下沟道141可能无法连接至上沟道143和145。
根据本实施例，第二半导体层145具有如参照图2I所描述的均匀初始厚度T1，因此，即使如图2K中所示第二半导体层145被切边，下沟道141和第二半导体层145之间的接触特性也会是优异的。
参照图2L，可以在第二半导体层145上形成填充层191。例如，可以在第二半导体层145上沉积氧化硅层或氮化硅层以填充竖直沟道孔103，可以使沉积的氧化硅层或氮化硅层与第二半导体层145平面化直至使成型堆叠件10暴露，从而形成填充层191。因此，第二半导体层145可以形成为在竖直沟道孔103内具有U形状的圆柱形结构。具有圆柱形结构的第二半导体层145被定义为上沟道145。上沟道145可以在竖直沟道孔103内围绕填充层191的侧壁。换言之，可以利用填充层191来填充上沟道145的具有圆柱形结构的内部空间。上沟道145可以与下沟道141的顶表面接触。下沟道141和上沟道145可以构成竖直沟道140。
根据本实施例，上沟道145由单个半导体层（即，第二半导体层）形成，因此在上沟道145内不存在界面。另一方面，如果上沟道如图3B中所示由第一半导体层143和第二半导体层145构成，则会在上沟道中存在界面。在这种情况下，载流子的流动或电流会因该界面而在上沟道中是不均匀的。然而，由于根据本实施例的上沟道145不具有界面，因此在本实施例的上沟道145中载流子的流动或电流可以是基本均匀的。结果，根据本发明构思的半导体存储器件可以具有优异的电特性。
参照图2M，可以在竖直沟道140之间形成暴露基底101的字线切割部107。在一些实施例中，可以干法蚀刻成型堆叠件10以形成贯穿成型堆叠件10的字线切割部107。位于字线切割部107下方的基底101可能因过度蚀刻而凹进。牺牲层120的侧壁和绝缘层110的侧壁可以被字线切割部107暴露。
参照图2N，可以通过字线割切部107提供蚀刻剂以选择性地去除牺牲层120。可以通过牺牲层120的选择性去除来形成包括沿竖直沟道140彼此竖直分隔开的绝缘层110的成型翼件15。例如，如果牺牲层120是氮化硅层，绝缘层110是氧化硅层，则蚀刻剂可以包括磷酸（H3PO4）。可以通过牺牲层120的选择性去除来形成暴露下沟道 141和存储层150的凹进区108。可以对被凹进区108暴露的下沟道141执行绝缘材料的沉积工艺或氧化工艺以形成栅极绝缘层113。
参照图2O，可以分别形成包括第一栅极161至第八栅极168的栅极160以填充凹进区108，从而形成包括被绝缘层110彼此竖直分隔开的栅极161至168的栅极堆叠件20。可以在基底101上沉积导电材料（例如，硅、金属、金属氮化物和/或金属硅化物），然后可以去除凹进区108外侧的导电材料，以形成栅极161至168。
可以将掺杂剂注入至被字线切割部107暴露的基底101中以形成共源极104s。可以利用与基底101的导电类型不同的导电类型的掺杂剂来对共源极104s进行掺杂。例如，可以利用P型掺杂剂对基底101进行掺杂，可以利用N型掺杂剂对共源极104s进行掺杂。
参照图2P，可以形成填充绝缘层171以填充字线切割部107。例如，可以沉积绝缘材料以覆盖栅极堆叠件20，可以使沉积的绝缘材料平面化以形成填充绝缘层171。可以去除竖直沟道140的顶端部分以形成开口105。可以利用硅来填充开口105，可以将掺杂剂注入至所述硅中以形成导电类型与共源极104s的导电类型相同的漏极104d。
参照图2Q，可以形成层间绝缘层173以覆盖栅极堆叠件20，并且可以形成塞182以贯穿层间绝缘层173。塞182可以连接到漏极104d。可以在层间绝缘层173上形成连接到塞182的位线180。位线180可以通过塞182电连接至竖直沟道140。结果，可以形成三维（3D）半导体存储器件1，例如，竖直NAND闪速存储器件。栅极161至168可以在基底101上沿第一水平方向（例如，正向和逆向）延伸，位线可以沿基本垂直于第一水平方向的第二方向（例如，左方向和右方向）延伸。沿竖直沟道140竖直堆叠的栅极161至168可以构成单元串。
栅极161至168的第一栅极161和第二栅极162可以邻近于下沟道141，第三栅极163至第八栅极168可以邻近于上沟道145。第一栅极161和第二栅极162可以是非存储选择栅极，并且可以与接地选择线GSL相对应。第三栅极163至第六栅极166可以是存储栅极，并且可以与字线WL相对应。第七栅极167和第八栅极168可以是非存储选择栅极，并且可以与串选择线SSL相对应。
如图2R中所示，根据本实施例的半导体存储器件1在共源极104s和下沟道141之间不具有使电流通路P增大的存储层150，因此可以使共源极104s和竖直沟道140之间的电流通路P最小化。此外，能够抑制因电流通路P的增大而导致的电阻的增加。由于如参照图2H至图2K描述的上沟道145沿具有L形状的存储层150的底端部分150b具有均匀的厚度，因此即使上沟道145被切边，也可以充分地提供从下沟道141至上沟道145的电流通路所需要的区域90。结果，下沟道141和上沟道145的体接触部144可以提供从下沟道141至上沟道145（或从上沟道145至下沟道141）的电流流动所需要的充足的空间或通路，从而可以在下沟道141和上沟道145之间实现优异的电流流动。短电流通路和/或优异的电流流动可以使半导体存储器件1具有改善的电特性。
图4A至图4C是示出图2R的修改示例的剖视图。
参照图4A，下沟道141可以具有朝着远离基底101的方向的顶表面凸起。例如，如果硅从基底101外延地生长以形成下沟道141，则下沟道141的顶表面141s可以具有凸起形状。
参照图4B，上沟道145可以插入至下沟道141内。例如，如参照图2F所描述的在蚀刻存储层150以暴露下沟道141的一部分的工艺和/或如参照图2G所描述的去除第一半导体层143的工艺期间，也可以蚀刻下沟道141的顶表面的一部分。结果，下沟道141的顶表面的这部分可以凹进，上沟道145的底端部分可以延伸至下沟道141的顶表面的凹进的区域中。
参照图4C，竖直沟道可以由直接连接至基底101的第二半导体层145构成。例如，可以跳过在图2C中描述的下沟道141的形成工艺，从而可以将竖直沟道形成为仅由第二半导体层145构成。在这种情况下，第二半导体层145可以与基底101接触，从而第二半导体层145和基底101可以构成体接触部144。
图5A至图5D是沿图1的线A1-A2截取的剖视图，以示出用于制造根据本发明构思的其他实施例的半导体存储器件的方法。图5E是图5D的一部分的放大的剖视图。
参照图5A，可以通过与参照图2A至图2N描述的工艺相同或相似的工艺来形成成型翼件15。根据本实施例，第一存储层151可以形成为围绕上沟道145。第一存储层151可以包括隧道绝缘层，或者第一存储层151可以包括隧道绝缘层和捕获绝缘层。在本实施例中，可以省略图2N的位于下沟道141的侧壁上的栅极绝缘层113。
参照图5B，可以形成第二存储层152以覆盖凹进区108的内表面。如果第一存储层151包括隧道绝缘层，则第二存储层152可以包括捕获绝缘层和阻挡绝缘层。在另一实施例中，如果第一存储层151包括隧道绝缘层和捕获绝缘层，则第二存储层152可以包括阻挡绝缘层。第一存储层151和第二存储层152可以构成存储层150。
参照图5C，包括第一栅极161至第八栅极168的栅极160可以通过导电材料的沉积工艺和蚀刻工艺形成在凹进区108内。因此，可以形成栅极堆叠件20。栅极堆叠件20可以包括在基底101上沿竖直沟道140竖直堆叠的栅极160。可以将掺杂剂注入至通过字线切割部107暴露的基底101内以形成共源极104s。
参照图5D，可以通过参照图2P和2Q描述的工艺相同或相似的工艺来形成填充绝缘层171、层间绝缘层173、塞182和位线180。填充绝缘层171可以填充字线切割部107，层间绝缘层173可以覆盖栅极堆叠件20。塞182可以贯穿层间绝缘层173从而连接至漏极104d。位线180可以设置在层间绝缘层173上，并且可以通过塞182电连接至竖直沟道140。结果，可以形成3D半导体存储器件2，例如，竖直NAND闪速存储器件。半导体存储器件2的平面结构可以与图1的半导体存储器件1的平面结构相同或相似。
根据本实施例，存储层150可以包括形成在竖直沟道孔103中的第一存储层151和形成在凹进区108中的第二存储层152。第二存储器件2的其他特征可以与图2Q和图2R的半导体存储器件1的相应特征相同。
图6A是示出包括根据本发明构思的实施例的半导体存储器件的存储卡的示意性框图。图6B是示出包括根据本发明构思的实施例的半导体存储器件的信息处理系统的示意性框图。
参照图6A，闪速存储器1210可以包括根据本发明构思的前述实施例的半导体存储器件1和半导体存储器件2中的至少一个。闪速存储器1210可以应用于存储卡1200。例如，存储卡1200可以包括控制在主机1230和闪速存储器1210之间的数据通信的存储控制器1220。静态随机存取存储（SRAM）器件1221可以用作中央处理单元（CPU）1222的工作存储器。主机接口单元1223可以被构造成包括存储卡1200和主机1230之间的数据通信协议。错误检查和校正（ECC）块1224可以检测并校正从存储器件1210读出的数据的错误。存储接口单元1225可以与存储器件1210通过接口连接。CPU 1222控制存储控制器1220的整体操作。
参照图6B，信息处理系统1300可以包括具有根据本发明构思的前述实施例的半导体存储器件1和半导体存储器件2中的至少一个的存储系统1310。信息处理系统1300可以包括移动设备或计算机。例如，信息处理系统1300可以包括调制解调器1320、中央处理单元（CPU）1330、随机存取存储器（RAM）1340和通过系统总线1360电连接至存储系统1310的用户接口单元1350。存储系统1310可以包括闪速存储器1311和存储控制器1312。存储系统1310可以具有与图6A示出的存储卡1200基本相同的结构。存储系统1310可以存储经CPU 1330处理过的数据或从外部系统输入的数据。信息处理系统1300可以被实现为存储卡、固态盘（SSD）装置、相机图像传感器和另一类型的应用程序芯片组。例如，如果存储系统1310可以实现为SSD装置，则信息处理系统1300可以稳定地并可靠地存储大量数据。
尽管已经参照示例实施例描述了本发明构思，但是对于本领域技术人员将明显的是，在不脱离本发明构思的精神和范围的情况下可做出各种改变和修改。因此，应该理解的是，以上实施例不是限制性的，而是示例性的。因此，由权利要求及其等同物的最宽的可许可的解释来确定本发明构思的范围，并且本发明构思的范围不应受前面的描述的限定或限制。
 工业实用性
本发明的实施例能够应用于三维结构的半导体存储器件以及制造所述三维结构的半导体存储器件过程中所使用的方法。

Claims (20)

  1. 一种半导体存储器件，所述半导体存储器件包括：
    多个栅极，竖直地堆叠在基底上；
    竖直沟道，填充竖直地贯穿所述多个栅极的沟道孔；以及
    存储层，在沟道的内侧壁上竖直地延伸，
    其中，竖直沟道包括：下沟道，填充沟道孔的下部区域并电连接至基底；上沟道，填充沟道孔的上部区域并接触下沟道，以及
    其中，上沟道在沟道孔的上部区域中沿存储层和下沟道延伸并具有均匀的厚度。
  2. 如权利要求1所述的半导体存储器件，其中，存储层沿沟道孔的上部区域的内侧壁竖直地延伸并且沿下沟道的顶表面水平地延伸，以包括具有L形状的底端部分。
  3. 如权利要求2所述的半导体存储器件，其中，下沟道的顶表面是平坦的或者是朝着远离基底的方向的凸形。
  4. 如权利要求2所述的半导体存储器件，其中，上沟道沿存储层的L形状的底端部分弯曲地延伸。
  5. 如权利要求2所述的半导体存储器件，其中，下沟道的顶表面的一部分是凹进的，以及
    其中，上沟道的底端部分设置在下沟道的顶表面的凹进的区域中。
  6. 如权利要求1所述的半导体存储器件，其中，下沟道具有完全填充沟道孔的下部区域的柱形形状，以及
    其中，上沟道具有部分地填充沟道孔的上部区域并且具有均匀的厚度的U型圆柱形结构。
  7. 如权利要求6所述的半导体存储器件，所述半导体存储器件还包括：
    绝缘填充层，填充上沟道的圆柱形结构的内空间。
  8. 如权利要求1所述的半导体存储器件，其中，存储层设置在上沟道和邻近于上沟道的栅极之间，以及
    其中，栅极绝缘层设置在下沟道和邻近于下沟道的栅极之间。
  9. 如权利要求1所述的半导体存储器件，其中，位于下沟道下方的基底是凹进的，以及
    其中，下沟道的底端部分设置在基底的凹进的区域中。
  10. 一种半导体存储器件，所述半导体存储器件包括：
    栅极堆叠件，包括竖直地堆叠在基底上的至少一个下非存储栅极、多个存储栅极和至少一个上非存储栅极；
    上沟道，竖直地贯穿所述至少一个上非存储栅极和所述多个存储栅极；
    下沟道，竖直地贯穿所述至少一个下非存储栅极；以及
    存储层，设置在上沟道与所述至少一个上非存储栅极之间以及上沟道与所述多个存储栅极之间，
    其中，存储层具有接触下沟道的L形状的底端部分，以及
    其中，上沟道沿存储层和下沟道的顶表面延伸并具有均匀的厚度。
  11. 如权利要求10所述的半导体存储器件，其中，上沟道的下部分具有沿存储层的L形状的底端部分延伸的弯曲形状。
  12. 如权利要求10所述的半导体存储器件，其中，上沟道和下沟道彼此连接以构成竖直地贯穿栅极堆叠件的竖直沟道，以及
    其中，竖直沟道电连接至基底。
  13. 如权利要求12所述的半导体存储器件，其中，竖直沟道填充竖直地贯穿栅极堆叠件的沟道孔，
    其中，下沟道具有完全地填充沟道孔的下部区域的柱形形状，
    其中，上沟道为具有沿沟道孔的上部区域的内侧壁和下沟道的顶表面连续地延伸的圆柱形形状的单层，以及
    其中，圆柱形形状的内空间填充有绝缘层。
  14. 如权利要求11所述的半导体存储器件，其中，存储层没有设置在下沟道和所述至少一个下非存储栅极之间。
  15. 如权利要求11所述的半导体存储器件，其中，存储层包括：
    第一存储层，设置在上沟道与所述至少一个上非存储栅极之间以及上沟道与所述多个存储栅极之间；以及
    第二存储层，设置在下沟道与所述至少一个下非存储栅极之间，
    其中，第二存储层还设置在第一存储层与所述至少一个上非存储栅极之间以及第一存储层和所述多个存储栅极之间。
  16. 一种用于制造半导体存储器件的方法，所述方法包括下述步骤：
    形成竖直地贯穿堆叠在基底上的多个层的沟道孔，沟道孔暴露基底；
    形成部分地填充沟道孔的下沟道；
    形成沿沟道孔的内侧壁和下沟道的顶表面延伸的存储层；
    在存储层上形成沿沟道孔的内侧壁竖直地延伸的间隔件；
    通过蚀刻工艺利用间隔件作为蚀刻掩模来蚀刻存储层，以暴露下沟道的顶表面的一部分；
    去除间隔件以暴露存储层；以及
    形成沿被暴露的存储层和下沟道的顶表面的被暴露的部分延伸的上沟道。
  17. 如权利要求16所述的方法，其中，去除间隔件的步骤包括：
    通过提供能够相对于存储层选择性地蚀刻间隔件的气态蚀刻剂来选择性地去除间隔件。
  18. 如权利要求17所述的方法，其中，存储层和间隔件分别包括绝缘层和硅层，以及
    其中，气态蚀刻剂包括氟、氯、溴、碘、它们的任意化合物或它们的任意组合。
  19. 如权利要求16所述的方法，所述方法还包括：
    对上沟道进行切边。
  20. 如权利要求19所述的方法，其中，对上沟道进行切边的步骤包括：
    通过提供包括氨水、过氧化氢和去离子水的溶液来使上沟道变薄。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109449162A (zh) * 2018-10-16 2019-03-08 长江存储科技有限责任公司 3d存储器件的制造方法及3d存储器件

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9917099B2 (en) * 2016-03-09 2018-03-13 Toshiba Memory Corporation Semiconductor device having vertical channel between stacked electrode layers and insulating layers
KR102609516B1 (ko) * 2016-05-04 2023-12-05 삼성전자주식회사 반도체 장치
US9911754B1 (en) * 2016-10-07 2018-03-06 Macronix International Co., Ltd. 3D memory structure
US10020314B1 (en) * 2017-03-02 2018-07-10 Sandisk Technologies Llc Forming memory cell film in stack opening
KR20180137264A (ko) * 2017-06-16 2018-12-27 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR102385568B1 (ko) * 2017-07-13 2022-04-12 삼성전자주식회사 수직형 메모리 장치
US20200051994A1 (en) * 2018-08-10 2020-02-13 Applied Materials, Inc. Memory device improvement
US11121258B2 (en) * 2018-08-27 2021-09-14 Micron Technology, Inc. Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods
KR20200047909A (ko) * 2018-10-26 2020-05-08 삼성전자주식회사 3차원 반도체 메모리 장치
CN111063683B (zh) * 2019-12-06 2022-08-30 中国科学院微电子研究所 具有u形沟道的半导体装置及包括其的电子设备
KR20210092091A (ko) 2020-01-15 2021-07-23 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
CN111357110A (zh) * 2020-02-17 2020-06-30 长江存储科技有限责任公司 用于在三维存储器件中形成沟道结构的方法
US11968833B2 (en) * 2021-01-15 2024-04-23 Macronix International Co., Ltd. Memory device with vertically separated channels
CN112713152B (zh) * 2021-02-07 2023-07-11 长江存储科技有限责任公司 一种三维存储器的制作方法及三维存储器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100178755A1 (en) * 2009-01-14 2010-07-15 Samsung Electronics Co., Ltd. Method of fabricating nonvolatile memory device
US20130161731A1 (en) * 2011-12-22 2013-06-27 Jin Ho Bin Semiconductor device and method of manufacturing the same
KR20130086778A (ko) * 2012-01-26 2013-08-05 삼성전자주식회사 수직형 비휘발성 메모리 소자의 제조 방법
US20140070302A1 (en) * 2012-09-11 2014-03-13 Dongchul Yoo Three-dimensional semiconductor memory device and method for fabricating the same
US20140199815A1 (en) * 2013-01-17 2014-07-17 Sung-Min Hwang Methods of manufacturing a semiconductor device

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4939955B2 (ja) 2007-01-26 2012-05-30 株式会社東芝 不揮発性半導体記憶装置
KR101014854B1 (ko) 2008-08-25 2011-02-16 주식회사 하이닉스반도체 수직 구조의 플래시 메모리소자 제조방법
KR101551901B1 (ko) 2008-12-31 2015-09-09 삼성전자주식회사 반도체 기억 소자 및 그 형성 방법
KR101603731B1 (ko) 2009-09-29 2016-03-16 삼성전자주식회사 버티칼 낸드 전하 트랩 플래시 메모리 디바이스 및 제조방법
US9536970B2 (en) * 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
KR101763420B1 (ko) * 2010-09-16 2017-08-01 삼성전자주식회사 3차원 반도체 기억 소자 및 그 제조 방법
KR101825539B1 (ko) 2010-10-05 2018-03-22 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR101800438B1 (ko) * 2010-11-05 2017-11-23 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR101842900B1 (ko) 2011-02-16 2018-03-29 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR101916222B1 (ko) 2011-04-29 2018-11-08 삼성전자 주식회사 수직 구조의 비휘발성 메모리 소자 및 그 제조 방법
KR20130057670A (ko) * 2011-11-24 2013-06-03 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
KR102007274B1 (ko) * 2013-01-15 2019-08-05 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
KR102081195B1 (ko) * 2013-08-28 2020-02-25 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102130558B1 (ko) * 2013-09-02 2020-07-07 삼성전자주식회사 반도체 장치
KR102101841B1 (ko) * 2013-10-28 2020-04-17 삼성전자 주식회사 수직형 비휘발성 메모리 소자
KR102039708B1 (ko) * 2013-11-13 2019-11-01 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
KR102245649B1 (ko) * 2014-03-31 2021-04-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102190350B1 (ko) * 2014-05-02 2020-12-11 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법
CN106663682B (zh) * 2014-06-23 2019-09-03 三星电子株式会社 制造半导体装置的方法
KR102248205B1 (ko) * 2014-06-25 2021-05-04 삼성전자주식회사 수직 채널 및 에어 갭을 갖는 반도체 소자
KR102235046B1 (ko) * 2014-07-02 2021-04-05 삼성전자주식회사 3차원 반도체 메모리 장치
KR102240024B1 (ko) * 2014-08-22 2021-04-15 삼성전자주식회사 반도체 장치, 반도체 장치의 제조방법 및 에피택시얼층의 형성방법
US10332904B2 (en) * 2016-09-20 2019-06-25 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100178755A1 (en) * 2009-01-14 2010-07-15 Samsung Electronics Co., Ltd. Method of fabricating nonvolatile memory device
US20130161731A1 (en) * 2011-12-22 2013-06-27 Jin Ho Bin Semiconductor device and method of manufacturing the same
KR20130086778A (ko) * 2012-01-26 2013-08-05 삼성전자주식회사 수직형 비휘발성 메모리 소자의 제조 방법
US20140070302A1 (en) * 2012-09-11 2014-03-13 Dongchul Yoo Three-dimensional semiconductor memory device and method for fabricating the same
US20140199815A1 (en) * 2013-01-17 2014-07-17 Sung-Min Hwang Methods of manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109449162A (zh) * 2018-10-16 2019-03-08 长江存储科技有限责任公司 3d存储器件的制造方法及3d存储器件

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