JP2000067577A5 - - Google Patents

Download PDF

Info

Publication number
JP2000067577A5
JP2000067577A5 JP1998292561A JP29256198A JP2000067577A5 JP 2000067577 A5 JP2000067577 A5 JP 2000067577A5 JP 1998292561 A JP1998292561 A JP 1998292561A JP 29256198 A JP29256198 A JP 29256198A JP 2000067577 A5 JP2000067577 A5 JP 2000067577A5
Authority
JP
Japan
Prior art keywords
circuit
memory cell
signal
data
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998292561A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000067577A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP10292561A priority Critical patent/JP2000067577A/ja
Priority claimed from JP10292561A external-priority patent/JP2000067577A/ja
Priority to US09/272,194 priority patent/US6337832B1/en
Publication of JP2000067577A publication Critical patent/JP2000067577A/ja
Priority to US10/025,857 priority patent/US6522599B2/en
Priority to US10/339,288 priority patent/US6724686B2/en
Publication of JP2000067577A5 publication Critical patent/JP2000067577A5/ja
Pending legal-status Critical Current

Links

JP10292561A 1998-06-10 1998-10-14 同期型半導体記憶装置 Pending JP2000067577A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP10292561A JP2000067577A (ja) 1998-06-10 1998-10-14 同期型半導体記憶装置
US09/272,194 US6337832B1 (en) 1998-06-10 1999-03-18 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
US10/025,857 US6522599B2 (en) 1998-06-10 2001-12-26 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
US10/339,288 US6724686B2 (en) 1998-06-10 2003-01-10 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16247798 1998-06-10
JP10-162477 1998-06-10
JP10292561A JP2000067577A (ja) 1998-06-10 1998-10-14 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000067577A JP2000067577A (ja) 2000-03-03
JP2000067577A5 true JP2000067577A5 (enExample) 2005-11-24

Family

ID=26488259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10292561A Pending JP2000067577A (ja) 1998-06-10 1998-10-14 同期型半導体記憶装置

Country Status (2)

Country Link
US (3) US6337832B1 (enExample)
JP (1) JP2000067577A (enExample)

Families Citing this family (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6560669B1 (en) * 1998-05-19 2003-05-06 Micron Technology, Inc. Double data rate synchronous memory with block-write
KR100431384B1 (ko) * 1998-12-15 2004-05-14 마츠시타 덴끼 산교 가부시키가이샤 클럭 위상 조정 방법, 및 집적 회로와 그 설계 방법
US6516363B1 (en) 1999-08-06 2003-02-04 Micron Technology, Inc. Output data path having selectable data rates
US6694416B1 (en) * 1999-09-02 2004-02-17 Micron Technology, Inc. Double data rate scheme for data output
JP4071910B2 (ja) * 1999-12-09 2008-04-02 富士通株式会社 半導体集積回路
EP1122735B1 (en) * 2000-01-31 2010-09-01 STMicroelectronics Srl Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
JP2002007200A (ja) * 2000-06-16 2002-01-11 Nec Corp メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体
KR100374641B1 (ko) * 2000-11-24 2003-03-04 삼성전자주식회사 스탠바이 모드에서 지연동기 루프회로의 전력소모를감소시키기 위한 제어회로를 구비하는 반도체 메모리장치및 이의 파우워 다운 제어방법
US6651122B2 (en) * 2000-12-07 2003-11-18 Micron Technology, Inc. Method of detecting a source strobe event using change detection
TW527537B (en) * 2001-01-03 2003-04-11 Leadtek Research Inc Conversion device of SDR and DDR, and interface card, motherboard and memory module interface using the same
JP4808856B2 (ja) * 2001-04-06 2011-11-02 富士通セミコンダクター株式会社 半導体記憶装置
US7003643B1 (en) 2001-04-16 2006-02-21 Micron Technology, Inc. Burst counter controller and method in a memory device operable in a 2-bit prefetch mode
JP2002319296A (ja) * 2001-04-19 2002-10-31 Nec Corp 半導体装置及びシステム及び方法
KR100408716B1 (ko) * 2001-06-29 2003-12-11 주식회사 하이닉스반도체 오토프리챠지 갭리스 보호회로를 가진 반도체 메모리소자의 오토프리챠지장치
JP2003045200A (ja) * 2001-08-02 2003-02-14 Mitsubishi Electric Corp 半導体モジュールおよびそれに用いる半導体記憶装置
US6798259B2 (en) * 2001-08-03 2004-09-28 Micron Technology, Inc. System and method to improve the efficiency of synchronous mirror delays and delay locked loops
US7082071B2 (en) * 2001-08-23 2006-07-25 Integrated Device Technology, Inc. Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes
US6795360B2 (en) * 2001-08-23 2004-09-21 Integrated Device Technology, Inc. Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes
US6687184B2 (en) * 2001-08-28 2004-02-03 Micron Technology, Inc. Memory device having selectable clock input and method for operating same
JP2003067324A (ja) * 2001-08-29 2003-03-07 Oki Electric Ind Co Ltd インタフェース回路
JP4694067B2 (ja) * 2001-09-28 2011-06-01 富士通セミコンダクター株式会社 半導体記憶装置
US6647538B1 (en) * 2001-11-08 2003-11-11 Lsi Logic Corporation Apparatus and method for signal skew characterization utilizing clock division
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
JP2003281890A (ja) * 2002-03-25 2003-10-03 Mitsubishi Electric Corp 同期型半導体記憶装置
US6819602B2 (en) * 2002-05-10 2004-11-16 Samsung Electronics Co., Ltd. Multimode data buffer and method for controlling propagation delay time
US7149824B2 (en) 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
KR100486263B1 (ko) * 2002-09-19 2005-05-03 삼성전자주식회사 Ｓｄｒ/ｄｄｒ 겸용 반도체 메모리 장치의 데이터 출력 회로
KR100498448B1 (ko) * 2002-09-30 2005-07-01 삼성전자주식회사 데이터 버스 사이의 커플링을 최소화하는 동기식 반도체장치 및 방법
DE10246790B4 (de) * 2002-10-08 2013-10-31 Qimonda Ag Integrierter Speicher
KR100510512B1 (ko) * 2002-11-18 2005-08-26 삼성전자주식회사 이중 데이터율 동기식 반도체 장치의 데이터 출력 회로 및그 방법
JP4257830B2 (ja) 2003-03-11 2009-04-22 パナソニック株式会社 データ送受信装置
US7051171B1 (en) 2003-04-11 2006-05-23 Broadlogic Network Technologies, Inc. Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM
US6928027B2 (en) * 2003-04-11 2005-08-09 Qualcomm Inc Virtual dual-port synchronous RAM architecture
US7177379B1 (en) 2003-04-29 2007-02-13 Advanced Micro Devices, Inc. DDR on-the-fly synchronization
US7120075B1 (en) 2003-08-18 2006-10-10 Integrated Device Technology, Inc. Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching
US7089439B1 (en) 2003-09-03 2006-08-08 T-Ram, Inc. Architecture and method for output clock generation on a high speed memory device
US6947349B1 (en) 2003-09-03 2005-09-20 T-Ram, Inc. Apparatus and method for producing an output clock pulse and output clock generator using same
US7464282B1 (en) 2003-09-03 2008-12-09 T-Ram Semiconductor, Inc. Apparatus and method for producing dummy data and output clock generator using same
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
KR100546389B1 (ko) * 2003-10-22 2006-01-26 삼성전자주식회사 카스 레이턴시에 따라 동기되는 타이밍이 변하는 반도체메모리 장치
US20050138857A1 (en) * 2003-11-26 2005-06-30 Markley Duane C. Transmitting control device for a navigable fishing apparatus and a fishing pole and transmitter assembly
US7016235B2 (en) * 2004-03-03 2006-03-21 Promos Technologies Pte. Ltd. Data sorting in memories
KR100546135B1 (ko) * 2004-05-17 2006-01-24 주식회사 하이닉스반도체 지연 고정 루프를 포함하는 메모리 장치
US7084686B2 (en) * 2004-05-25 2006-08-01 Micron Technology, Inc. System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US7245551B2 (en) * 2004-08-19 2007-07-17 Micron Technology, Inc. Read command triggered synchronization circuitry
US7078951B2 (en) * 2004-08-27 2006-07-18 Micron Technology, Inc. System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
JP4632121B2 (ja) * 2004-12-14 2011-02-16 エルピーダメモリ株式会社 半導体記憶装置
JP4771961B2 (ja) * 2004-12-24 2011-09-14 スパンション エルエルシー 同期型記憶装置、およびその制御方法
US7401179B2 (en) * 2005-01-21 2008-07-15 Infineon Technologies Ag Integrated circuit including a memory having low initial latency
JPWO2006080065A1 (ja) * 2005-01-27 2008-06-19 スパンション エルエルシー 記憶装置、およびその制御方法
US20060184726A1 (en) * 2005-02-11 2006-08-17 Nokia Corporation Flexible access and control of Dynamic Random Access Memory
US7423919B2 (en) * 2005-05-26 2008-09-09 Micron Technology, Inc. Method and system for improved efficiency of synchronous mirror delays and delay locked loops
US7349289B2 (en) * 2005-07-08 2008-03-25 Promos Technologies Inc. Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM
JP2007066026A (ja) * 2005-08-31 2007-03-15 Renesas Technology Corp 半導体装置とその試験方法及び製造方法
US7450944B2 (en) * 2005-11-03 2008-11-11 Motorola, Inc. Method and apparatus for base station synchronization
KR100743494B1 (ko) * 2006-02-28 2007-07-30 삼성전자주식회사 직렬화 방법과, 이를 이용한 반도체 메모리 장치의 고속데이터 출력 테스트 방법
JP5226669B2 (ja) * 2006-04-24 2013-07-03 サンディスク テクノロジィース インコーポレイテッド 高効率フラッシュメモリデータ転送
US7434121B2 (en) * 2006-05-30 2008-10-07 Infineon Technologies Flash Gmbh & Co. Kg Integrated memory device and method for its testing and manufacture
US7483334B2 (en) * 2006-09-26 2009-01-27 Micron Technology, Inc. Interleaved input signal path for multiplexed input
KR100829455B1 (ko) * 2006-11-13 2008-05-15 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 출력 제어신호 생성회로 및방법
KR100826649B1 (ko) * 2006-11-24 2008-05-06 주식회사 하이닉스반도체 딥 파워다운 모드 제어 회로
US20080137472A1 (en) * 2006-12-07 2008-06-12 Josef Schnell Memory including first and second receivers
CN101617371B (zh) * 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
US7624225B2 (en) * 2007-03-22 2009-11-24 International Business Machines Corporation System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system
KR100870753B1 (ko) * 2007-06-20 2008-11-26 스펜션 엘엘씨 동기형 기억 장치 및 그 제어 방법
US7573307B2 (en) * 2007-08-01 2009-08-11 Texas Instruments Incorporated Systems and methods for reduced area delay locked loop
US7864623B2 (en) * 2008-05-22 2011-01-04 Elpida Memory, Inc. Semiconductor device having latency counter
WO2010013340A1 (ja) * 2008-07-31 2010-02-04 富士通株式会社 データ転送装置、データ送信装置、データ受信装置およびデータ転送方法
KR101033464B1 (ko) * 2008-12-22 2011-05-09 주식회사 하이닉스반도체 반도체 집적 회로
JP2010182358A (ja) * 2009-02-04 2010-08-19 Elpida Memory Inc 半導体装置
JP2010192030A (ja) * 2009-02-17 2010-09-02 Elpida Memory Inc 半導体記憶装置及びこれを備えるメモリモジュール、並びに、データ処理システム
US20100268897A1 (en) * 2009-04-16 2010-10-21 Keishi Okamoto Memory device and memory device controller
JP2010257540A (ja) * 2009-04-27 2010-11-11 Toshiba Corp 不揮発性半導体記憶装置
JP4772891B2 (ja) 2009-06-30 2011-09-14 株式会社東芝 ホストコントローラ、コンピュータ端末およびカードアクセス方法
US8352834B2 (en) 2009-11-12 2013-01-08 Broadlogic Network Technologies Inc. High throughput interleaver / deinterleaver
JP2011138567A (ja) * 2009-12-25 2011-07-14 Toshiba Corp 半導体記憶装置
US8040747B2 (en) * 2009-12-30 2011-10-18 Hynix Semiconductor Inc. Circuit and method for controlling precharge in semiconductor memory apparatus
JP2011180713A (ja) * 2010-02-26 2011-09-15 Elpida Memory Inc 半導体メモリモジュール
JP2012198965A (ja) * 2011-03-22 2012-10-18 Toshiba Corp 不揮発性半導体記憶装置
CN102508804A (zh) * 2011-10-20 2012-06-20 豪威科技(上海)有限公司 Sd/sdio主控制器
US8611178B2 (en) * 2011-11-11 2013-12-17 Qualcomm Incorporated Device and method to perform memory operations at a clock domain crossing
US8817564B2 (en) * 2012-05-21 2014-08-26 Elite Semiconductor Memory Technology Inc. Circuit for sensing multi-level cell
US9520169B2 (en) * 2013-02-25 2016-12-13 Longitude Semiconductor S.A.R.L. Semiconductor device
US9036434B1 (en) * 2013-10-31 2015-05-19 Nanya Technology Corporation Random access memory and method of adjusting read timing thereof
US9804793B2 (en) * 2016-03-04 2017-10-31 Intel Corporation Techniques for a write zero operation
KR20170111572A (ko) 2016-03-29 2017-10-12 삼성전자주식회사 반도체 메모리 장치 및 이의 동작 방법
US10402110B2 (en) 2016-08-04 2019-09-03 Rambus Inc. Adjustable access energy and access latency memory system and devices
KR102647419B1 (ko) * 2016-09-28 2024-03-14 에스케이하이닉스 주식회사 반도체장치
US9728236B1 (en) * 2016-10-21 2017-08-08 Dell Products, Lp System and method of training optimization for dual channel memory modules
US10249351B2 (en) 2016-11-06 2019-04-02 Intel Corporation Memory device with flexible internal data write control circuitry
US10490239B2 (en) 2016-12-27 2019-11-26 Intel Corporation Programmable data pattern for repeated writes to memory
US10884639B2 (en) * 2017-02-27 2021-01-05 Qualcomm Incorporated Providing single data rate (SDR) mode or double data rate (DDR) mode for the command and address (CA) bus of registering clock drive (RCD) for dynamic random access memory (DRAM)
US10437514B2 (en) 2017-10-02 2019-10-08 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
US10467158B2 (en) 2017-11-29 2019-11-05 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
US10332575B2 (en) 2017-11-29 2019-06-25 Micron Technology, Inc. Signal training for prevention of metastability due to clocking indeterminacy
KR102511341B1 (ko) * 2018-02-27 2023-03-20 에스케이하이닉스 주식회사 메모리 장치, 메모리 컨트롤러 및 이들을 포함하는 메모리 시스템과, 이들의 동작 방법
US10937473B2 (en) * 2018-08-08 2021-03-02 Micron Technology, Inc. Clock signal drivers for read and write memory operations
US11609870B2 (en) * 2018-12-04 2023-03-21 Rambus lnc. Off-module data buffer
JP7235389B2 (ja) * 2019-03-29 2023-03-08 ラピスセミコンダクタ株式会社 半導体記憶装置
US10847207B2 (en) 2019-04-08 2020-11-24 Micron Technology, Inc. Apparatuses and methods for controlling driving signals in semiconductor devices
US10910027B2 (en) 2019-04-12 2021-02-02 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
US10937476B2 (en) 2019-06-24 2021-03-02 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
US10854273B1 (en) 2019-06-24 2020-12-01 Micron Technology, Inc. Apparatuses and methods for controlling word drivers
US10854272B1 (en) 2019-06-24 2020-12-01 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
US10854274B1 (en) 2019-09-26 2020-12-01 Micron Technology, Inc. Apparatuses and methods for dynamic timing of row pull down operations
US11205470B2 (en) 2020-04-20 2021-12-21 Micron Technology, Inc. Apparatuses and methods for providing main word line signal with dynamic well
US10998020B1 (en) * 2020-05-05 2021-05-04 Realtek Semiconductor Corporation Memory system and memory access interface device thereof
US11442494B2 (en) 2020-06-08 2022-09-13 Analog Devices, Inc. Apparatus and methods for controlling a clock signal
JP6970244B1 (ja) * 2020-06-23 2021-11-24 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. メモリコントローラ
US11526453B1 (en) 2021-08-13 2022-12-13 Micron Technology, Inc. Apparatus including parallel pipelines and methods of manufacturing the same
US11562781B1 (en) * 2021-10-13 2023-01-24 Infineon Technologies LLC Memory devices with low pin count interfaces, and corresponding methods and systems
US11990175B2 (en) 2022-04-01 2024-05-21 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
CN116597878B (zh) * 2023-07-17 2023-12-01 长鑫存储技术有限公司 数据处理电路及存储器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384745A (en) 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
US5947893A (en) 1994-04-27 1999-09-07 Board Of Regents, The University Of Texas System Method of making a porous prothesis with biodegradable coatings
JPH0973776A (ja) * 1995-09-07 1997-03-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH09180435A (ja) 1995-12-28 1997-07-11 Mitsubishi Electric Corp 半導体記憶装置
JPH09198861A (ja) 1996-01-16 1997-07-31 Mitsubishi Electric Corp 同期型半導体記憶装置
JP3893167B2 (ja) 1996-04-26 2007-03-14 株式会社ルネサステクノロジ 同期型半導体記憶装置
JPH10163451A (ja) * 1996-12-02 1998-06-19 Hitachi Ltd 半導体記憶装置
JP4059951B2 (ja) * 1997-04-11 2008-03-12 株式会社ルネサステクノロジ 半導体記憶装置
JPH11203862A (ja) 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体記憶装置
JPH11306757A (ja) 1998-04-27 1999-11-05 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH11339493A (ja) 1998-05-27 1999-12-10 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000011639A (ja) 1998-06-19 2000-01-14 Mitsubishi Electric Corp 半導体記憶装置
JP2000030448A (ja) 1998-07-15 2000-01-28 Mitsubishi Electric Corp 同期型半導体記憶装置
JP4190662B2 (ja) * 1999-06-18 2008-12-03 エルピーダメモリ株式会社 半導体装置及びタイミング制御回路

Similar Documents

Publication Publication Date Title
JP2000067577A5 (enExample)
JP5123336B2 (ja) パイプラッチ回路を有するメモリ素子のデータ伝達方法
JP3386705B2 (ja) 半導体記憶装置およびそのバーストアドレスカウンタ
JP3730898B2 (ja) データ・ストローブ・プロトコルを使用した主記憶装置
JP2004523056A5 (enExample)
KR100495917B1 (ko) 고속 데이터 출력을 위한 파이프래치 회로
JP2001273774A5 (enExample)
KR100255511B1 (ko) 이중센싱출력경로를구비한동기화메모리장치
JPH07321820A (ja) 相互接続点メモリ
KR100532441B1 (ko) 레이턴시 회로를 구비하는 반도체 메모리 장치 및 그데이터 출력 제어 방법
US6510087B2 (en) Semiconductor memory device
JP4756729B2 (ja) 半導体記憶装置
JPS6386630A (ja) 並列伝送路におけるフレ−ム同期方式
KR20020025665A (ko) 반도체 집적 회로
JP3090104B2 (ja) 半導体メモリ装置
KR100486199B1 (ko) 반도체메모리장치의하이임피던스제어신호발생회로
KR102812286B1 (ko) 싱글 포트 구조를 활용한 동기식 이중 포트 메모리 구현 방법
JP2723546B2 (ja) ディレイ回路
JP2871975B2 (ja) 半導体メモリ装置
JPH06290584A (ja) 半導体記憶装置
KR970051251A (ko) 반도체 메모리 장치
JPH0750950B2 (ja) 時分割スイッチ
JP2560863B2 (ja) 放送選択スイッチ
JPS63215197A (ja) 時間スイツチ回路
JPH06350551A (ja) Ｔｓａ回路