JP2000067577A - 同期型半導体記憶装置 - Google Patents

同期型半導体記憶装置

Info

Publication number
JP2000067577A
JP2000067577A JP10292561A JP29256198A JP2000067577A JP 2000067577 A JP2000067577 A JP 2000067577A JP 10292561 A JP10292561 A JP 10292561A JP 29256198 A JP29256198 A JP 29256198A JP 2000067577 A JP2000067577 A JP 2000067577A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
data
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10292561A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000067577A5 (enExample
Inventor
Tsukasa Oishi
司 大石
Masatoshi Ishikawa
正敏 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10292561A priority Critical patent/JP2000067577A/ja
Priority to US09/272,194 priority patent/US6337832B1/en
Publication of JP2000067577A publication Critical patent/JP2000067577A/ja
Priority to US10/025,857 priority patent/US6522599B2/en
Priority to US10/339,288 priority patent/US6724686B2/en
Publication of JP2000067577A5 publication Critical patent/JP2000067577A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
JP10292561A 1998-06-10 1998-10-14 同期型半導体記憶装置 Pending JP2000067577A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP10292561A JP2000067577A (ja) 1998-06-10 1998-10-14 同期型半導体記憶装置
US09/272,194 US6337832B1 (en) 1998-06-10 1999-03-18 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
US10/025,857 US6522599B2 (en) 1998-06-10 2001-12-26 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
US10/339,288 US6724686B2 (en) 1998-06-10 2003-01-10 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16247798 1998-06-10
JP10-162477 1998-06-10
JP10292561A JP2000067577A (ja) 1998-06-10 1998-10-14 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000067577A true JP2000067577A (ja) 2000-03-03
JP2000067577A5 JP2000067577A5 (enExample) 2005-11-24

Family

ID=26488259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10292561A Pending JP2000067577A (ja) 1998-06-10 1998-10-14 同期型半導体記憶装置

Country Status (2)

Country Link
US (3) US6337832B1 (enExample)
JP (1) JP2000067577A (enExample)

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EP1298667A3 (en) * 2001-09-28 2004-01-14 Fujitsu Limited Semiconductor memory device
JP2004111041A (ja) * 2002-09-19 2004-04-08 Samsung Electronics Co Ltd Ｓｄｒ／ｄｄｒ兼用半導体メモリ装置のデータ出力回路
WO2006067852A1 (ja) * 2004-12-24 2006-06-29 Spansion Llc 同期型記憶装置、およびその制御方法
JP2006172577A (ja) * 2004-12-14 2006-06-29 Elpida Memory Inc 半導体記憶装置
WO2006080065A1 (ja) * 2005-01-27 2006-08-03 Spansion Llc 記憶装置、およびその制御方法
US7372380B2 (en) 2003-03-11 2008-05-13 Matsushita Elecetric Industrial Co., Ltd. Data transmitting/receiving device
KR100870753B1 (ko) * 2007-06-20 2008-11-26 스펜션 엘엘씨 동기형 기억 장치 및 그 제어 방법
JP2010518547A (ja) * 2007-02-16 2010-05-27 モスエイド テクノロジーズ インコーポレイテッド メモリシステムのクロックモード決定
JP2012198965A (ja) * 2011-03-22 2012-10-18 Toshiba Corp 不揮発性半導体記憶装置

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US6337832B1 (en) 2002-01-08

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