JP2001273774A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2001273774A5 JP2001273774A5 JP2000089561A JP2000089561A JP2001273774A5 JP 2001273774 A5 JP2001273774 A5 JP 2001273774A5 JP 2000089561 A JP2000089561 A JP 2000089561A JP 2000089561 A JP2000089561 A JP 2000089561A JP 2001273774 A5 JP2001273774 A5 JP 2001273774A5
- Authority
- JP
- Japan
- Prior art keywords
- block
- bit line
- input
- selection signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 16
- 239000004065 semiconductor Substances 0.000 claims 14
- 238000003491 array Methods 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 2
- 239000011159 matrix material Substances 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000089561A JP2001273774A (ja) | 2000-03-28 | 2000-03-28 | 半導体記憶装置 |
| US09/812,361 US6388937B2 (en) | 2000-03-28 | 2001-03-20 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000089561A JP2001273774A (ja) | 2000-03-28 | 2000-03-28 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001273774A JP2001273774A (ja) | 2001-10-05 |
| JP2001273774A5 true JP2001273774A5 (enExample) | 2005-06-16 |
Family
ID=18605302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000089561A Pending JP2001273774A (ja) | 2000-03-28 | 2000-03-28 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6388937B2 (enExample) |
| JP (1) | JP2001273774A (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4808838B2 (ja) * | 2000-10-26 | 2011-11-02 | 旭化成エレクトロニクス株式会社 | 半導体記憶装置 |
| JP4143287B2 (ja) * | 2001-11-08 | 2008-09-03 | エルピーダメモリ株式会社 | 半導体記憶装置とそのデータ読み出し制御方法 |
| US6903956B2 (en) * | 2002-09-27 | 2005-06-07 | Oki Electric Industry Co., Ltd. | Semiconductor memory device |
| US6947349B1 (en) | 2003-09-03 | 2005-09-20 | T-Ram, Inc. | Apparatus and method for producing an output clock pulse and output clock generator using same |
| US7464282B1 (en) | 2003-09-03 | 2008-12-09 | T-Ram Semiconductor, Inc. | Apparatus and method for producing dummy data and output clock generator using same |
| US6891774B1 (en) | 2003-09-03 | 2005-05-10 | T-Ram, Inc. | Delay line and output clock generator using same |
| US7089439B1 (en) | 2003-09-03 | 2006-08-08 | T-Ram, Inc. | Architecture and method for output clock generation on a high speed memory device |
| JP4721776B2 (ja) * | 2004-07-13 | 2011-07-13 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| JP2009176343A (ja) * | 2008-01-22 | 2009-08-06 | Liquid Design Systems:Kk | 半導体記憶装置 |
| KR101060899B1 (ko) * | 2009-12-23 | 2011-08-30 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 이의 동작 방법 |
| JP5777991B2 (ja) * | 2011-09-22 | 2015-09-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US8953395B2 (en) * | 2012-02-23 | 2015-02-10 | Apple Inc. | Memory with variable strength sense amplifier |
| US9384826B2 (en) * | 2014-12-05 | 2016-07-05 | Texas Instruments Incorporated | Circuits and methods for performance optimization of SRAM memory |
| US9824738B2 (en) * | 2016-03-11 | 2017-11-21 | Toshiba Memory Corporation | Semiconductor storage device |
| US10210915B2 (en) * | 2016-06-10 | 2019-02-19 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device including the same |
| KR102646847B1 (ko) | 2016-12-07 | 2024-03-12 | 삼성전자주식회사 | 반도체 메모리 장치, 반도체 메모리 장치의 동작 방법 및 메모리 시스템 |
| WO2020075380A1 (ja) * | 2018-10-12 | 2020-04-16 | ソニーセミコンダクタソリューションズ株式会社 | 記憶回路および撮像装置 |
| US20250259671A1 (en) * | 2024-02-08 | 2025-08-14 | Arm Limited | Increased throughput for reads in static random access memory |
| US12422992B2 (en) | 2024-02-08 | 2025-09-23 | Arm Limited | Increased throughput for writes to memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10275477A (ja) | 1997-01-29 | 1998-10-13 | Hitachi Ltd | スタティック型ram |
| JPH11162174A (ja) | 1997-11-25 | 1999-06-18 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| JP2000011681A (ja) * | 1998-06-22 | 2000-01-14 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
-
2000
- 2000-03-28 JP JP2000089561A patent/JP2001273774A/ja active Pending
-
2001
- 2001-03-20 US US09/812,361 patent/US6388937B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001273774A5 (enExample) | ||
| US6411128B2 (en) | Logical circuit for serializing and outputting a plurality of signal bits simultaneously read from a memory cell array or the like | |
| US8027203B2 (en) | Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure | |
| JP3317187B2 (ja) | 半導体記憶装置 | |
| US7958382B2 (en) | Latency signal generator and method thereof | |
| JP2007531957A (ja) | 非同期スタティックランダムアクセスメモリ | |
| JP2007287305A (ja) | 半導体メモリ素子 | |
| JP5164358B2 (ja) | マルチポートメモリ装置 | |
| JP2000260181A5 (enExample) | ||
| JP2010182367A (ja) | 半導体記憶装置 | |
| JP2007095284A (ja) | 直列入/出力インターフェイスを有するマルチポートメモリ素子 | |
| EP0521165A1 (en) | Semiconductor storing device | |
| KR100276652B1 (ko) | 반도체 메모리 장치 및 그 장치의 데이터 처리 방법 | |
| WO2002019129A3 (en) | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner | |
| JPH07182854A (ja) | 半導体記憶回路の制御方法 | |
| US6707740B2 (en) | Semiconductor memory | |
| JP2970513B2 (ja) | 半導体記憶装置およびその制御方法 | |
| US6373778B1 (en) | Burst operations in memories | |
| JP3090104B2 (ja) | 半導体メモリ装置 | |
| JP2003196985A (ja) | 半導体メモリ及び半導体メモリのビットライト又はバイトライト方法 | |
| US7317629B2 (en) | Semiconductor memory device with simplified data control signals | |
| KR100558474B1 (ko) | 반도체 메모리 장치 | |
| KR0156969B1 (ko) | 버스트 페이지 억세스 장치 | |
| JP2684368B2 (ja) | 半導体記憶装置 | |
| KR100596799B1 (ko) | 메모리 장치용 입력 데이타 분배 장치 |