JP2001273774A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JP2001273774A
JP2001273774A JP2000089561A JP2000089561A JP2001273774A JP 2001273774 A JP2001273774 A JP 2001273774A JP 2000089561 A JP2000089561 A JP 2000089561A JP 2000089561 A JP2000089561 A JP 2000089561A JP 2001273774 A JP2001273774 A JP 2001273774A
Authority
JP
Japan
Prior art keywords
block
selection signal
bit line
input
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000089561A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001273774A5 (enExample
Inventor
Yoshikazu Takeyama
山 嘉 和 竹
Takayuki Harima
磨 高 之 播
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000089561A priority Critical patent/JP2001273774A/ja
Priority to US09/812,361 priority patent/US6388937B2/en
Publication of JP2001273774A publication Critical patent/JP2001273774A/ja
Publication of JP2001273774A5 publication Critical patent/JP2001273774A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP2000089561A 2000-03-28 2000-03-28 半導体記憶装置 Pending JP2001273774A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000089561A JP2001273774A (ja) 2000-03-28 2000-03-28 半導体記憶装置
US09/812,361 US6388937B2 (en) 2000-03-28 2001-03-20 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000089561A JP2001273774A (ja) 2000-03-28 2000-03-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2001273774A true JP2001273774A (ja) 2001-10-05
JP2001273774A5 JP2001273774A5 (enExample) 2005-06-16

Family

ID=18605302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000089561A Pending JP2001273774A (ja) 2000-03-28 2000-03-28 半導体記憶装置

Country Status (2)

Country Link
US (1) US6388937B2 (enExample)
JP (1) JP2001273774A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002133853A (ja) * 2000-10-26 2002-05-10 Asahi Kasei Microsystems Kk 半導体記憶装置
JP2017224377A (ja) * 2016-06-10 2017-12-21 株式会社半導体エネルギー研究所 メモリ装置、およびそれを有する半導体装置

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4143287B2 (ja) * 2001-11-08 2008-09-03 エルピーダメモリ株式会社 半導体記憶装置とそのデータ読み出し制御方法
US6903956B2 (en) * 2002-09-27 2005-06-07 Oki Electric Industry Co., Ltd. Semiconductor memory device
US6947349B1 (en) 2003-09-03 2005-09-20 T-Ram, Inc. Apparatus and method for producing an output clock pulse and output clock generator using same
US7464282B1 (en) 2003-09-03 2008-12-09 T-Ram Semiconductor, Inc. Apparatus and method for producing dummy data and output clock generator using same
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
US7089439B1 (en) 2003-09-03 2006-08-08 T-Ram, Inc. Architecture and method for output clock generation on a high speed memory device
JP4721776B2 (ja) * 2004-07-13 2011-07-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2009176343A (ja) * 2008-01-22 2009-08-06 Liquid Design Systems:Kk 半導体記憶装置
KR101060899B1 (ko) * 2009-12-23 2011-08-30 주식회사 하이닉스반도체 반도체 메모리 장치 및 이의 동작 방법
JP5777991B2 (ja) * 2011-09-22 2015-09-16 ルネサスエレクトロニクス株式会社 半導体装置
US8953395B2 (en) * 2012-02-23 2015-02-10 Apple Inc. Memory with variable strength sense amplifier
US9384826B2 (en) * 2014-12-05 2016-07-05 Texas Instruments Incorporated Circuits and methods for performance optimization of SRAM memory
US9824738B2 (en) * 2016-03-11 2017-11-21 Toshiba Memory Corporation Semiconductor storage device
KR102646847B1 (ko) 2016-12-07 2024-03-12 삼성전자주식회사 반도체 메모리 장치, 반도체 메모리 장치의 동작 방법 및 메모리 시스템
WO2020075380A1 (ja) * 2018-10-12 2020-04-16 ソニーセミコンダクタソリューションズ株式会社 記憶回路および撮像装置
US20250259671A1 (en) * 2024-02-08 2025-08-14 Arm Limited Increased throughput for reads in static random access memory
US12422992B2 (en) 2024-02-08 2025-09-23 Arm Limited Increased throughput for writes to memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10275477A (ja) 1997-01-29 1998-10-13 Hitachi Ltd スタティック型ｒａｍ
JPH11162174A (ja) 1997-11-25 1999-06-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000011681A (ja) * 1998-06-22 2000-01-14 Mitsubishi Electric Corp 同期型半導体記憶装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002133853A (ja) * 2000-10-26 2002-05-10 Asahi Kasei Microsystems Kk 半導体記憶装置
JP2017224377A (ja) * 2016-06-10 2017-12-21 株式会社半導体エネルギー研究所 メモリ装置、およびそれを有する半導体装置

Also Published As

Publication number Publication date
US6388937B2 (en) 2002-05-14
US20010043482A1 (en) 2001-11-22

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