JP2004523056A5 - - Google Patents

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Publication number
JP2004523056A5
JP2004523056A5 JP2002586351A JP2002586351A JP2004523056A5 JP 2004523056 A5 JP2004523056 A5 JP 2004523056A5 JP 2002586351 A JP2002586351 A JP 2002586351A JP 2002586351 A JP2002586351 A JP 2002586351A JP 2004523056 A5 JP2004523056 A5 JP 2004523056A5
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JP
Japan
Prior art keywords
output
data
data bits
signal
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002586351A
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English (en)
Japanese (ja)
Other versions
JP4080892B2 (ja
JP2004523056A (ja
Filing date
Publication date
Priority claimed from US09/808,506 external-priority patent/US6556494B2/en
Application filed filed Critical
Publication of JP2004523056A publication Critical patent/JP2004523056A/ja
Publication of JP2004523056A5 publication Critical patent/JP2004523056A5/ja
Application granted granted Critical
Publication of JP4080892B2 publication Critical patent/JP4080892B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2002586351A 2001-03-14 2002-03-08 マルチビットプリフェッチ出力データパス Expired - Fee Related JP4080892B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/808,506 US6556494B2 (en) 2001-03-14 2001-03-14 High frequency range four bit prefetch output data path
PCT/US2002/007668 WO2002089141A1 (en) 2001-03-14 2002-03-08 Multiple bit prefetch output data path

Publications (3)

Publication Number Publication Date
JP2004523056A JP2004523056A (ja) 2004-07-29
JP2004523056A5 true JP2004523056A5 (enExample) 2005-11-17
JP4080892B2 JP4080892B2 (ja) 2008-04-23

Family

ID=25198971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002586351A Expired - Fee Related JP4080892B2 (ja) 2001-03-14 2002-03-08 マルチビットプリフェッチ出力データパス

Country Status (8)

Country Link
US (2) US6556494B2 (enExample)
EP (1) EP1377982B1 (enExample)
JP (1) JP4080892B2 (enExample)
KR (1) KR100568646B1 (enExample)
CN (1) CN100565698C (enExample)
AT (1) ATE341082T1 (enExample)
DE (1) DE60214992T2 (enExample)
WO (1) WO2002089141A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4812976B2 (ja) * 2001-07-30 2011-11-09 エルピーダメモリ株式会社 レジスタ、メモリモジュール及びメモリシステム
JP2003044349A (ja) * 2001-07-30 2003-02-14 Elpida Memory Inc レジスタ及び信号生成方法
US7549011B2 (en) * 2001-08-30 2009-06-16 Micron Technology, Inc. Bit inversion in memory devices
US6785168B2 (en) * 2002-12-27 2004-08-31 Hynix Semiconductor Inc. Semiconductor memory device having advanced prefetch block
KR100518564B1 (ko) * 2003-04-03 2005-10-04 삼성전자주식회사 이중 데이터율 동기식 메모리장치의 출력 멀티플렉싱 회로및 방법
KR100564596B1 (ko) * 2003-12-18 2006-03-28 삼성전자주식회사 멀티비트 데이터의 지연 시간 보상이 가능한 반도체메모리 장치
JP2005182939A (ja) * 2003-12-22 2005-07-07 Toshiba Corp 半導体記憶装置
US7016235B2 (en) * 2004-03-03 2006-03-21 Promos Technologies Pte. Ltd. Data sorting in memories
US7054215B2 (en) * 2004-04-02 2006-05-30 Promos Technologies Pte. Ltd. Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stage
KR100562645B1 (ko) * 2004-10-29 2006-03-20 주식회사 하이닉스반도체 반도체 기억 소자
US7230858B2 (en) * 2005-06-28 2007-06-12 Infineon Technologies Ag Dual frequency first-in-first-out structure
US7349289B2 (en) * 2005-07-08 2008-03-25 Promos Technologies Inc. Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM
US7358872B2 (en) * 2005-09-01 2008-04-15 Micron Technology, Inc. Method and apparatus for converting parallel data to serial data in high speed applications
US7567465B2 (en) * 2007-08-30 2009-07-28 Micron Technology, Inc. Power saving sensing scheme for solid state memory
JP2011058847A (ja) * 2009-09-07 2011-03-24 Renesas Electronics Corp 半導体集積回路装置
KR20110088947A (ko) * 2010-01-29 2011-08-04 주식회사 하이닉스반도체 반도체 메모리의 데이터 출력 회로
TWI459401B (zh) * 2011-03-09 2014-11-01 Etron Technology Inc 應用於一記憶體電路內複數個記憶區塊的栓鎖系統
TWI490698B (zh) * 2013-05-10 2015-07-01 Integrated Circuit Solution Inc 高速資料傳輸架構
CN103413516B (zh) * 2013-08-22 2016-03-30 京东方科技集团股份有限公司 数据传输装置、数据传输方法及显示装置
US9412294B2 (en) 2013-08-22 2016-08-09 Boe Technology Group Co., Ltd. Data transmission device, data transmission method and display device
EP3714370B1 (en) * 2017-11-24 2022-01-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Data bus with multi-input pipeline
CN111208867B (zh) * 2019-12-27 2021-08-24 芯创智（北京）微电子有限公司 一种基于ddr读数据整数时钟周期的同步电路及同步方法
CN116705132B (zh) * 2022-02-24 2024-05-14 长鑫存储技术有限公司 数据传输电路、数据传输方法和存储器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10255459A (ja) 1997-03-10 1998-09-25 Mitsubishi Electric Corp ラインメモリ
JPH11176158A (ja) * 1997-12-10 1999-07-02 Fujitsu Ltd ラッチ回路、データ出力回路及びこれを有する半導体装置
TW430815B (en) * 1998-06-03 2001-04-21 Fujitsu Ltd Semiconductor integrated circuit memory and, bus control method
JP2000076853A (ja) 1998-06-17 2000-03-14 Mitsubishi Electric Corp 同期型半導体記憶装置

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