JP2000012864A - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法

Info

Publication number
JP2000012864A
JP2000012864A JP10174482A JP17448298A JP2000012864A JP 2000012864 A JP2000012864 A JP 2000012864A JP 10174482 A JP10174482 A JP 10174482A JP 17448298 A JP17448298 A JP 17448298A JP 2000012864 A JP2000012864 A JP 2000012864A
Authority
JP
Japan
Prior art keywords
crystal silicon
single crystal
substrate
thin film
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10174482A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000012864A5 (enExample
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP10174482A priority Critical patent/JP2000012864A/ja
Priority to US09/337,333 priority patent/US6380046B1/en
Publication of JP2000012864A publication Critical patent/JP2000012864A/ja
Priority to US10/124,344 priority patent/US20020109144A1/en
Priority to US10/759,297 priority patent/US7199024B2/en
Publication of JP2000012864A5 publication Critical patent/JP2000012864A5/ja
Priority to US11/716,583 priority patent/US8187926B2/en
Priority to US11/978,605 priority patent/US7816736B2/en
Priority to US11/978,609 priority patent/US20080061301A1/en
Priority to US11/978,612 priority patent/US8053837B2/en
Priority to US11/978,586 priority patent/US7834398B2/en
Priority to US11/978,610 priority patent/US8288248B2/en
Priority to US12/216,754 priority patent/US7790570B2/en
Priority to US12/216,756 priority patent/US8314010B2/en
Priority to US12/216,755 priority patent/US8241997B2/en
Priority to US13/680,448 priority patent/US8575741B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
JP10174482A 1998-06-22 1998-06-22 半導体装置の作製方法 Pending JP2000012864A (ja)

Priority Applications (14)

Application Number Priority Date Filing Date Title
JP10174482A JP2000012864A (ja) 1998-06-22 1998-06-22 半導体装置の作製方法
US09/337,333 US6380046B1 (en) 1998-06-22 1999-06-21 Method of manufacturing a semiconductor device
US10/124,344 US20020109144A1 (en) 1998-06-22 2002-04-18 Method of manufacturing a semiconductor device
US10/759,297 US7199024B2 (en) 1998-06-22 2004-01-20 Method of manufacturing a semiconductor device
US11/716,583 US8187926B2 (en) 1998-06-22 2007-03-12 Method of manufacturing a semiconductor device
US11/978,610 US8288248B2 (en) 1998-06-22 2007-10-30 Method of manufacturing semiconductor device having island-like single crystal semiconductor layer
US11/978,586 US7834398B2 (en) 1998-06-22 2007-10-30 Method of manufacturing a semiconductor device
US11/978,605 US7816736B2 (en) 1998-06-22 2007-10-30 Method of manufacturing a semiconductor device
US11/978,609 US20080061301A1 (en) 1998-06-22 2007-10-30 Method of manufacturing a semiconductor device
US11/978,612 US8053837B2 (en) 1998-06-22 2007-10-30 Semiconductor device
US12/216,754 US7790570B2 (en) 1998-06-22 2008-07-10 Method of manufacturing a semiconductor device
US12/216,756 US8314010B2 (en) 1998-06-22 2008-07-10 Method of manufacturing a semiconductor device including thermal oxidation to form an insulating film
US12/216,755 US8241997B2 (en) 1998-06-22 2008-07-10 Method of manufacturing a semiconductor device having a gate electrode formed over a silicon oxide insulating layer
US13/680,448 US8575741B2 (en) 1998-06-22 2012-11-19 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10174482A JP2000012864A (ja) 1998-06-22 1998-06-22 半導体装置の作製方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007024310A Division JP2007158371A (ja) 2007-02-02 2007-02-02 半導体装置の作製方法

Publications (2)

Publication Number Publication Date
JP2000012864A true JP2000012864A (ja) 2000-01-14
JP2000012864A5 JP2000012864A5 (enExample) 2005-10-13

Family

ID=15979263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10174482A Pending JP2000012864A (ja) 1998-06-22 1998-06-22 半導体装置の作製方法

Country Status (2)

Country Link
US (13) US6380046B1 (enExample)
JP (1) JP2000012864A (enExample)

Cited By (48)

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US6846718B1 (en) * 1999-10-14 2005-01-25 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer and SOI wafer
JP2005026472A (ja) * 2003-07-02 2005-01-27 Sharp Corp 半導体装置の製造方法
EP1975998A2 (en) 2007-03-26 2008-10-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a plurality of island-shaped SOI structures
EP1978554A2 (en) 2007-04-06 2008-10-08 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate comprising implantation and separation steps
EP1978553A2 (en) 2007-04-03 2008-10-08 Semiconductor Energy Laboratory Co., Ltd. SOI substrate, method for manufacturing the same, and semiconductor device
EP1993130A2 (en) 2007-05-17 2008-11-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP2009038358A (ja) * 2007-07-09 2009-02-19 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2009065015A (ja) * 2007-09-07 2009-03-26 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
EP2105957A2 (en) 2008-03-26 2009-09-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate and method for manufacturing semiconductor device
JP2009246389A (ja) * 2009-07-23 2009-10-22 Semiconductor Energy Lab Co Ltd 半導体装置
JP2009260369A (ja) * 2009-07-23 2009-11-05 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2009283974A (ja) * 2009-08-20 2009-12-03 Semiconductor Energy Lab Co Ltd 半導体装置
US7638805B2 (en) 1998-09-04 2009-12-29 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device
JP2010016391A (ja) * 2009-08-20 2010-01-21 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7709337B2 (en) 2007-04-20 2010-05-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and semiconductor device
US7755113B2 (en) 2007-03-16 2010-07-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device
US7776722B2 (en) 2007-05-18 2010-08-17 Semiconductor Energy Laboratory Co., Ltd. Manufacturing methods of semiconductor substrate, thin film transistor and semiconductor device
US7790570B2 (en) 1998-06-22 2010-09-07 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7795114B2 (en) 2007-08-10 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing methods of SOI substrate and semiconductor device
US7799658B2 (en) 2007-10-10 2010-09-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US7807500B2 (en) 1998-07-29 2010-10-05 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer
US7816234B2 (en) 2007-11-05 2010-10-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7829431B2 (en) 2007-07-13 2010-11-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a SOI with plurality of single crystal substrates
US7829396B2 (en) 2007-08-24 2010-11-09 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device and manufacturing apparatus of the same
US7846817B2 (en) 2007-03-26 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7851318B2 (en) 2007-11-01 2010-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device
US7858495B2 (en) 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US7943487B2 (en) 2008-09-29 2011-05-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7981766B2 (en) 2007-08-17 2011-07-19 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method and manufacturing apparatus of semiconductor
US7989305B2 (en) 2007-10-10 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate using cluster ion
US20110223724A1 (en) * 2000-09-28 2011-09-15 Oki Semiconductor Co., Ltd. Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same
US8021958B2 (en) 2008-03-26 2011-09-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
US8043938B2 (en) 2009-05-14 2011-10-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and SOI substrate
US8048728B2 (en) 2007-04-13 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Display device, method for manufacturing display device, and SOI substrate
US8101466B2 (en) 2007-03-26 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and method for manufacturing SOI substrate
US8110478B2 (en) 2007-10-23 2012-02-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate, display panel, and display device
US8163628B2 (en) 2007-11-01 2012-04-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US8211780B2 (en) 2007-12-03 2012-07-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2012164814A (ja) * 2011-02-07 2012-08-30 Sumco Corp エピタキシャルウェーハの製造方法
US8283238B2 (en) 2007-06-28 2012-10-09 Semiconductor Energy Laboratory Co., Ltd. Layer transfer process for semiconductor device
US8313989B2 (en) 2008-10-22 2012-11-20 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and method for manufacturing the same
US8324086B2 (en) 2008-01-16 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor substrate by laser irradiation
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
US8530332B2 (en) 2008-03-26 2013-09-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and semiconductor device
JP2014123129A (ja) * 2007-05-18 2014-07-03 Semiconductor Energy Lab Co Ltd 発光装置
US8772128B2 (en) 2007-10-10 2014-07-08 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
US9633892B2 (en) 2008-03-26 2017-04-25 Semiconductor Energy Laboratory Co., Ltd Method for manufacturing SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced and method for manufacturing semiconductor device

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JP3295346B2 (ja) * 1997-07-14 2002-06-24 株式会社半導体エネルギー研究所 結晶性珪素膜の作製方法及びそれを用いた薄膜トランジスタ
JP3830623B2 (ja) * 1997-07-14 2006-10-04 株式会社半導体エネルギー研究所 結晶性半導体膜の作製方法
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US6559036B1 (en) * 1998-08-07 2003-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
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JP4493779B2 (ja) 2000-01-31 2010-06-30 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
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US20070020330A1 (en) 2004-11-24 2007-01-25 Medpointe Healthcare Inc. Compositions comprising azelastine and methods of use thereof
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US20110143506A1 (en) * 2009-12-10 2011-06-16 Sang-Yun Lee Method for fabricating a semiconductor memory device
US8367524B2 (en) * 2005-03-29 2013-02-05 Sang-Yun Lee Three-dimensional integrated circuit structure
JP2007180402A (ja) * 2005-12-28 2007-07-12 Toshiba Corp 半導体装置及びその製造方法
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JP5289805B2 (ja) * 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 半導体装置製造用基板の作製方法
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US7199024B2 (en) 2007-04-03
US7834398B2 (en) 2010-11-16
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US20130143387A1 (en) 2013-06-06
US20080061301A1 (en) 2008-03-13
US7816736B2 (en) 2010-10-19
US8187926B2 (en) 2012-05-29
US20040147095A1 (en) 2004-07-29
US20080286942A1 (en) 2008-11-20
US8053837B2 (en) 2011-11-08
US20070173000A1 (en) 2007-07-26
US6380046B1 (en) 2002-04-30
US8575741B2 (en) 2013-11-05
US8241997B2 (en) 2012-08-14
US20080213953A1 (en) 2008-09-04
US8314010B2 (en) 2012-11-20
US20080286956A1 (en) 2008-11-20
US7790570B2 (en) 2010-09-07
US20080067529A1 (en) 2008-03-20
US8288248B2 (en) 2012-10-16
US20080083953A1 (en) 2008-04-10
US20080067597A1 (en) 2008-03-20

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