JP5688203B2 - 半導体基板の作製方法 - Google Patents
半導体基板の作製方法 Download PDFInfo
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- JP5688203B2 JP5688203B2 JP2008258236A JP2008258236A JP5688203B2 JP 5688203 B2 JP5688203 B2 JP 5688203B2 JP 2008258236 A JP2008258236 A JP 2008258236A JP 2008258236 A JP2008258236 A JP 2008258236A JP 5688203 B2 JP5688203 B2 JP 5688203B2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-O azanium;hydrofluoride Chemical compound [NH4+].F LDDQLRUQCUTJBB-UHFFFAOYSA-O 0.000 description 1
- BHVMAFDNFMTYLQ-UHFFFAOYSA-N azanylidyne(azanylidynegermyloxy)germane Chemical compound N#[Ge]O[Ge]#N BHVMAFDNFMTYLQ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052800 carbon group element Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- BIXHRBFZLLFBFL-UHFFFAOYSA-N germanium nitride Chemical compound N#[Ge]N([Ge]#N)[Ge]#N BIXHRBFZLLFBFL-UHFFFAOYSA-N 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- SYHGEUNFJIGTRX-UHFFFAOYSA-N methylenedioxypyrovalerone Chemical compound C=1C=C2OCOC2=CC=1C(=O)C(CCC)N1CCCC1 SYHGEUNFJIGTRX-UHFFFAOYSA-N 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 150000002831 nitrogen free-radicals Chemical class 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- QQQSFSZALRVCSZ-UHFFFAOYSA-N triethoxysilane Chemical compound CCO[SiH](OCC)OCC QQQSFSZALRVCSZ-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Description
図1は、半導体基板の構成例を示す斜視図である。半導体基板10は、支持基板100に単結晶半導体層116が貼り付けられている。単結晶半導体層116はバッファ層101を介して支持基板100に設けられており、半導体基板10はいわゆるSOI構造の基板であり、絶縁層上に単結晶半導体層が形成されている基板である。
・原子間力顕微鏡(AFM):走査型プローブ顕微鏡SPI3800N/SPA500(セイコーインスツルメンツ社製)
・測定モード:ダイナミックフォースモード(DFMモード)
・カンチレバー:SI−DF40(シリコン製、バネ定数40N/m以上45N/m以下、共振周波数250kHz以上390kHz以下、探針の先端R≦10nm)
・走査速度:1.0Hz
・測定点数:256×256点
単結晶半導体層115が分離された単結晶半導体基板117は再生処理して、単結晶半導体基板110として再利用することができる。本実施形態では、再生処理方法について説明する。
図16〜図18を用いて、本実施形態では、半導体基板10を用いた半導体装置の作製方法の一例として、トランジスタを作製する方法を説明する。複数のトランジスタを組み合わせることで、各種の半導体装置が形成される。以下、図16〜図18の断面図を用いて、トランジスタの作製方法を説明する。なお、本実施形態では、nチャネル型のトランジスタとpチャネル型のトランジスタを同時に作製する方法を説明する。
本実施の形態では、本実施の形態では、半導体基板10を用いた半導体装置の作製方法の一例として、上記実施の形態3とは異なるトランジスタを作製する方法について説明する。以下、図38〜図40の断面図を用いて、トランジスタの作製方法を説明する。なお、本実施形態では、nチャネル型のトランジスタとpチャネル型のトランジスタを同時に作製する方法を説明する。
図19を用いて、本実施形態では、半導体基板10を用いた半導体装置の作製方法の一例としてトランジスタを作製する方法を説明する。複数の薄膜トランジスタを組み合わせることで、各種の半導体装置が形成される。なお、本実施形態では、nチャネル型のトランジスタとpチャネル型のトランジスタを同時に作製する方法を説明する。
実施形態3乃至5では、半導体装置の作製方法の一例として、トランジスタの作製方法を説明したが、半導体膜付き基板に、トランジスタと共に容量、抵抗など各種の半導体素子を形成することで、高付加価値の半導体装置を作製することができる。本実施形態では、図面を参照しながら半導体装置の具体的な態様を説明する。
・厚さ 50nm
・ガスの種類(流量)
SiH4(4sccm)
N2O (800sccm)
・基板温度 400℃
・圧力 40Pa
・RF周波数 27MHz
・RFパワー 50W
・電極間距離 15mm
・電極面積 615.75cm2
・厚さ 50nm
・ガスの種類(流量)
SiH4(10sccm)
NH3(100sccm)
N2O (20sccm)
H2(400sccm)
・基板温度 300℃
・圧力 40Pa
・RF周波数 27MHz
・RFパワー 50W
・電極間距離 30mm
・電極面積 615.75cm2
・RFパワー 150W
・加速電圧 40kV
・ドーズ量 1.75×1016ions/cm−2
・厚さ 50nm
・ガスの種類(流量)
TEOS(15sccm)
O2 (750sccm)
・基板温度 300℃
・圧力 100Pa
・RF周波数 27MHz
・RFパワー 300W
・電極間距離 14mm
・電極面積 615.75cm2
<レーザの仕様>
XeClエキシマレーザ
波長308nm
パルス幅25nsec
繰り返し周波数30Hz
・347mJ/cm2
・387mJ/cm2
・431mJ/cm2
・477mJ/cm2
・525mJ/cm2
・572mJ/cm2
・619mJ/cm2
・664mJ/cm2
・706mJ/cm2
・743mJ/cm2
<レーザの仕様>
XeClエキシマレーザ
波長308nm
パルス幅25nsec
繰り返し周波数30Hz
・レーザビーム照射無し、大気雰囲気(条件1)
・449.0mJ/cm2、窒素雰囲気(条件2)
・543.1mJ/cm2、窒素雰囲気(条件3)
・543.1mJ/cm2、大気雰囲気(条件4)
・637.3mJ/cm2、窒素雰囲気(条件5)
上記のような水素プラズマ中には、H+イオン、H2 +イオン、H3 +イオンといった水素イオン種が存在する。ここで、各水素イオン種の反応過程(生成過程、消滅過程)について、以下に反応式を列挙する。
e+H→e+H++e ・・・・・ (1)
e+H2→e+H2 ++e ・・・・・ (2)
e+H2→e+(H2)*→e+H+H ・・・・・ (3)
e+H2 +→e+(H2 +)*→e+H++H ・・・・・ (4)
H2 ++H2→H3 ++H ・・・・・ (5)
H2 ++H2→H++H+H2 ・・・・・ (6)
e+H3 +→e+H++H+H ・・・・・ (7)
e+H3 +→H2+H ・・・・・ (8)
e+H3 +→H+H+H ・・・・・ (9)
上記のように、H3 +イオンは、主として反応式(5)により表される反応過程により生成される。一方で、反応式(5)と競合する反応として、反応式(6)により表される反応過程が存在する。H3 +イオンが増加するためには、少なくとも、反応式(5)の反応が、反応式(6)の反応より多く起こる必要がある(なお、H3 +イオンが減少する反応としては他にも(7)、(8)、(9)が存在するため、(5)の反応が(6)の反応より多いからといって、必ずしもH3 +イオンが増加するとは限らない。)。反対に、反応式(5)の反応が、反応式(6)の反応より少ない場合には、プラズマ中におけるH3 +イオンの割合は減少する。
ここで、水素イオン種の割合(特にH3 +イオンの割合)が異なる例を示す。図42は、100%水素ガス(イオン源の圧力:4.7×10−2Pa)から生成されるイオンの質量分析結果を示すグラフである。なお、上記質量分析は、イオン源から引き出されたイオンを測定することにより行った。横軸はイオンの質量である。スペクトル中、質量1、質量2、質量3のピークは、それぞれ、H+イオン、H2 +イオン、H3 +イオンに対応する。縦軸は、スペクトルの強度であり、イオンの数に対応する。図42では、質量が異なるイオンの数量を、質量3のイオンを100とした場合の相対比で表している。図42から、上記イオン源により生成されるイオンの割合は、H+イオン:H2 +イオン:H3 +イオン=1:1:8程度となることが分かる。なお、このような割合のイオンは、プラズマを生成するプラズマソース部(イオン源)と、当該プラズマからイオンビームを引き出すための引出電極などから構成されるイオンドーピング装置によっても得ることが出来る。
図42のような複数種のイオンを含むプラズマを生成し、生成された複数種のイオンを質量分離しないで単結晶半導体基板に照射する場合、単結晶半導体基板の表面には、H+イオン、H2 +イオン、H3 +イオンの各イオンが照射される。イオンの照射からイオン導入領域形成にかけてのメカニズムを再現するために、以下の5種類のモデルを考える。
1.照射される水素イオン種がH+イオンで、照射後もH+イオン(或いはH)である場合。
2.照射される水素イオン種がH2 +イオンで、照射後もH2 +イオン(或いはH2)のままである場合。
3.照射される水素イオン種がH2 +イオンで、照射後に2個のH(或いはH+イオン)に分裂する場合。
4.照射される水素イオン種がH3 +イオンで、照射後もH3 +イオン(或いはH3)のままである場合。
5.照射される水素イオン種がH3 +イオンで、照射後に3個のH(或いはH+イオン)に分裂する場合。
上記のモデルを基にして、水素イオン種をシリコン基板に照射する場合のシミュレーションを行った。シミュレーション用のソフトウェアとしては、SRIM(the Stopping and Range of Ions in Matter:モンテカルロ法によるイオン導入過程のシミュレーションソフトウェア)、TRIM((the Transport of Ions in Matter)の改良版)を用いている。なお、計算の関係上、モデル2ではH2 +イオンを質量2倍のH+イオンに置き換えて計算した。また、モデル4ではH3 +イオンを質量3倍のH+イオンに置き換えて計算した。さらに、モデル3ではH2 +イオンを運動エネルギー1/2のH+イオンに置き換え、モデル5ではH3 +イオンを運動エネルギー1/3のH+イオンに置き換えて計算を行った。
[フィッティング関数]
=X/V×[モデル1のデータ]+Y/V×[モデル5のデータ]
・モデル3に示される照射過程により導入される水素は、モデル5の照射過程と比較して僅かであるため、除外して考えても大きな影響はない(SIMSデータにおいても、ピークが現れていない)。
・モデル5とピーク位置の近いモデル3は、モデル5において生じるチャネリング(結晶の格子構造に起因する元素の移動)により隠れてしまう可能性が高い。すなわち、モデル3のフィッティングパラメータを見積もるのは困難である。これは、本シミュレーションが非晶質シリコンを前提としており、結晶性に起因する影響を考慮していないことによるものである。
図42に示すようなH3 +イオンの割合を高めた水素イオン種を単結晶半導体基板に照射することで、H3 +イオンに起因する複数のメリットを享受することができる。例えば、H3 +イオンはH+イオンやHなどに分離して基板内に導入されるため、主にH+イオンやH2 +イオンを照射する場合と比較して、イオンの導入効率を向上させることができる。これにより、SOI基板の生産性向上を図ることができる。また、同様に、H3 +イオンが分離した後のH+イオンやHの運動エネルギーは小さくなる傾向にあるから、薄い半導体層の製造に向いている。
20 半導体基板
100 支持基板
101 バッファ層
110 単結晶半導体基板
111 バルク単結晶半導体基板
112 絶縁層
113 損傷層
114 接合層
115 単結晶半導体層
116 単結晶半導体層
117 単結晶半導体基板
121 イオンビーム
122 レーザビーム
123 矢印
200 マイクロプロセッサ
201 演算回路
202 演算回路制御部
203 命令解析部
204 割り込み制御部
205 タイミング制御部
206 レジスタ
207 レジスタ制御部
208 バスインターフェース
209 読み出し専用メモリ
210 メモリインターフェース
211 半導体装置
212 アナログ回路部
213 デジタル回路部
214 共振回路
215 整流回路
216 定電圧回路
217 リセット回路
218 発振回路
219 復調回路
220 変調回路
221 RFインターフェース
222 制御レジスタ
223 クロックコントローラ
224 インターフェース
225 中央処理ユニット
226 ランダムアクセスメモリ
227 読み出し専用メモリ
228 アンテナ
229 容量部
230 電源管理回路
300 レーザビーム
301 レーザ発振器
302 被処理物
303 ステージ
304 コントローラ
306 チャンバー
307 矢印
308 窓
309 気体供給口
310 排気口
311 光学系
319 被処理物
320 レーザビーム
321 レーザ発振器
323 ステージ
324 チャンバー
325 矢印
326 窓
327 窓
328 窓
329 気体供給口
330 排気口
332 ハーフミラー
333 レンズ
334 フォトディテクタ
350 プローブ光
350D プローブ光
351 レーザ発振器
352 ミラー
353 光ファイバー
354 コリメータ
355 フォトディテクタ
356 オシロスコープ
390 気体加熱装置
393 ステージ
398 気体貯蔵装置
399 気体供給装置
400 基板
401 選択用トランジスタ
402 表示制御用トランジスタ
403 半導体層
404 半導体層
405 走査線
406 信号線
407 電流供給線
408 画素電極
411 電極
412 ゲート電極
413 電極
427 層間絶縁膜
428 隔壁層
429 EL層
430 対向電極
431 対向基板
432 樹脂層
451 チャネル形成領域
452 不純物領域
510 基板
511 半導体層
512 チャネル形成領域
513 不純物領域
522 走査線
523 信号線
524 画素電極
525 トランジスタ
527 層間絶縁膜
528 電極
529 柱状スペーサ
530 配向膜
532 対向基板
533 対向電極
534 配向膜
535 液晶層
603 半導体膜
604 半導体膜
606 ゲート絶縁膜
607 電極
608 高濃度不純物領域
609 低濃度不純物領域
610 チャネル形成領域
611 チャネル形成領域
612 サイドウォール
614 高濃度不純物領域
617 pチャネル型トランジスタ
618 nチャネル型トランジスタ
619 絶縁膜
620 絶縁膜
621 導電膜
622 導電膜
651 半導体膜
652 半導体膜
653 ゲート絶縁層
654 導電層
655 導電層
656 レジストマスク
657 レジストマスク
658 導電層
659 導電層
660 導電層
661 導電層
662 導電層
663 導電層
665 ゲート電極
666 ゲート電極
668 不純物元素
669 不純物領域
670 不純物領域
671 レジストマスク
672 レジストマスク
673 不純物元素
675 不純物領域
676 不純物領域
677 チャネル形成領域
679 レジストマスク
680 不純物元素
681 不純物領域
682 不純物領域
683 チャネル形成領域
684 絶縁層
685 絶縁層
686 導電層
803 素子分離絶縁層
804 保護層
805 素子領域
806 素子領域
807 ゲート絶縁層
808 ゲート電極層
809 ゲート電極層
810 絶縁膜
821 チャネル形成領域
826 チャネル形成領域
827 層間絶縁層
828 絶縁層
831 pチャネル型電界効果トランジスタ
832 nチャネル型電界効果トランジスタ
901 携帯電話機
902 表示部
903 操作スイッチ
911 デジタルプレーヤー
912 表示部
913 操作部
914 イヤホン
921 電子ブック
922 表示部
923 操作スイッチ
1000 スマートフォン携帯電話
1001 筐体
1002 筐体
1101 表示部
1102 スピーカー
1103 マイクロフォン
1104 操作キー
1105 ポインティングデバイス
1106 表面カメラ用レンズ
1107 外部接続端子
1108 イヤホン端子
112a 絶縁膜
112b 絶縁膜
1201 キーボード
1202 外部メモリスロット
1203 裏面カメラ用レンズ
1204 ライト
3801 領域
3802 領域
3803 液相領域
3804 固相領域
807a、807b ゲート絶縁層
808a、808b ゲート電極層
815a、815b 不純物領域
816a、816b 側壁絶縁層
817a、817b 側壁絶縁層
819a、819b 不純物領域
820a、820b 不純物領域
822a、822b、823a、823b シリサイド
824a、824b 不純物領域
840a、840b、840c、840d 配線層
841a、841b、841c 配線層
842a 配線層
842b 配線層
842c 配線層
2600 c−Si基板
2600D c−Si基板
2601 酸化窒化シリコン膜
2602 窒化酸化シリコン膜
2603 イオン添加層
2604 酸化シリコン膜
2605 ガラス基板
2606 シリコン層
2610 レーザビーム
2611 シリコン層
2612 シリコン層
2608a SOI基板
2608b SOI基板
Claims (5)
- 単結晶半導体基板から分離される単結晶半導体層、及び前記単結晶半導体層が固定される支持基板を有する半導体基板の作製方法であって、
水素ガスを励起して、H + 、H 2 + 、H 3 + を有するプラズマを生成し、
前記プラズマに含まれるイオンを加速して、前記単結晶半導体基板の一方の面から前記イオンを添加して、前記単結晶半導体基板の一方の面から所定の深さの領域に損傷層を形成し、
前記単結晶半導体基板の一方の面または前記支持基板の一方の面上にバッファ層を形成し、
前記単結晶半導体基板と前記支持基板とを前記バッファ層を介して密着させることで、前記単結晶半導体基板と前記支持基板とを貼り合わせ、
前記単結晶半導体基板を加熱することによって、前記損傷層を劈開面として前記単結晶半導体基板を前記支持基板から分離することにより、前記単結晶半導体基板から分離された前記単結晶半導体層が固定された支持基板を形成し、
前記単結晶半導体層を有する側より前記単結晶半導体層にレーザビームを照射し、前記単結晶半導体層の前記レーザビームが照射されている領域の表面から深さ方向の一部の領域を溶融することで、前記単結晶半導体層を再結晶化させ、
前記バッファ層は、第1の絶縁層と、第2の絶縁層と、酸化シリコン層とを有し、
前記第1の絶縁層は、酸化窒化シリコン層であり、
前記第2の絶縁層は、窒化シリコン層または窒化酸化シリコン層であり、
前記第2の絶縁層は、前記第1の絶縁層と前記酸化シリコン層との間に設けられ、
前記酸化シリコン層は、前記支持基板に接し、
前記損傷層に添加するイオンは、H 3 + を80%以上含むことを特徴とする半導体基板の作製方法。 - 単結晶半導体基板から分離される単結晶半導体層、及び前記単結晶半導体層が固定される支持基板を有する半導体基板の作製方法であって、
水素ガスを励起して、H + 、H 2 + 、H 3 + を有するプラズマを生成し、
前記プラズマに含まれるイオンを加速して、前記単結晶半導体基板の一方の面から前記イオンを添加して、前記単結晶半導体基板の一方の面から所定の深さの領域に損傷層を形成し、
前記単結晶半導体基板の一方の面または前記支持基板の一方の面上にバッファ層を形成し、
前記単結晶半導体基板と前記支持基板とを前記バッファ層を介して密着させることで、前記単結晶半導体基板と前記支持基板とを貼り合わせ、
前記単結晶半導体基板を加熱することによって、前記損傷層を劈開面として前記単結晶半導体基板を前記支持基板から分離することにより、前記単結晶半導体基板から分離された前記単結晶半導体層が固定された支持基板を形成し、
不活性雰囲気中で、前記単結晶半導体層を有する側より前記単結晶半導体層にレーザビームを照射し、前記単結晶半導体層の前記レーザビームが照射されている領域の表面から深さ方向の一部の領域を溶融することで、前記単結晶半導体層を再結晶化させ、
前記バッファ層は、第1の絶縁層と、第2の絶縁層と、酸化シリコン層とを有し、
前記第1の絶縁層は、酸化窒化シリコン層であり、
前記第2の絶縁層は、窒化シリコン層または窒化酸化シリコン層であり、
前記第2の絶縁層は、前記第1の絶縁層と前記酸化シリコン層との間に設けられ、
前記酸化シリコン層は、前記支持基板に接し、
前記損傷層に添加するイオンは、H 3 + を80%以上含むことを特徴とする半導体基板の作製方法。 - 請求項1または2において、
前記支持基板は、歪み点が650℃以上690℃以下であることを特徴とする半導体基板の作製方法。 - 請求項1乃至3のいずれか1項において、
前記支持基板は、ガラス基板であることを特徴とする半導体基板の作製方法。 - 請求項1乃至4のいずれか1項において、
前記レーザビームの断面形状は線状、正方形、または長方形であることを特徴とする半導体基板の作製方法。
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TW200933714A (en) | 2009-08-01 |
TWI533363B (zh) | 2016-05-11 |
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