ATE511210T1 - Verfahren für das herstellen eines soi wafers - Google Patents
Verfahren für das herstellen eines soi wafersInfo
- Publication number
- ATE511210T1 ATE511210T1 AT04291457T AT04291457T ATE511210T1 AT E511210 T1 ATE511210 T1 AT E511210T1 AT 04291457 T AT04291457 T AT 04291457T AT 04291457 T AT04291457 T AT 04291457T AT E511210 T1 ATE511210 T1 AT E511210T1
- Authority
- AT
- Austria
- Prior art keywords
- source
- handle
- compound
- substrate
- splitting area
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 150000001875 compounds Chemical class 0.000 abstract 3
- 239000000463 material Substances 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 3
- 235000012431 wafers Nutrition 0.000 abstract 3
- 230000003313 weakening effect Effects 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 239000012467 final product Substances 0.000 abstract 1
- 239000010453 quartz Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04291457A EP1605504B1 (de) | 2004-06-10 | 2004-06-10 | Verfahren für das Herstellen eines SOI Wafers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE511210T1 true ATE511210T1 (de) | 2011-06-15 |
Family
ID=34931164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04291457T ATE511210T1 (de) | 2004-06-10 | 2004-06-10 | Verfahren für das herstellen eines soi wafers |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7256103B2 (de) |
| EP (2) | EP1605504B1 (de) |
| JP (1) | JP4508955B2 (de) |
| AT (1) | ATE511210T1 (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5249511B2 (ja) * | 2006-11-22 | 2013-07-31 | 信越化学工業株式会社 | Ｓｏｑ基板およびｓｏｑ基板の製造方法 |
| FR2914496B1 (fr) | 2007-03-29 | 2009-10-02 | Soitec Silicon On Insulator | Amelioration de la defectivite post decollement d'une couche mince par modification de son recuit de decollement. |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2849178B2 (ja) * | 1990-07-27 | 1999-01-20 | 信越半導体株式会社 | ウェーハの保管方法 |
| US6037988A (en) * | 1996-03-22 | 2000-03-14 | Microsoft Corp | Method for generating sprites for object-based coding sytems using masks and rounding average |
| FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
| SG65697A1 (en) * | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
| US6027988A (en) | 1997-05-28 | 2000-02-22 | The Regents Of The University Of California | Method of separating films from bulk substrates by plasma immersion ion implantation |
| US5909627A (en) * | 1998-05-18 | 1999-06-01 | Philips Electronics North America Corporation | Process for production of thin layers of semiconductor material |
| JP2000012864A (ja) * | 1998-06-22 | 2000-01-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| JP2000150835A (ja) * | 1998-11-05 | 2000-05-30 | Fujitsu Ltd | 非単結晶シリコン薄膜の製造方法 |
| TW484184B (en) * | 1998-11-06 | 2002-04-21 | Canon Kk | Sample separating apparatus and method, and substrate manufacturing method |
| FR2797347B1 (fr) | 1999-08-04 | 2001-11-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
| EP1939932A1 (de) * | 1999-08-10 | 2008-07-02 | Silicon Genesis Corporation | Ein Substrat mit einer verspannten Silizium-Germanium Trennschicht |
| EP2259299A1 (de) * | 1999-10-14 | 2010-12-08 | Shin-Etsu Handotai Co., Ltd. | Verfahren zur Herstellung von SOI-Wafern und SOI-Wafer |
| JP2004063730A (ja) * | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Ｓｏｉウェーハの製造方法 |
| FR2847076B1 (fr) * | 2002-11-07 | 2005-02-18 | Soitec Silicon On Insulator | Procede de detachement d'une couche mince a temperature moderee apres co-implantation |
-
2004
- 2004-06-10 AT AT04291457T patent/ATE511210T1/de not_active IP Right Cessation
- 2004-06-10 EP EP04291457A patent/EP1605504B1/de not_active Expired - Lifetime
- 2004-06-10 EP EP10013020A patent/EP2293326A3/de not_active Withdrawn
- 2004-11-09 US US10/984,913 patent/US7256103B2/en active Active
-
2005
- 2005-06-10 JP JP2005171177A patent/JP4508955B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2293326A2 (de) | 2011-03-09 |
| US20050277267A1 (en) | 2005-12-15 |
| EP1605504B1 (de) | 2011-05-25 |
| JP2005354078A (ja) | 2005-12-22 |
| JP4508955B2 (ja) | 2010-07-21 |
| EP2293326A3 (de) | 2012-01-25 |
| EP1605504A1 (de) | 2005-12-14 |
| US7256103B2 (en) | 2007-08-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |