JP4508955B2 - 材料複合体ウェーハの製造方法 - Google Patents
材料複合体ウェーハの製造方法 Download PDFInfo
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- JP4508955B2 JP4508955B2 JP2005171177A JP2005171177A JP4508955B2 JP 4508955 B2 JP4508955 B2 JP 4508955B2 JP 2005171177 A JP2005171177 A JP 2005171177A JP 2005171177 A JP2005171177 A JP 2005171177A JP 4508955 B2 JP4508955 B2 JP 4508955B2
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- 239000000463 material Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000002131 composite material Substances 0.000 title description 35
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 37
- 230000003313 weakening effect Effects 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000010453 quartz Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000926 separation method Methods 0.000 claims description 24
- 238000003860 storage Methods 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000005350 fused silica glass Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- -1 and Ge Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000000638 solvent extraction Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 55
- 239000012467 final product Substances 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000000047 product Substances 0.000 description 7
- 238000003303 reheating Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000007717 exclusion Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Description
Claims (17)
- 材料複合体ウェーハの製造方法において、
a)ソース基板(1)に所定の分割領域(5)を形成するステップと、
b)ソース‐ハンドル複合体(9)を形成するために前記ソース基板(1)をハンドル基板(7)に取り付けるステップと、
c)前記所定の分割領域(5)を脆弱化するために前記ソース‐ハンドル複合体(9)を熱アニールするステップと、
d)前記ソース基板(1)を前記所定の分割領域(5)で機械的分割により分離するステップとを含み、
前記ソース基板(1)が第1の材料から作られており、前記ハンドル基板(7)が第2の材料から作られており、
ステップd)で前記ソース‐ハンドル複合体(9)を18℃〜25℃の範囲に相当する室温(RT)よりも高い分離温度の状態にし、前記分離温度において前記所定の分割領域(5)の脆弱化の程度を本質的に同一にとどめ、前記温度で前記機械的分割を実施することを特徴とする方法。 - 前記分離温度が150℃を下回っている請求項1に記載の方法。
- 前記分離温度が50℃を下回っている請求項1に記載の方法。
- 前記ソース‐ハンドル複合体(9)をステップc)とステップd)との間で室温(RT)よりも高い保管温度で保管し、前記保管温度ではその保管の間は前記所定の分割領域(5)の脆弱化の程度を同一程度にとどめている請求項1〜3のいずれか1項に記載の方法。
- 保管を、50℃〜150℃の温度で行う請求項4に記載の方法。
- 保管を、50℃〜140℃の温度で行う請求項4に記載の方法。
- 保管を、70℃〜120℃の温度で行う請求項4に記載の方法。
- 保管を、不活性雰囲気下で、特に窒素及び/又はアルゴンの雰囲気下で行う請求項4〜7のいずれか1項に記載の方法。
- 前記アニール済みソース‐ハンドル複合体(9)を炉(13)に保管する請求項4〜8のいずれか1項に記載の方法。
- 前記アニール済みソース‐ハンドル複合体(9)をホットプレート(13)上に保管する請求項4〜9のいずれか1項に記載の方法。
- 前記第1の材料及び/又は第2の材料が、シリコンと、A(III)‐B(V)半導体と、A(III)‐B(V)半導体の合金と、Geと、炭化ケイ素と、合成水晶と、溶融シリカとから成っている材料のグループの少なくとも1つである請求項1〜10のいずれか1項に記載の方法。
- 前記ソース‐ハンドル複合体(9)を、ステップc)の後で冷却し、それから機械的な分割の前に再加熱する請求項1〜11のいずれか1項に記載の方法。
- 前記ソース‐ハンドル複合体(9)を、150℃〜250℃の温度まで再加熱する請求項12に記載の方法。
- 前記ソース‐ハンドル複合体(9)を、180℃〜220℃の温度まで再加熱する請求項12に記載の方法。
- 前記ソース‐ハンドル複合体(9)を、180℃〜200℃の温度まで再加熱する請求項12に記載の方法。
- 前記ソース‐ハンドル複合体(9)を、1時間〜3時間に亘り再加熱する請求項12又は15のいずれか1項に記載の方法。
- 前記ソース‐ハンドル複合体(9)を、2時間に亘り再加熱する請求項12又は15のいずれか1項に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04291457A EP1605504B1 (en) | 2004-06-10 | 2004-06-10 | Method for manufacturing a SOI wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005354078A JP2005354078A (ja) | 2005-12-22 |
JP4508955B2 true JP4508955B2 (ja) | 2010-07-21 |
Family
ID=34931164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005171177A Active JP4508955B2 (ja) | 2004-06-10 | 2005-06-10 | 材料複合体ウェーハの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7256103B2 (ja) |
EP (2) | EP1605504B1 (ja) |
JP (1) | JP4508955B2 (ja) |
AT (1) | ATE511210T1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5249511B2 (ja) * | 2006-11-22 | 2013-07-31 | 信越化学工業株式会社 | Soq基板およびsoq基板の製造方法 |
FR2914496B1 (fr) * | 2007-03-29 | 2009-10-02 | Soitec Silicon On Insulator | Amelioration de la defectivite post decollement d'une couche mince par modification de son recuit de decollement. |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0484431A (ja) * | 1990-07-27 | 1992-03-17 | Shin Etsu Handotai Co Ltd | ウェーハの保管方法 |
JP2000150835A (ja) * | 1998-11-05 | 2000-05-30 | Fujitsu Ltd | 非単結晶シリコン薄膜の製造方法 |
JP2002516483A (ja) * | 1998-05-18 | 2002-06-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 半導体材料の改良された薄膜製造方法 |
JP2003506892A (ja) * | 1999-08-04 | 2003-02-18 | コミツサリア タ レネルジー アトミーク | 過度の脆弱化ステップを有した薄層の移送方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6037988A (en) * | 1996-03-22 | 2000-03-14 | Microsoft Corp | Method for generating sprites for object-based coding sytems using masks and rounding average |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
SG65697A1 (en) * | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
US6027988A (en) * | 1997-05-28 | 2000-02-22 | The Regents Of The University Of California | Method of separating films from bulk substrates by plasma immersion ion implantation |
JP2000012864A (ja) * | 1998-06-22 | 2000-01-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
TW484184B (en) * | 1998-11-06 | 2002-04-21 | Canon Kk | Sample separating apparatus and method, and substrate manufacturing method |
WO2001011930A2 (en) * | 1999-08-10 | 2001-02-15 | Silicon Genesis Corporation | A cleaving process to fabricate multilayered substrates using low implantation doses |
JP4103391B2 (ja) * | 1999-10-14 | 2008-06-18 | 信越半導体株式会社 | Soiウエーハの製造方法及びsoiウエーハ |
JP2004063730A (ja) * | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
FR2847076B1 (fr) * | 2002-11-07 | 2005-02-18 | Soitec Silicon On Insulator | Procede de detachement d'une couche mince a temperature moderee apres co-implantation |
-
2004
- 2004-06-10 EP EP04291457A patent/EP1605504B1/en active Active
- 2004-06-10 EP EP10013020A patent/EP2293326A3/en not_active Withdrawn
- 2004-06-10 AT AT04291457T patent/ATE511210T1/de not_active IP Right Cessation
- 2004-11-09 US US10/984,913 patent/US7256103B2/en active Active
-
2005
- 2005-06-10 JP JP2005171177A patent/JP4508955B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0484431A (ja) * | 1990-07-27 | 1992-03-17 | Shin Etsu Handotai Co Ltd | ウェーハの保管方法 |
JP2002516483A (ja) * | 1998-05-18 | 2002-06-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 半導体材料の改良された薄膜製造方法 |
JP2000150835A (ja) * | 1998-11-05 | 2000-05-30 | Fujitsu Ltd | 非単結晶シリコン薄膜の製造方法 |
JP2003506892A (ja) * | 1999-08-04 | 2003-02-18 | コミツサリア タ レネルジー アトミーク | 過度の脆弱化ステップを有した薄層の移送方法 |
Also Published As
Publication number | Publication date |
---|---|
US20050277267A1 (en) | 2005-12-15 |
EP1605504B1 (en) | 2011-05-25 |
ATE511210T1 (de) | 2011-06-15 |
JP2005354078A (ja) | 2005-12-22 |
EP2293326A2 (en) | 2011-03-09 |
EP2293326A3 (en) | 2012-01-25 |
EP1605504A1 (en) | 2005-12-14 |
US7256103B2 (en) | 2007-08-14 |
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