TW200715388A - Method for dicing a wafer - Google Patents

Method for dicing a wafer

Info

Publication number
TW200715388A
TW200715388A TW094136026A TW94136026A TW200715388A TW 200715388 A TW200715388 A TW 200715388A TW 094136026 A TW094136026 A TW 094136026A TW 94136026 A TW94136026 A TW 94136026A TW 200715388 A TW200715388 A TW 200715388A
Authority
TW
Taiwan
Prior art keywords
wafer
reference point
dicing
cracks
temperature difference
Prior art date
Application number
TW094136026A
Other languages
Chinese (zh)
Other versions
TWI256674B (en
Inventor
Chien-Yu Chen
Hung-Pin Li
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW94136026A priority Critical patent/TWI256674B/en
Application granted granted Critical
Publication of TWI256674B publication Critical patent/TWI256674B/en
Publication of TW200715388A publication Critical patent/TW200715388A/en

Links

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  • Dicing (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)

Abstract

A method for dicing a wafer is disclosed. In the the method, a wafer containing a first surface and a second surface opposite the first surface is supplied firstly, herein a plurality of scribe lines on the first surface. The wafer is then vertically diced along the scribe lines from the first surface to a reference point so as to form a plurality of scribe lanes, herein the reference point is at a predetermined distance from the second surface. Thereafter, a thermal shake process is performed on the wafer to generate a temperature difference between the reference point and the second surface, herein the temperature difference produces a stress concentration between the reference point and the second surface to form a plurality of cracks thereon, thereby dicing the wafer by the cracks to form a plurality of dies.
TW94136026A 2005-10-14 2005-10-14 Method for dicing a wafer TWI256674B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94136026A TWI256674B (en) 2005-10-14 2005-10-14 Method for dicing a wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94136026A TWI256674B (en) 2005-10-14 2005-10-14 Method for dicing a wafer

Publications (2)

Publication Number Publication Date
TWI256674B TWI256674B (en) 2006-06-11
TW200715388A true TW200715388A (en) 2007-04-16

Family

ID=37614744

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94136026A TWI256674B (en) 2005-10-14 2005-10-14 Method for dicing a wafer

Country Status (1)

Country Link
TW (1) TWI256674B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI576970B (en) * 2016-04-08 2017-04-01 上海新昇半導體科技有限公司 Method for ramp down the temperature of wafer in load lock and devicde for ramp down the temperature of wafer
TWI742276B (en) * 2017-06-05 2021-10-11 日商迪思科股份有限公司 Wafer manufacturing method
TWI815900B (en) * 2018-06-06 2023-09-21 日商迪思科股份有限公司 Wafer processing methods

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110098148A (en) * 2018-01-30 2019-08-06 株式会社迪思科 The processing method of chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI576970B (en) * 2016-04-08 2017-04-01 上海新昇半導體科技有限公司 Method for ramp down the temperature of wafer in load lock and devicde for ramp down the temperature of wafer
TWI742276B (en) * 2017-06-05 2021-10-11 日商迪思科股份有限公司 Wafer manufacturing method
TWI815900B (en) * 2018-06-06 2023-09-21 日商迪思科股份有限公司 Wafer processing methods

Also Published As

Publication number Publication date
TWI256674B (en) 2006-06-11

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees