ATE515794T1 - Verfahren zur herstellung eines geoi-wafers (germanium on insulator) - Google Patents

Verfahren zur herstellung eines geoi-wafers (germanium on insulator)

Info

Publication number
ATE515794T1
ATE515794T1 AT08007334T AT08007334T ATE515794T1 AT E515794 T1 ATE515794 T1 AT E515794T1 AT 08007334 T AT08007334 T AT 08007334T AT 08007334 T AT08007334 T AT 08007334T AT E515794 T1 ATE515794 T1 AT E515794T1
Authority
AT
Austria
Prior art keywords
substrate
germanium
handle
source
insulator
Prior art date
Application number
AT08007334T
Other languages
English (en)
Inventor
Konstantin Bourdelle
Fabrice Letertre
Bruce Fauvre
Christophe Morales
Chrystal Deguet
Original Assignee
S O I Tec Silicon
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S O I Tec Silicon, Commissariat Energie Atomique filed Critical S O I Tec Silicon
Application granted granted Critical
Publication of ATE515794T1 publication Critical patent/ATE515794T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Inorganic Insulating Materials (AREA)
AT08007334T 2004-11-19 2004-11-19 Verfahren zur herstellung eines geoi-wafers (germanium on insulator) ATE515794T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04292742A EP1659623B1 (de) 2004-11-19 2004-11-19 Verfahren zur Herstellung eines Germanium-On-Insulator-Wafers (GeOI)

Publications (1)

Publication Number Publication Date
ATE515794T1 true ATE515794T1 (de) 2011-07-15

Family

ID=34931539

Family Applications (2)

Application Number Title Priority Date Filing Date
AT04292742T ATE392712T1 (de) 2004-11-19 2004-11-19 Verfahren zur herstellung eines germanium-on- insulator-wafers (geoi)
AT08007334T ATE515794T1 (de) 2004-11-19 2004-11-19 Verfahren zur herstellung eines geoi-wafers (germanium on insulator)

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AT04292742T ATE392712T1 (de) 2004-11-19 2004-11-19 Verfahren zur herstellung eines germanium-on- insulator-wafers (geoi)

Country Status (9)

Country Link
US (1) US7229898B2 (de)
EP (2) EP1973155B1 (de)
JP (1) JP4173884B2 (de)
KR (1) KR100734239B1 (de)
CN (1) CN100472709C (de)
AT (2) ATE392712T1 (de)
DE (1) DE602004013163T2 (de)
SG (1) SG122908A1 (de)
TW (1) TWI297171B (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
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US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7568412B2 (en) * 2005-10-04 2009-08-04 Marquip, Llc Method for order transition on a plunge slitter
FR2892230B1 (fr) * 2005-10-19 2008-07-04 Soitec Silicon On Insulator Traitement d'une couche de germamium
KR100823031B1 (ko) * 2006-12-21 2008-04-17 동부일렉트로닉스 주식회사 이미지 센서 제조방법
ATE518241T1 (de) * 2007-01-24 2011-08-15 Soitec Silicon On Insulator Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer
FR2912552B1 (fr) * 2007-02-14 2009-05-22 Soitec Silicon On Insulator Structure multicouche et son procede de fabrication.
WO2008123116A1 (en) 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
WO2008123117A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
SG178762A1 (en) 2007-04-13 2012-03-29 Semiconductor Energy Lab Display device, method for manufacturing display device, and soi substrate
EP1986229A1 (de) * 2007-04-27 2008-10-29 S.O.I.T.E.C. Silicon on Insulator Technologies Herstellungsverfahren für Wafer aus Verbundmaterial und entsprechender Wafer aus Verbundmaterial
US20080274626A1 (en) * 2007-05-04 2008-11-06 Frederique Glowacki Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface
US8513678B2 (en) * 2007-05-18 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
FR2923079B1 (fr) * 2007-10-26 2017-10-27 S O I Tec Silicon On Insulator Tech Substrats soi avec couche fine isolante enterree
WO2009057669A1 (en) * 2007-11-01 2009-05-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing photoelectric conversion device
JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
WO2009115859A1 (en) * 2008-03-19 2009-09-24 S.O.I. Tec Silicon On Insulator Technologies Substrates for monolithic optical circuits and electronic circuits
FR2933534B1 (fr) * 2008-07-03 2011-04-01 Soitec Silicon On Insulator Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat
EP2161742A1 (de) * 2008-09-03 2010-03-10 S.O.I.TEC. Silicon on Insulator Technologies S.A. Verfahren zur Herstellung eines lokal passivierten Germanium-on-Insulator-Substrats
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
CN102169888B (zh) * 2011-03-10 2012-11-14 清华大学 应变GeOI结构及其形成方法
US8786017B2 (en) 2011-03-10 2014-07-22 Tsinghua University Strained Ge-on-insulator structure and method for forming the same
US8890209B2 (en) * 2011-03-10 2014-11-18 Tsinghua University Strained GE-ON-insulator structure and method for forming the same
US8704306B2 (en) * 2011-03-10 2014-04-22 Tsinghua University Strained Ge-on-insulator structure and method for forming the same
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
CN103832970B (zh) * 2012-11-27 2016-06-15 中国科学院微电子研究所 一种低温晶圆键合方法
KR102279162B1 (ko) * 2015-03-03 2021-07-20 한국전자통신연구원 게르마늄 온 인슐레이터 기판 및 그의 형성방법
KR101889352B1 (ko) 2016-09-13 2018-08-20 한국과학기술연구원 변형된 저마늄을 포함하는 반도체 소자의 제조 방법 및 이에 의해 제조된 반도체 소자
US10763115B2 (en) * 2017-06-16 2020-09-01 Nxp Usa, Inc. Substrate treatment method for semiconductor device fabrication
US10276687B1 (en) * 2017-12-20 2019-04-30 International Business Machines Corporation Formation of self-aligned bottom spacer for vertical transistors
FR3111232B1 (fr) * 2020-06-09 2022-05-06 Soitec Silicon On Insulator Substrat temporaire demontable compatible avec de tres hautes temperatures et procede de transfert d’une couche utile a partir dudit substrat
CN114256345A (zh) * 2020-09-21 2022-03-29 上海华力集成电路制造有限公司 一种fdsoi器件结构及其制备方法
CN115070512B (zh) * 2022-03-11 2024-04-26 北京爱瑞思光学仪器有限公司 一种锗晶片的双抛工艺、装置及锗晶片

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
JP2004335642A (ja) * 2003-05-06 2004-11-25 Canon Inc 基板およびその製造方法
EP1652226A2 (de) * 2003-08-04 2006-05-03 ASM America, Inc. Oberflächenbehandlung vor der ablagerung auf germanium

Also Published As

Publication number Publication date
EP1659623A1 (de) 2006-05-24
CN100472709C (zh) 2009-03-25
KR100734239B1 (ko) 2007-07-02
TW200618047A (en) 2006-06-01
TWI297171B (en) 2008-05-21
DE602004013163D1 (de) 2008-05-29
US20060110899A1 (en) 2006-05-25
DE602004013163T2 (de) 2009-05-14
JP4173884B2 (ja) 2008-10-29
US7229898B2 (en) 2007-06-12
JP2006148066A (ja) 2006-06-08
CN1776886A (zh) 2006-05-24
EP1659623B1 (de) 2008-04-16
EP1973155A1 (de) 2008-09-24
EP1973155B1 (de) 2011-07-06
SG122908A1 (en) 2006-06-29
ATE392712T1 (de) 2008-05-15
KR20060056239A (ko) 2006-05-24

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