DE60238548D1 - Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten - Google Patents

Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten

Info

Publication number
DE60238548D1
DE60238548D1 DE60238548T DE60238548T DE60238548D1 DE 60238548 D1 DE60238548 D1 DE 60238548D1 DE 60238548 T DE60238548 T DE 60238548T DE 60238548 T DE60238548 T DE 60238548T DE 60238548 D1 DE60238548 D1 DE 60238548D1
Authority
DE
Germany
Prior art keywords
substrate
microcomponents
thin layers
layers containing
implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60238548T
Other languages
English (en)
Inventor
Bernard Aspar
Chrystelle Lagahe
Bruno Ghyselen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE60238548D1 publication Critical patent/DE60238548D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
DE60238548T 2001-10-11 2002-10-08 Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten Expired - Lifetime DE60238548D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0113105A FR2830983B1 (fr) 2001-10-11 2001-10-11 Procede de fabrication de couches minces contenant des microcomposants
PCT/FR2002/003422 WO2003032384A1 (fr) 2001-10-11 2002-10-08 Procede de fabrication de couches minces contenant des microcomposants

Publications (1)

Publication Number Publication Date
DE60238548D1 true DE60238548D1 (de) 2011-01-20

Family

ID=8868171

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60238548T Expired - Lifetime DE60238548D1 (de) 2001-10-11 2002-10-08 Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten

Country Status (10)

Country Link
US (1) US7615463B2 (de)
EP (1) EP1435111B1 (de)
JP (1) JP4425631B2 (de)
KR (1) KR20040051605A (de)
CN (1) CN100440477C (de)
AT (1) ATE491225T1 (de)
DE (1) DE60238548D1 (de)
FR (1) FR2830983B1 (de)
TW (1) TWI307125B (de)
WO (1) WO2003032384A1 (de)

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FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
DE60336543D1 (de) 2003-05-27 2011-05-12 Soitec Silicon On Insulator Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
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FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
KR101219358B1 (ko) * 2011-07-26 2013-01-21 삼성코닝정밀소재 주식회사 기판 분리 방법 및 이를 이용한 접합기판 제조방법
TWI573198B (zh) * 2011-09-27 2017-03-01 索泰克公司 在三度空間集積製程中轉移材料層之方法及其相關結構與元件
US8673733B2 (en) * 2011-09-27 2014-03-18 Soitec Methods of transferring layers of material in 3D integration processes and related structures and devices
US8841742B2 (en) 2011-09-27 2014-09-23 Soitec Low temperature layer transfer process using donor structure with material in recesses in transfer layer, semiconductor structures fabricated using such methods
CN104507853B (zh) 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
FR3074960B1 (fr) * 2017-12-07 2019-12-06 Soitec Procede de transfert d'une couche utilisant une structure demontable
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture
FR3094559A1 (fr) * 2019-03-29 2020-10-02 Soitec Procédé de transfert de paves d’un substrat donneur sur un substrat receveur

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Also Published As

Publication number Publication date
KR20040051605A (ko) 2004-06-18
EP1435111A1 (de) 2004-07-07
JP2005505935A (ja) 2005-02-24
ATE491225T1 (de) 2010-12-15
US20050221583A1 (en) 2005-10-06
JP4425631B2 (ja) 2010-03-03
EP1435111B1 (de) 2010-12-08
CN1586004A (zh) 2005-02-23
CN100440477C (zh) 2008-12-03
US7615463B2 (en) 2009-11-10
FR2830983B1 (fr) 2004-05-14
TWI307125B (en) 2009-03-01
FR2830983A1 (fr) 2003-04-18
WO2003032384A1 (fr) 2003-04-17

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