WO2004001842A3 - Schicht-anordnung und verfahren zum herstellen einer schicht-anordnung - Google Patents

Schicht-anordnung und verfahren zum herstellen einer schicht-anordnung Download PDF

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Publication number
WO2004001842A3
WO2004001842A3 PCT/DE2003/001827 DE0301827W WO2004001842A3 WO 2004001842 A3 WO2004001842 A3 WO 2004001842A3 DE 0301827 W DE0301827 W DE 0301827W WO 2004001842 A3 WO2004001842 A3 WO 2004001842A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer assembly
layer
producing
assembly
decomposable material
Prior art date
Application number
PCT/DE2003/001827
Other languages
English (en)
French (fr)
Other versions
WO2004001842A2 (de
Inventor
Hans-Joachim Barth
Recai Sezi
Original Assignee
Infineon Technologies Ag
Hans-Joachim Barth
Recai Sezi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Hans-Joachim Barth, Recai Sezi filed Critical Infineon Technologies Ag
Priority to JP2004514543A priority Critical patent/JP2005534168A/ja
Priority to EP03760551A priority patent/EP1514303A2/de
Priority to US10/518,880 priority patent/US20060014374A1/en
Publication of WO2004001842A2 publication Critical patent/WO2004001842A2/de
Publication of WO2004001842A3 publication Critical patent/WO2004001842A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Laminated Bodies (AREA)

Abstract

Die Erfindung betrifft eine Schicht-Anordnung und ein Verfahren zum Herstellen einer Schicht-Anordnung. Die Schicht-Anordnung hat eine auf einem Substrat angeordnete Schicht, die einen ersten Teilbereich aus zersetzbarem Material und einen daneben angeordneten zweiten Teilbereich mit einer Nutzstruktur aus einem nicht-zersetzbaren Material aufweist. Ferner hat die Schicht-Anordnung eine Deckschicht auf der Schicht aus zersetzbarem Material und der Nutzstruktur, wobei die Schicht-Anordnung derart eingerichtet ist, dass das zersetzbare Material aus der Schicht-Anordnung entfernbar ist.
PCT/DE2003/001827 2002-06-20 2003-06-03 Schicht-anordnung und verfahren zum herstellen einer schicht-anordnung WO2004001842A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004514543A JP2005534168A (ja) 2002-06-20 2003-06-03 層配置物および層配置物の製造方法
EP03760551A EP1514303A2 (de) 2002-06-20 2003-06-03 Schicht-anordnung und verfahren zum herstellen einer schicht-anordnung
US10/518,880 US20060014374A1 (en) 2002-06-20 2003-06-03 Layer assembly and method for producing a layer assembly

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10227615A DE10227615A1 (de) 2002-06-20 2002-06-20 Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
DE10227615.3 2002-06-20

Publications (2)

Publication Number Publication Date
WO2004001842A2 WO2004001842A2 (de) 2003-12-31
WO2004001842A3 true WO2004001842A3 (de) 2004-03-11

Family

ID=29723324

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001827 WO2004001842A2 (de) 2002-06-20 2003-06-03 Schicht-anordnung und verfahren zum herstellen einer schicht-anordnung

Country Status (7)

Country Link
US (1) US20060014374A1 (de)
EP (1) EP1514303A2 (de)
JP (1) JP2005534168A (de)
CN (1) CN100349280C (de)
DE (1) DE10227615A1 (de)
TW (1) TWI222137B (de)
WO (1) WO2004001842A2 (de)

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* Cited by examiner, † Cited by third party
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CN101094804B (zh) * 2004-03-15 2011-12-28 佐治亚技术研究公司 微机电系统封装件及其制造方法
EP1577940B1 (de) * 2004-03-17 2017-04-05 Imec Verfahren zur Herstellung einer Halbleitervorrichtung mit Damaszenstrukturen mit Luftzwischenräumen
TWI292933B (en) * 2004-03-17 2008-01-21 Imec Inter Uni Micro Electr Method of manufacturing a semiconductor device having damascene structures with air gaps
US7371684B2 (en) * 2005-05-16 2008-05-13 International Business Machines Corporation Process for preparing electronics structures using a sacrificial multilayer hardmask scheme
US7337671B2 (en) 2005-06-03 2008-03-04 Georgia Tech Research Corp. Capacitive microaccelerometers and fabrication methods
FR2897198B1 (fr) * 2006-02-08 2008-09-19 Commissariat Energie Atomique Structure d'interconnexions et procede de realisation
US7578189B1 (en) 2006-05-10 2009-08-25 Qualtre, Inc. Three-axis accelerometers
US7767484B2 (en) 2006-05-31 2010-08-03 Georgia Tech Research Corporation Method for sealing and backside releasing of microelectromechanical systems
US8778801B2 (en) * 2012-09-21 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming seed layer structure
CN106684335A (zh) * 2017-02-06 2017-05-17 厦门大学 一种锂离子电池微米级硅负极的制备方法

Citations (4)

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US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US6165890A (en) * 1997-01-21 2000-12-26 Georgia Tech Research Corporation Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections
US20020016058A1 (en) * 2000-06-15 2002-02-07 Bin Zhao Microelectronic air-gap structures and methods of forming the same
WO2002019420A2 (en) * 2000-08-31 2002-03-07 Georgia Tech Research Corporation Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnection structures

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JP2555940B2 (ja) * 1993-07-27 1996-11-20 日本電気株式会社 半導体装置及びその製造方法
DE4441898C1 (de) * 1994-11-24 1996-04-04 Siemens Ag Verfahren zur Herstellung eines Halbleiterbauelementes
JP2763023B2 (ja) * 1995-12-18 1998-06-11 日本電気株式会社 半導体装置の製造方法
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6365958B1 (en) * 1998-02-06 2002-04-02 Texas Instruments Incorporated Sacrificial structures for arresting insulator cracks in semiconductor devices
JP3137087B2 (ja) * 1998-08-31 2001-02-19 日本電気株式会社 半導体装置の製造方法
KR100308871B1 (ko) * 1998-12-28 2001-11-03 윤덕용 동축 구조의 신호선 및 그의 제조 방법
JP3691982B2 (ja) * 1999-03-12 2005-09-07 株式会社東芝 半導体装置の製造方法
US6030896A (en) * 1999-04-21 2000-02-29 National Semiconductor Corporation Self-aligned copper interconnect architecture with enhanced copper diffusion barrier
US6342722B1 (en) * 1999-08-05 2002-01-29 International Business Machines Corporation Integrated circuit having air gaps between dielectric and conducting lines
US6153935A (en) * 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
TW476134B (en) * 2000-02-22 2002-02-11 Ibm Method for forming dual-layer low dielectric barrier for interconnects and device formed
KR100499304B1 (ko) * 2000-03-21 2005-07-04 신에쓰 가가꾸 고교 가부시끼가이샤 레지스트 재료 및 패턴 형성 방법
US6265321B1 (en) * 2000-04-17 2001-07-24 Chartered Semiconductor Manufacturing Ltd. Air bridge process for forming air gaps
US6413852B1 (en) * 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
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* Cited by examiner, † Cited by third party
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US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US6165890A (en) * 1997-01-21 2000-12-26 Georgia Tech Research Corporation Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections
US20020016058A1 (en) * 2000-06-15 2002-02-07 Bin Zhao Microelectronic air-gap structures and methods of forming the same
WO2002019420A2 (en) * 2000-08-31 2002-03-07 Georgia Tech Research Corporation Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnection structures

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
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Also Published As

Publication number Publication date
EP1514303A2 (de) 2005-03-16
DE10227615A1 (de) 2004-01-15
WO2004001842A2 (de) 2003-12-31
JP2005534168A (ja) 2005-11-10
TWI222137B (en) 2004-10-11
CN100349280C (zh) 2007-11-14
US20060014374A1 (en) 2006-01-19
TW200400561A (en) 2004-01-01
CN1663040A (zh) 2005-08-31

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