經濟部智慧財產局員工消費合作社印製 476134 A7 B7_ 五、發明說明（1 ) 發明領域 本發明一般係關於形成用於互連之低介電質障礙層之方 法及所形成之裝置以及更特別關於以連續沈積層形成用於 擴散障礙及附著改良之半導體結構之銅互連上之雙層低介 電質障礙層之方法及藉由該方法所形成之裝置。 發明背景 形成用於提供半導體晶片結構、平板顯示器以及封裝應 用之介質、線以及其他凹處之互連技術已經發展多年。例 如，在發展超大型積體電路（VLSI)結構之互連技術時，鋁 已經利用爲位在單一底材上之半導體區或是裝置之接觸及 互連之主要金屬源。因爲其低成本、良好歐姆觸點以及高 導電率，鋁已經爲選擇之材料。 然而，純鋁薄膜導體具有令人不滿意性質如低融點，該 性質限制其使用於低溫處理、在回火期間可能之Si擴散至 A1中而導致接觸及接合失效以及不良電性遷移阻抗。當金 屬固體之電場重疊在隨機加熱擴散上而造成淨離子漂移時 該電性遷移現像發生。因此，已經發展許多鋁合金，提供 在純鋁之上之優點。例如，美國專利案案飞虎爲第4,566，177 號揭示銘合金導電層，該合金最高包含3%比重之秒、銅、 鎳、鉻及錳以改良電性遷移阻抗。美國專利案案號爲第 3,631，304號揭示具有氧化鋁之鋁合金，該鋁合金亦用以改 良電性遷移阻抗。 最近，VLSI及ULSI技術已經置放更多嚴厲要求在接線需 求上，因爲該裝置具有高電路密度及需要較快速操作速度 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 裝—— (請先閱讀背面之注意事項再填寫本頁) · 476134 A7 B7 五、發明說明（2 ) 。此情形導致逐漸變小之導線中之較高電流密度。結果， 要求導電接線，該接線需要鋁合金導體或是具有較高導電 率之不同電線材料之較大橫截面電線。該工業之明顯選擇 爲依據令人滿意之高導電率而使用銅發展後者。 在VLSI及ULSI互連結構如介質及線之形成中，銅沈積至 線、介質及其他凹處内以互連位於相同底材上之半導體區 域或是裝置。銅由於其與Si之快速反應速率而已知在半導 體裝置接合具有問題。任何銅原子或是離子擴散至矽底材 中可能造成裝置失效。除此以外，銅擴散至金屬間介電質 中亦可把因爲產生短路及開路而造成裝置失效。所以對銅 互連之可靠度極其重要，該互連爲塗層以防止銅與周圍材 料相互擴散。這些層，通常稱爲，，櫬墊”、，，障礙，，及，，蓋，，， 亦必須展現介於該銅互連與種種不同介電質層以及接觸介 質之間之良好附著。 在銅線後端（BEOL)之晶片網路互連之金屬化處理中，介 浃及渠溝爲利用厚介電質沈積、介質及渠溝開口、薄櫬墊 沈積在介質及渠溝壁上、以銅充填介質及渠溝壁、頂部銅 表面平坦化以及最終以保護層覆蓋頂部表面之標準連續稃 f加以金屬化以供防止銅遷移至次上階層介電質以及^於 將與銅t相互作用最小化而上階層介電質爲沈積。最終覆 蓋層另外作用爲次上層介電質之反應性離子蝕刻停止層。 邊金屬化處理重複於各階層互連接線。 在傳統處理中，用以覆蓋各銅BE0L階層之最普通材料爲 氮化矽（SiN)。在ULSI中已經可靠地製造，其中Cu爲金屬 Μ氏張尺度適關家標準（CNS)A4規格⑵〇 χ 297公髮「 裝— (請先閱讀背面之注意事項再填寫本頁) 訂. 經濟部智慧財產局員工消費合作社印製 -5- 經濟部智慧財產局員工消費合作社印製 476134 A7 B7_ 五、發明說明（3 ) 間介電質而二氧化矽（Si02)爲互連介電質。然而，對互連 之連續效能改良而言，該ULSI工業正趨向低介電常數（低k) 金屬間介電質。SiN具有相當高介電常數7至8以及明顯地增 加有效之階層内部電容。未來BEOL之SiN應用將最小化或 是取代以符合低k需求。 解答已經由其他人提議以解決銅低k BEOL困難度。例如 ，一解答爲使用自我對準金屬覆蓋層以涵蓋及保護銅線之 頂部表面，以提供良好附著以及此外，作用爲銅擴散之障 礙層。然而，爲符合所需銅障礙層性質，該金屬覆蓋層厚 度必須爲至少1，000〜2,000 A，當介於該線之間之間隔小於 3,000 A時，可能造成介於導線之間之短路。僅有金屬之蓋 之使用在處理次階層介電質時亦呈現困難度。在上階層介 電質之反應性離子蝕刻（RIE)期間沒有蚀刻停止以及下金屬 及介電質將易於由此RIE處理蚀刻及造成污染物。 還有其他人已經藉由使用由如包含Si、C、Η或是Si、C 、Ο、Η之厚度最高爲800 A之那些材料形成之薄，低k介 電質膜而提議一解答。然而，這些低k膜（具有小於4之介電 常數）通常不作用爲良好銅擴散障礙層。在BEOL互連製造 期間，它們亦不是銅氧化之良好障礙層以及可能因爲CuO 形成大大地減弱附著及形成空隙而造成災難性失效。在比 較上，SiN通常藉由SiH4及NH3之電漿增強之化學汽相沈積 (PECVD)法沈積，本身不會造成銅氧化以及SiN已知爲良好 氧化障礙層。 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476134 A7 B7_ V. Description of the Invention (1) Field of the Invention The present invention generally relates to a method for forming a low-dielectric barrier layer for interconnection and a device formed therefor, and more particularly to Method for forming double-layered low-dielectric barrier layer on copper interconnect for diffusion barrier and adhesion-improved semiconductor structure by continuous deposition layer and device formed by the method. BACKGROUND OF THE INVENTION Interconnect technology for forming dielectrics, wires, and other recesses for providing semiconductor wafer structures, flat panel displays, and packaging applications has been developed for many years. For example, in the development of interconnect technology for very large-scale integrated circuit (VLSI) structures, aluminum has been used as the primary metal source for semiconductor regions or device contacts and interconnections on a single substrate. Because of its low cost, good ohmic contacts, and high electrical conductivity, aluminum has been the material of choice. However, pure aluminum thin film conductors have unsatisfactory properties such as low melting points, which limits their use in low temperature processing, possible Si diffusion into A1 during tempering, resulting in contact and bonding failures and poor electrical migration resistance. This electromigration phenomenon occurs when the electric field of a metal solid overlaps with random heating diffusion and causes a drift of ionic ions. Therefore, many aluminum alloys have been developed to provide advantages over pure aluminum. For example, U.S. patent case Feihu No. 4,566,177 discloses a conductive layer of Ming alloy, which contains a maximum of 3% seconds, copper, nickel, chromium, and manganese to improve electrical migration resistance. U.S. Patent No. 3,631,304 discloses an aluminum alloy with alumina, which is also used to improve electrical migration resistance. Recently, VLSI and ULSI technologies have placed more stringent requirements on wiring requirements, because the device has a high circuit density and requires faster operating speed. -4- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) Packing-(Please read the notes on the back before filling out this page) · 476134 A7 B7 V. Description of the invention (2). This situation results in a higher current density in the gradually smaller wires. As a result, conductive wiring is required, which requires an aluminum alloy conductor or a larger cross-section wire of a different wire material having a higher conductivity. The industry's obvious choice was to use copper to develop the latter based on satisfactory high electrical conductivity. In the formation of VLSI and ULSI interconnect structures such as dielectrics and wires, copper is deposited into the wires, dielectrics, and other recesses to interconnect semiconductor regions or devices on the same substrate. Copper is known to have problems bonding in semiconductor devices due to its fast reaction rate with Si. Any diffusion of copper atoms or ions into the silicon substrate may cause the device to fail. In addition, copper diffusion into intermetallic dielectrics can also cause device failure due to short circuits and open circuits. Therefore, it is extremely important for the reliability of the copper interconnect, which is a coating to prevent copper from diffusing with surrounding materials. These layers, commonly referred to as "pads", barriers, and caps, must also exhibit good adhesion between the copper interconnect and the various dielectric layers and contact media. In the metallization process of the copper wire back-end (BEOL) chip network interconnection, the dielectrics and trenches are deposited using thick dielectrics, dielectrics and trench openings, and thin trenches are deposited on the dielectrics and trench walls. Standard continuous with copper filling media and trench walls, top copper surface flattening, and finally covering the top surface with a protective layer is metallized to prevent copper from migrating to the next-level dielectric and to interact with copper. The effect is minimized and the upper layer dielectric is deposited. The final cover layer additionally acts as a reactive ion etch stop layer for the next upper layer dielectric. The edge metallization process is repeated at each level of interconnect wiring. In traditional processes, it is used to The most common material covering each copper BE0L layer is silicon nitride (SiN). It has been reliably manufactured in ULSI, of which Cu is a metal M-scale standard (CNS) A4 specification ⑵χχ297 — (Please read the first (Please fill in this page again for the matters needing attention) Order. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics -5- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 476134 A7 B7_ V. Description of the Invention (3) Dielectric dielectric and silicon dioxide (Si02) is an interconnect dielectric. However, for continuous performance improvement of interconnects, the ULSI industry is moving towards a low dielectric constant (low k) intermetal dielectric. SiN has a fairly high dielectric constant of 7 to 8 and significantly increase the effective internal capacitance of the hierarchy. In the future, the SiN application of BEOL will be minimized or replaced to meet the low-k requirement. The solution has been proposed by others to solve the difficulty of copper low-k BEOL. For example, one solution is to use self Align the metal overlay to cover and protect the top surface of the copper wire to provide good adhesion and, in addition, act as a barrier to copper diffusion. However, to meet the required copper barrier properties, the thickness of the metal overlay must be at least 1 2,000 ~ 2,000 A, when the interval between the wires is less than 3,000 A, it may cause a short circuit between the wires. The use of only a metal cover is also presented when processing sub-level dielectrics. There is no difficulty. There is no etch stop during the reactive ion etching (RIE) of the upper-layer dielectric and the lower metal and dielectric will be susceptible to etching and contamination by this RIE. Still others have used the A solution is proposed for thin, low-k dielectric films that include Si, C, rhenium, or those with a maximum thickness of 800 A of Si, C, 0, and Η. However, these low-k films (with less than 4 (Dielectric constant) usually does not act as a good copper diffusion barrier. They are also not good barriers to copper oxidation during BEOL interconnect manufacturing and may cause catastrophic failure due to CuO formation which greatly reduces adhesion and forms voids. In comparison, SiN is usually deposited by plasma enhanced chemical vapor deposition (PECVD) method of SiH4 and NH3, which does not itself cause copper oxidation and SiN is known as a good oxidation barrier. -6- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
476134 五、發明說明（4) 所以本發明之一目的爲提供用於形成陳礙層在銅導體上 之方法，該障礙層沒有傳統銅障礙層缺陷及短處。 裝--- (請先閱讀背面之注意事項再填寫本頁) —本發明之另一目的爲提供縮減SiN蓋厚度以及改良其附 著至銅之方法。 本發明i另一目的爲提供用於形成低介電質障礙層在銅 導體上之方法，改良擴散障礙及附著性質。 本發明i另一目的爲提供用於形成雙層介電質障礙層在 銅導體上之方法，其中包含磷或硼之金屬合金膜以及包含 石夕之低介電質材料爲連續沈積在銅導體頂部上。 本發明心另一目的爲提供藉由在回火處理之前沈積附著 及擴散障礙層之二分離層而用於形成雙層介電質障礙層在 銅導體上之方法。 胃 本發明之另一目的爲提供用於形成雙層介電質障礙層在 銅線後端處理中使用爲介質或是互連之銅導體上之方法。 本發明之另一目的爲提供用於形成雙層介電質障礙層在 銅導體上之方法，其中包含磷或硼之金屬合金膜之沈積處 理緊接著回火處理以使得該金屬合金擴散至該銅導體至少 2 - 4原子層中。 經濟部智慧財產局員工消費合作社即製 本發明之另一目的爲提供半導體結構之電氣導體，包含 金屬導體、包含磷或硼之金屬合金膜以及頂部上之介電 質材料膜。 ％ 本發明之另一目的爲提供半導體結構之電氣導體，其中 厚度介於50 A與200 A之間之一層包含磷或硼之金屬合金 經濟部智慧財產局員工消費合作社印製 476134 A7 B7 五、發明說明（5 ) 膜首先沈積在金屬導體上，以及厚度介於100 A與500 A之 間之低k介電質材料之後沈積在該金屬合金膜頂部上。 發明總結 如本發明，揭示用於形成雙層低介電質障礙層在銅導體 上之方法及所形成之結構。 在較佳具體實施例中，用於形成雙層低介電質障礙層在 銅導體上之方法可以藉由提供具有形成在絕緣體層中之銅 導體之預先處理底材；沈積包含磷或硼之金屬合金膜在該 銅導體頂部上；在降低氣體氣壓中將第一加熱處理之預先 處理底材加熱到至少300°C溫度一時間長度，以足夠於包含 磷或硼之金屬合金擴散至該銅導體頂部表面之至少2〜4原 子層中；沈積介電質膜在該包含磷或硼之金屬合金膜頂部 上；以及在降低氣體氣壓中將第二加熱處理之預先處理底 材加熱到至少300°C溫度至少1小時之操作步驟加以完成。 當制訂一降低氣體氣壓時，意義爲包含眞空、H2、形成氣 體以及惰性氣體氣壓。 另外，該二層（金屬及介電質）可以連續沈積，緊接著在 降低氣壓之400°C溫度單一回火步驟處理2小時。 在形成雙層低介電質障礙層在銅導體上之方法中，第一 加熱處理可以在至少325°C之溫度實行至少1小時。第二加 熱處理可以在至少350°C之溫度實行至少2小時。在第一及 第二加熱處理中使用之降低氣壓可以爲氫氣（N2 + H 2)氮氣 之形成氣體或是眞空。包含磷或棚之金屬合金膜之沈積處 理可以藉由無電電鍍技術加以實行。另外，亦可能藉由包 冬 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 裝--- (請先閱讀背面之注意事項再填寫本頁) . 476134 A7 B7_ 五、發明說明（6 ) 含磷或硼之第一金屬層合金膜之後續沈積而組合該二回火 程序爲單一回火程序，緊接著介電質膜之沈積以及在氮氣 或是包括形成氣體、H2、氮氣之降低氣壓或是眞空中在 400°C實行雙層之最終加熱2小時。該介電質膜可以藉由電 漿增強之化學汽相沈積技術沈積在包含磷或硼之金屬合金 膜上。該方法尚可以包含在沈積該包含嶙或硼之金屬合金 膜之步驟之前沈積鈀長晶層在預先處理底材上之步驟。該 包含磷或硼之金屬合金膜可以爲Me-X-P或是Me-X-B，其 中Me爲該合金膜主要成分以及X爲合金改性劑。 經濟部智慧財產局員工消費合作社印製 ，裝--- (請先閱讀背面之注意事項再填寫本頁) 用於形成雙層低介電質障礙層在銅導體上之方法尚可以 包含藉由利用硫酸之稀釋硫酸把溶液之選擇性離子交換方 法沈積鈀長晶層在該銅導體上之步驟。該包含磷或硼之金 屬合金膜尚可以包含介於大約8 6比重％與大約9 0比重％之 間之Me、介於大約2比重％與大約4比重％之間之X以及介 於大約6比重％與大約1 2比重％之間之P或是B。沈積之介 電質膜可以具有小於或是等於5之介電常數。該方法尚可以 包含沈積該包含磷或硼之金屬合金膜爲介於大約50 A與大 約300 A之間之厚度，以及較佳爲介於大約100 A與大約200 A之間之步驟。該方法尚可以包含藉由在介於大約70 °C與 大約80°C之間之溫度，在介於大約8與大約9之間之pH値 之包含硫酸鈷、鎢酸銨、擰檬酸鈉及硼酸之次磷酸鹽溶液 之無電沈積處理沈積該包含磷或硼之金屬合金膜之步驟。 該方法尚可以包含在介於大約325°C與大約400°C之間之溫 度實行第一加熱處理介於大約〇 · 5小時與大約2小時之間之 -9 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 屬 而 之 五、發明說明（7) 時間週期之步驟。該方法尚可以包含沈積選自包含Si、c 、〇、N及/或H之材料、包含Si、c、H、N及類似鑽石碳 之材料組成之群組之材料介電質膜之步驟。該方法尚可以 包含沈積該介電質膜爲介於大約1〇〇 A與大約5〇〇 A之間之 厚度，以及較佳爲介於大約25〇 A與大約35〇 A之間之步驟 。邊方法尚可以包含在介於大約35(rc與大約4〇〇β〇之間之 恤度實行第二加熱處理介於大約〗小時與大約5小時之間之 時間週期之步驟。該包含嶙或硼之金屬合金膜可以爲以卜 X-P或是Me-X-B ’其中Meg〇或是Ni ; 或是Sn。 本發明尚指7F半導體結構之電氣導體，包含位於絕緣體 層之金屬導體、在該金屬導體頂部上之包含鱗或刪之金屬 合金膜以及在該包含磷或硼之金屬合金膜頂部上之 材料膜。 在半導體結構之電氣導體中，該包含磷或硼之金屬合金 呈現至該金屬導體頂部表面之至少2〜4原子層中。該全 導體可以包含銅。該包含磷或硼之金屬合金可以爲Μ" MeUX-P或是ι·χ·Β之二元或是三元合金，476134 V. Description of the invention (4) Therefore, one object of the present invention is to provide a method for forming an obstruction layer on a copper conductor, which has no defects and shortcomings of the traditional copper barrier layer. Installation --- (Please read the precautions on the back before filling this page)-Another object of the present invention is to provide a method for reducing the thickness of the SiN cover and improving its attachment to copper. Another object of the present invention is to provide a method for forming a low dielectric barrier layer on a copper conductor to improve the diffusion barrier and adhesion properties. Another object of the present invention is to provide a method for forming a double-layer dielectric barrier layer on a copper conductor, in which a metal alloy film containing phosphorus or boron and a low-dielectric material containing Shi Xi are continuously deposited on the copper conductor. On top. Another object of the present invention is to provide a method for forming a double-layer dielectric barrier layer on a copper conductor by depositing two separate layers of an adhesion and diffusion barrier layer before tempering. Stomach Another object of the present invention is to provide a method for forming a double-layer dielectric barrier layer to be used as a dielectric or interconnected copper conductor in copper wire back-end processing. Another object of the present invention is to provide a method for forming a double-layer dielectric barrier layer on a copper conductor, wherein a deposition treatment of a metal alloy film containing phosphorus or boron is followed by a tempering treatment to diffuse the metal alloy to the Copper conductors are in at least 2-4 atomic layers. Produced by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another object of the present invention is to provide electrical conductors for semiconductor structures, including metal conductors, metal alloy films containing phosphorus or boron, and dielectric material films on top. % Another object of the present invention is to provide electrical conductors for semiconductor structures, in which the thickness is between 50 A and 200 A. A layer of a metal alloy containing phosphorus or boron is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 476134 A7 B7 5. Description of the Invention (5) The film is first deposited on a metal conductor, and a low-k dielectric material having a thickness between 100 A and 500 A is then deposited on top of the metal alloy film. Summary of the Invention According to the present invention, a method for forming a double-layered low-dielectric barrier layer on a copper conductor and the structure formed are disclosed. In a preferred embodiment, the method for forming a double-layered low-dielectric barrier layer on a copper conductor can be accomplished by providing a pre-treated substrate having a copper conductor formed in an insulator layer; depositing a substrate containing phosphorus or boron A metal alloy film is on top of the copper conductor; the first heat-treated pretreated substrate is heated to a temperature of at least 300 ° C for a length of time in a reduced gas pressure, enough to diffuse a metal alloy containing phosphorus or boron to the copper In at least 2 to 4 atomic layers on the top surface of the conductor; depositing a dielectric film on top of the metal alloy film containing phosphorus or boron; and heating the pre-treated substrate for the second heat treatment to at least 300 in a reduced gas pressure ° C temperature at least 1 hour to complete the operation steps. When formulating a reduced gas pressure, it means to include airspace, H2, gas formation, and inert gas pressure. In addition, the two layers (metal and dielectric) can be continuously deposited, followed by a single tempering step at a reduced temperature of 400 ° C for 2 hours. In the method of forming a double-layered low dielectric barrier layer on a copper conductor, the first heat treatment may be performed at a temperature of at least 325 ° C for at least 1 hour. The second heat treatment may be performed at a temperature of at least 350 ° C for at least 2 hours. The reduced air pressure used in the first and second heat treatment may be a formation gas of hydrogen (N 2 + H 2) nitrogen gas or emptied. The deposition process of a metal alloy film containing phosphorus or a shed can be performed by electroless plating technology. In addition, it is also possible to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) by the Bao Dong paper size. (Please read the precautions on the back before filling this page). 476134 A7 B7_ V. Description of the invention (6) The subsequent deposition of the first metal layer alloy film containing phosphorus or boron is combined with the two tempering procedures into a single tempering procedure, followed by the deposition of the dielectric film and the formation of nitrogen, or a gas, H2 2. Decrease the pressure of nitrogen or carry out double-layer final heating at 400 ° C for 2 hours. The dielectric film can be deposited on a metal alloy film containing phosphorus or boron by a plasma enhanced chemical vapor deposition technique. The method may further include the step of depositing a palladium crystal layer on a pre-treated substrate before the step of depositing the metal alloy film containing rhenium or boron. The metal alloy film containing phosphorus or boron may be Me-X-P or Me-X-B, where Me is a main component of the alloy film and X is an alloy modifier. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, installed --- (Please read the precautions on the back before filling this page) The method for forming a double-layer low-dielectric barrier layer on a copper conductor can also include A step of depositing a palladium crystal layer on the copper conductor by a selective ion exchange method of diluting sulfuric acid with a solution of sulfuric acid. The metal alloy film containing phosphorus or boron may further include Me between about 86% by weight and about 90% by weight, X between about 2% by weight and about 4% by weight, and about 6 P or B is between specific gravity% and about 12 specific gravity%. The deposited dielectric film may have a dielectric constant of 5 or less. The method may further include the step of depositing the metal alloy film containing phosphorus or boron to a thickness between about 50 A and about 300 A, and preferably between about 100 A and about 200 A. The method may further include the step of containing cobalt sulfate, ammonium tungstate, and sodium citrate at a temperature between about 70 ° C and about 80 ° C and at a pH between about 8 and about 9. And an electroless deposition treatment of a hypophosphate solution of boric acid to deposit the metal alloy film containing phosphorus or boron. The method may also include performing a first heat treatment at a temperature between about 325 ° C and about 400 ° C, and a temperature between about 0.5 hours and about 2 hours. (CNS) A4 specification (210 X 297 mm) The fifth is the description of the invention (7) The steps of the time cycle. The method may further include the step of depositing a dielectric film of a material selected from the group consisting of a material including Si, c, O, N, and / or H, a material including Si, c, H, N, and diamond-like carbon materials. The method may further include the step of depositing the dielectric film to a thickness between about 100 A and about 500 A, and preferably between about 25 A and about 35 A. The edge method may further include the step of performing a second heat treatment for a time period between about 35 hours and about 5 hours between about 35 ° rc and about 400 ° β. The method includes: The metal alloy film of boron can be made of XP or Me-XB, where Meg0 or Ni; or Sn. The present invention also refers to an electrical conductor of a 7F semiconductor structure, including a metal conductor located on an insulator layer, and the metal conductor. A metal alloy film containing scales or deletions on the top and a material film on top of the metal alloy film containing phosphorus or boron. In an electrical conductor of a semiconductor structure, the metal alloy containing phosphorus or boron appears to the top of the metal conductor At least 2 to 4 atomic layers on the surface. The full conductor may contain copper. The metal alloy containing phosphorus or boron may be a M " MeUX-P or ι · χ · Β binary or ternary alloy,
Me爲或是Ni以及uSi、w或是sn。該包含鱗或叙 金屬合金可以沈積爲介於大約1〇 A與大約1〇〇〇八之間之厚 度，以及較佳爲介於大約5〇 A與大約2〇〇 A之間之厚度。 Μ包含嶙或硼之金屬合金可以藉由無電電艘技術加以沈積 。該沈積之介電質材料可以選自包含Si、c、〇、^H之 材料組成之群組。該介電質材料可以沈積爲介於大約10 A 與大約5，_ A之間之厚度，以及較佳爲介於大約⑽入與 本紙張尺度適用中國國家標準（CNS)Ai^TilO X 297公ir 裝 訂---------. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -10- 經濟部智慧財產局員工消費合作社印製 476134 A7 B7_ 五、發明說明（8 ) 大約500 A之間之厚度。該半導體結構可以形成在選自矽、 矽鍺、絕緣體上矽以及砷化鎵組成之群組之底材上。 圖式之簡單説明 本發明這些目的、態樣以及優點依據規範及附圖考慮將 變成明顯，其中： 圖1爲形成在具有第二雙道鑲嵌法結構形成在頂部之雙道 鑲嵌法結構之銅導體上之本發明雙層低介電質障礙層之放 大橫截面圖； 圖2爲解釋形成在銅導體上之雙層擴散障礙/附著增強之 本發明另一具體實施例之放大橫截面圖； 圖3爲解釋多層障礙層測試結構之元素次要離子計數相依 性爲進入本發明結構中深度之函數圖。在此例子中，C 〇 -W-P膜爲300 A厚以及低k介電SiCOH膜在頂部上； 圖4爲解釋多層障礙層結構之種種不同元素次要離子計數 相依性爲進入本發明結構中深度之函數圖。在此例子中， CoSnP膜爲300 A厚以及在頂部上之低k介電SiCOH膜爲500 A厚，其中該金屬合金膜已經在350°C回火2小時； 圖5爲解釋在該結構上之附著測試結果以及具有金屬合金 膜在其之間之銅上氮化矽膜處理之相依性數據表；以及 圖6爲解釋在該結構上之附著測試結果以及SiCOH/櫬墊金 屬之雙層障礙層充填回火之相依性數據表。 較佳具體實施之詳細説明 本發明揭示一種藉由首先提供具有形成在絕緣層之銅導 體之預先處理底材，之後沈積包含磷或硼之金屬合金膜在 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Me is either Ni and uSi, w or sn. The scale-containing or alloy metal may be deposited to a thickness between about 10 A and about 1000 A, and preferably between about 50 A and about 2000 A. Metal alloys containing rhenium or boron can be deposited by electroless boat technology. The deposited dielectric material may be selected from the group consisting of materials including Si, c, O, and H. The dielectric material can be deposited to a thickness between about 10 A and about 5, _ A, and preferably between about 50 A and about 2,000 A. This paper size applies Chinese National Standard (CNS) Ai ^ TilO X 297 mm ir binding ---------. (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -10- Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476134 A7 B7_ 5. Description of the invention (8) Thickness between about 500 A. The semiconductor structure may be formed on a substrate selected from the group consisting of silicon, silicon germanium, silicon on insulator, and gallium arsenide. Brief description of the drawings These objects, aspects, and advantages of the present invention will become apparent in consideration of specifications and drawings. Among them: Figure 1 is a copper formed in a dual-channel mosaic structure with a second dual-channel mosaic structure formed on top. An enlarged cross-sectional view of a double-layer low-dielectric barrier layer of the present invention on a conductor; FIG. 2 is an enlarged cross-sectional view of another embodiment of the present invention explaining a double-layer diffusion barrier / adhesion enhancement formed on a copper conductor; FIG. 3 is a graph explaining the dependency of elemental secondary ion counts of the multilayer barrier test structure as a function of depth into the structure of the present invention. In this example, the Co-WP film is 300 A thick with a low-k dielectric SiCOH film on top; Figure 4 illustrates the dependency of the secondary ion count of various elements of the multilayer barrier structure on the depth of entry into the structure of the invention Function graph. In this example, the CoSnP film is 300 A thick and the low-k dielectric SiCOH film on the top is 500 A thick, where the metal alloy film has been tempered at 350 ° C for 2 hours; Figure 5 is explained on the structure The results of the adhesion test results and the dependence of the silicon nitride film treatment on the copper with the metal alloy film in between; and Figure 6 illustrates the adhesion test results on the structure and the double barrier of the SiCOH / pad metal The layers are filled with a dependency data table for tempering. Detailed description of the preferred embodiment The present invention discloses a method for providing a pre-treated substrate having a copper conductor formed on an insulating layer, and then depositing a metal alloy film containing phosphorus or boron. (CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 476134 A7 _B7_ 五、發明說明（9 ) 該銅導體頂部上、在降低氣體氣壓中將預先處理底材加熱 到至少300°C之溫度一時間長度，以足夠於該金屬合金擴散 至該銅導體表面層中、之後沈積介電質膜在該金屬合金膜 頂部上以及在降低氣體氣壓中將預先處理底材加熱到至少 3 00 °C溫度至少1小時時間週期而形成用於互連之雙層低介 電質障礙層之方法。 本發明尚揭示半導體結構之電氣導體，包含位於絕緣體 層之金屬導體、在該金屬導體頂部上之包含磷或硼之金屬 合金膜以及該包含磷或硼之金屬合金膜頂部上之介電質材 料膜。 在藉由本發明提供之方法或是裝置中，該包含磷或硼之 金屬合金膜可以藉由Me_X-P或是Me-X-B表示，其中Me 爲該合金膜主要成分以及X爲合金改性劑。M e可以爲C 〇或 是Ni以及X可以爲W或是Sn。P及B代表磷及硼。該包含磷 或硼之金屬合金尚可以包含介於大約8 6比重％與大約9 0比 重％之間之Me、介於大約2比重％與大約4比重％之間之X 以及介於大約6比重％與大約1 2比重％之間之P或是B。該 金屬合金膜沈積爲介於大約50 A與大約300 A之間之厚度。 在本發明新穎方法中利用之加熱處理或是回火處理對形 成之最終雙層介電質障礙層爲重要的。例如，在第一回火 處理中，該半導體底材加熱到至少300°C之溫度或是較佳爲 加熱至介於大約350°C與大約400°C之間之溫度一時間長度 ，以足夠於該含磷或硼之金屬合金擴散到至少表面層中， 亦即該銅導體之至少2〜4原子層中。該足夠時間長度可以 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476134 A7 _B7_ V. Description of the Invention (9) The copper conductor is heated on the top of the copper conductor to a temperature of at least 300 ° C for a period of time in a reduced gas pressure, which is sufficient After the metal alloy diffuses into the surface of the copper conductor, a dielectric film is deposited on top of the metal alloy film and the pre-treated substrate is heated to a temperature of at least 300 ° C for at least 1 hour in a reduced gas pressure for a period of time A method of forming a two-layer low-dielectric barrier layer for interconnection. The invention also discloses an electrical conductor of a semiconductor structure, comprising a metal conductor on an insulator layer, a metal alloy film containing phosphorus or boron on top of the metal conductor, and a dielectric material on top of the metal alloy film containing phosphorus or boron. membrane. In the method or device provided by the present invention, the metal alloy film containing phosphorus or boron may be represented by Me_X-P or Me-X-B, where Me is a main component of the alloy film and X is an alloy modifier. Me can be Co or Ni and X can be W or Sn. P and B represent phosphorus and boron. The metal alloy containing phosphorus or boron may further include Me between approximately 86% by weight and approximately 90% by weight, X between approximately 2% by weight and approximately 4% by weight, and approximately 6 by weight. P or B between% and about 12% by weight. The metal alloy film is deposited to a thickness between about 50 A and about 300 A. The heat treatment or tempering treatment used in the novel method of the present invention is important to the final double-layer dielectric barrier layer formed. For example, in the first tempering process, the semiconductor substrate is heated to a temperature of at least 300 ° C or preferably to a temperature between about 350 ° C and about 400 ° C for a period of time, which is sufficient The metal alloy containing phosphorus or boron diffuses into at least the surface layer, that is, at least 2 to 4 atomic layers of the copper conductor. The sufficient time can be -12- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 A7 ----— B7 _ 五、發明說明（1〇) 爲介於大約0.5小時與大約2小時之間。第二回火處理，在 ，介電質障礙層沈積之後實行，可以在至少3〇(rc之溫度或 是較佳爲大約350。〇與大約40(rc之間之溫度實行介於大約！ 小時與大約5小時之間之時間週期。或是，二回火步驟可以 在降低氣壓中之4〇〇。(：藉由加熱該雙層2小時而組合爲單一 步驟。 忑介％貝層可以由如包含Si、C、〇、1^及/或11之材料沈 積。該沈積之介電膜厚度爲介於大約1〇〇人與大約5〇〇入之 間，以及車父佳爲介於大約i〇〇 A與大約3A之間。 t發明新禎方法组合無電電鍍金屬膜與連續沈積至抛光（ 如精由化學機械研磨）銅/介電質頂部表面之低k(介電常數） 介電質覆蓋層膜以產生雙層障礙層。該雙層障礙層呈現銅 擴散障礙層所需性質、銅之良好附著、低介電常數，而維 持次上階層介電質之反應性離子_(RIE)停止效能。本發 明雙層障礙層〈額外利益爲該介電質覆蓋層厚度之最小化 ，通常減低該互連結構之有效介電常數以及提#已經顯示 將電性遷移最小化之導體冗餘性。 本發明雙層障礙層之結構可以藉由下列處理形成。以平 坦化結構開始，該結構包括嵌入在介電質内之銅線，而銅 表面在介電質層中顯露。在第一步驟中，具有銅表面強烈 附著之金屬覆蓋層之自我對準選擇性應用爲執行以形成金 屬至金屬焊接。該金屬覆蓋層具有介於大約1〇〇 A與大約 400 A之間之厚纟，因此提供較大電氣可靠度以及改/良之電 性遷移阻抗。該金屬覆蓋層尚提供在封閉空隙及小丘能: ^1 --- (請先閱讀背面之注意事項再填寫本頁) .Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ---- B7 _ V. The description of the invention (10) is between about 0.5 hours and about 2 hours. The second tempering treatment, which is performed after the dielectric barrier layer is deposited, may be performed at a temperature of at least 30 ° C or preferably about 350 ° C and about 40 ° C. And a time period between about 5 hours. Alternatively, the two tempering steps can be performed at a reduced air pressure of 400. (: Combined into a single step by heating the double layer for 2 hours. Such as Si, C, 0, 1 ^ and / or 11 material deposition. The thickness of the deposited dielectric film is between about 100 people and about 5,000, and the car is preferably between about 〇〇A and about 3A. Invented a new method to combine the electroless plating metal film and continuous deposition (such as fine chemical mechanical polishing) copper / dielectric top surface low k (dielectric constant) dielectric Layer to produce a double-layer barrier layer. The double-layer barrier layer exhibits the properties required for a copper diffusion barrier layer, good copper adhesion, and low dielectric constant, while maintaining reactive ions of the next-level dielectrics_ (RIE ) Stop efficiency. The double-layer barrier layer of the present invention (the additional benefit is the dielectric cover layer) The minimization of the thickness usually reduces the effective dielectric constant of the interconnect structure and the increase in conductor redundancy that has been shown to minimize electrical migration. The double barrier structure of the present invention can be formed by the following processes. Flat Beginning of the structure, the structure includes copper wires embedded in the dielectric, and the copper surface is exposed in the dielectric layer. In the first step, a self-aligned selective application of a metal cap layer with a strong copper surface adhesion To perform metal-to-metal welding. The metal cover has a thickness between about 100 A and about 400 A, thus providing greater electrical reliability and improved electrical migration resistance. The metal cover The layer is still available in closed gaps and humps: ^ 1 --- (Please read the precautions on the back before filling this page).
經濟部智慧財產局員工消費合作社印製 476134 五、發明說明（11 中具有較大穩足性之銅表面。在第一回火或是加熱處理實 行之後，該處理在稍後章節中必須更詳細説明，執行毯覆 =1包負覆盍層i第二沈積處理。該毯覆性介電質覆蓋層 最佳方式爲由非常低介電常數材料如包含si、c、〇、 /^Η之材料或是包含Si、c、H、N以及類似鑽石碳之材料 氣備或疋，亦可以使用SiN，然而，較正常需要之厚度更 縮減之厚度爲單一層障礙層。 由選擇性鈷基之擦電處理製備之雙層覆蓋層獲得之結果 ，特別爲Co_W-P但是不限於c〇_w_p，盥已經顧示 良好附著與達成之Cu敎性以及以擴散控制之_、sicH 或是SiCOH膜組合。 形成用於擴散障礙層及附著之本發明雙層覆蓋層之化學 步驟可以更詳細説明如下：本發明新類方法之整體目的爲 在CMP處理之後建立雙層金屬/介電質膜在銅表面上。沈積 在銅表面上之第一步驟中，金屬膜藉由厚度介於大約i〇〇 A 與· A之間之-層之無電電鍍達成之選擇性沈積加以沈積 。孩層爲藉由具有Me-X-P之一般結構之合金形成，並中 Me代表該合金膜主要成分，χ爲合金改性劑；給予該膜對 銅增加附著之非常特定性質以及擴散障礙層性質，以及？代 表在膜形成處理期間共沈澱之特定量磷。在本發明較佳具 體實施例中，X選擇爲3至5%原子W，而ρ爲合金膜之了至 9°/〇原子等級。 在本發明處理之第二步驟中，該銅結構在降低氣愿，例 如形成氣體或是氫氣在3 5 0 以頂部合金膜回火至少2小時 Μ氏張尺度適用中國國家標準（CNS)A4規格（210 χ 297公髮） (請先閱讀背面之注意事項再填寫本頁) 裝 .. -14 - 經濟部智慧財產局員工消費合作社印製 476134 A7 B7__ 五、發明說明（12) 。該溫度處理允許該合金成分緊密交融以及在一些原子層 中擴散至該銅表面中以提供化學及金屬壓焊以及與銅形成 優等附著。或是，該回火步驟可以在介電質沈積期間或是 之後加以執行。 在本發明處理之第三步驟中，該介電質膜加在該金屬膜 頂部以形成雙層結構。此情形通常藉由電漿增強之化學汽 相沈積（PECVD)處理完成。在該處理中，該介電質材料沈 積在之前沈積在該銅上之Me-X-P層之上，以及通常爲介 於100 A與大約500 A之間之厚度。已經發現較佳介電質膜 爲那些基於矽化合物如SiCOH、SiCH或是SiN之膜。低介電 常數材料如類似鑽石碳（DLC)亦可以使用。較佳介電質材 料爲SiCOH，因爲展現最低介電常數。 在本發明處理之第四步驟中，一回火處理在氫氣、氮氣 或是形成氣體之降低氣壓之至少300°C溫度應用至雙層至少 2小時。此最終回火處理移除金屬覆蓋/介電質介面有機雜 質以及可能其他揮發性產物，那些雜質及揮發性產物減損 達成良好附著性質。 藉由本發明處理之種種不同化學步驟形成之最終結構顯 示在圖1中。圖1解釋具有本發明第一較佳具體實施例併入 之雙道鑲嵌法互連結構10放大之橫截面圖。該結構10顯示 具有二介電質互連階層20及30，包含介質22，32以及渠 溝2 4，3 4。該結構建立在具有作用裝置1 4形成在頂部表面 16之半導體底材12上。在該底材12上，第一介電質層18 爲沈積以及以介質3 2之開口以及渠溝3 4之開口加以圖案化 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 .. 476134 A7 B7__ 五、發明說明（13) 。戒介質及渠溝開口之後與櫬墊對齊，亦即，障礙層3 6以 金屬3 8充填，以及藉由化學機械研磨方法加以平坦化以在 該渠溝3 4上達成平坦化頂部表面4 〇。 在結合本發明新穎方法之該處理之次步驟中，c 〇 _ w _ p 之無電沈積覆蓋層44之應用選擇性地只沈積在該金屬渠溝 34頂部上。該覆蓋層44防止金屬3 8往外擴散至該介電質層 5〇中以及由於連續處理而防止渠溝34污染。該金屬層44以 選擇性介電質覆蓋層5 2使用爲在後續處理期間或是在半導 月豆裝置操作期間將渠溝金屬由任何相互作用隔離之主要震 置。該選擇性介電質覆蓋層52可用以更進一步改良Co_w_ P金屬合金層40之障礙層性質或是使用爲集成增強層如反 應性離子蝕刻（RIE)停止層。第二介電質層5〇，如圖1所示 ，在RIE處理之後用以形成介質22及渠溝24之雙道鑲嵌法 凹洞。在此案例中，該介電質覆蓋層5 2使用爲RIE停止。 當其使用時’該RIE停止層5 2爲蚀刻以在以櫬螯層3 6開始 之處理中開啓至第二階層渠溝2 4，該處理爲重複直到獲得 需要數目之互連階層爲止。 經濟部智慧財產局員工消費合作社印製 -I --- (請先閱讀背面之注咅？事項再填寫本頁>> 圖2爲使用於附著測試以及具有本發明雙層障礙層形成在 頂邵上之擴散障礙層效能之銅測試工具放大橫截面圖。明 白在該矽底材1 2頂部上爲首先沈積包含大約80〇 A厚之金 屬櫬墊層之障礙層36。2,000 A厚之銅導體38之後濺鍍沈 積在該櫬墊層36頂部上。沈積之該無電金屬覆蓋層44可以 爲具有介於300 A與500 A之間之厚度之Co-W-P或是Co-Sn-P層。具有500 A厚度之SiCOH之低k介電質層52之後沈 -16 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 476134 A7 B7_ 五、發明說明（14) 積在頂部上。爲增強SIMS訊號，一層類似鑽石碳5 4沈積在 該3丨(3011層5 2頂部上。 圖3及圖4解釋在圖2顯示之結構上獲得之SIMS/繪圖。如 圖3及圖4所見，當只有300 A厚之Co_W_P或是Co_Sn-P 之無電沈積金屬層以及500 A厚之SiCOH層沈積時，在回火 之後將提升銅擴散以橫跨至金屬層之表面層而至SiCOH中 ，該銅完全保持在該無電沈積金屬合金層44之後以及之下 以及不穿透該層44而至該介電質層52中。這些結果指示本 發明結構停止該銅遷移以及因爲橫跨該SiCOH層5 2之氧分 子之銅潛在氧化效應，至少在熱能量之下。所以，顯示之 結構爲銅及氧原子熱遷移停止物之有效系統。 圖5爲解釋依據利用之間之種種不同金屬合金膜之介於銅 導體與SiN介電質層之間之附著力獲得之數據表。顯示銅附 著至氮化矽與在氮化物應用之前之銅表面預先處理強烈相 關。最佳結果爲藉由使用Co-W-P内層、Co-Sn-P内層、 以及高密度電漿（HDP)沈積氮化物而獲得。圖5之表中指示 之附著力以單位Mpa X m 1 /2顯示。 具有無電沈積覆蓋層在具有SiCOH介電質層之銅上之雙層 覆蓋層之附著測試結果顯示在圖6中。6個取樣爲以S i -Si02/櫬墊金屬/Cu(2,000 A)執行。該些取樣以Co-W-P、 Co-P以及Co-Sn-P其中之一無電電鍍。該些取樣接著以工 具執行，其中500 A之SiCOH介電質材料爲應用在該覆蓋層 表面之上。某些取樣在無電沈積處理之後以及在SiCOH沈 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 厂裝--- (請先閱讀背面之注意事項再填寫本頁) .. 經濟部智慧財產局員工消費合作社印製 476134 A7 B7 五、發明說明（15) 積之後加熱回火，而其他只在SiCOH之後。圖6顯示之結果 指示該Co-W-P產生最佳附著値。 圖6顯示之取樣尚藉由SIMS分析加以測試以供檢查跨越該 Co-W-P膜之加熱銅遷移。該SIMS資料指示銅保持在覆蓋 層之後以及如預測不遷移至介電質層。 測試結果發現藉由使用Co-W-P内層之介電質SiCOH至 Cu之增加附著顯示在圖6中。已經發現介電質SiCOH層附著 至銅可以在介電質應用之後藉由使用降低氣壓預先處理而 顯著地增加。最佳結果爲在SiCOH沈積之後藉由使用Co-W-P覆蓋層以及在形成氣體中以350°C回火至少2小時而獲 得。這些取樣在正確介面顯現爲衰減，亦即，SiCOH至無 電沈積層，與當附著，回火膜正衰減至銅層之下時在 SiCOH之後該系統不回火時相反。 所以，本發明新穎方法及藉由該方法形成之裝置已經在 上述説明以及附圖1至6中詳細説明。已經顯示低k介電質 材料單一使用之技術議題及問題爲由於該SiCOH對銅沒有 良好附著以及SiCOH對氧有某種程度之滲透性。這些二因 素因此結合造成銅氧化以及在介電質/銅之介面上分層，結 果造成可靠度問題。所以，本發明新穎方法利用雙層障礙 層，例如，Cu/Co-W-P/SiCOH 以及 Cu/Co-Sn-P/SiCOH，所以 銅不移動經過金屬合金之無電沈積覆蓋層之層以及保持在 其之後，縱使在380°C回火2小時之後。 雖然本發明已經以解釋性方式説明，但是必須瞭解所使 用之術語意圖爲説明文字特性而非限制。 -18- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ"裝—— (請先閱讀背面之注意事項再填寫本頁) ·. 經濟部智慧財產局員工消費合作社却製 476134 A7 B7 五、發明說明（16) 此外，雖然本發明已經以較佳及替代方案具體實施例加 以説明，但是將體會那些熟知相關技藝之人士將容易地應 用這些技術至本發明其他可能變化。 本發明具體實施例之宣稱獨有性質或是特殊利益定義如 下。 -19 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs 476134 V. Description of the invention (11 copper surface with greater stability. After the first tempering or heating treatment is implemented, this treatment must be described in more detail in a later section It is illustrated that the blanket deposition = the second deposition process of the negative coating layer i is performed. The best way to cover the blanket dielectric coating layer is to use a very low dielectric constant material such as si, c, 〇, / ^ Η The material is Si, c, H, N, and diamond-like carbon or gas-filled materials. SiN can also be used. However, the thickness that is more reduced than the normal thickness is a single barrier layer. The results obtained by the double-layer coating prepared by the rubbing treatment, especially Co_W-P but not limited to c0_w_p, have been shown to have good adhesion and achieved Cu properties and diffusion controlled _, sicH or SiCOH film The chemical steps of forming the double-layered cover layer of the present invention for diffusion barrier layer and adhesion can be explained in more detail as follows: The overall purpose of the new method of the present invention is to establish a double-layered metal / dielectric film on copper after CMP treatment. On the surface. In the first step on the copper surface, the metal film is deposited by selective deposition achieved by electroless plating with a thickness of between -100A and · A. The layer is formed by having Me-XP The general structure of the alloy is formed, and Me represents the main component of the alloy film, χ is an alloy modifier; the film is given a very specific property to increase the adhesion to copper and the properties of the diffusion barrier layer, and? A specific amount of phosphorus precipitated. In a preferred embodiment of the present invention, X is selected to be 3 to 5% atomic W, and ρ is an alloy film to 9 ° / 0 atomic level. In the second step of the process of the present invention The copper structure is reducing gas hopes, such as forming a gas or hydrogen, and tempering the top alloy film at 3 50 for at least 2 hours. The M-scale is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297). (Please Please read the notes on the back before filling this page.) Packing .. -14-Printed by the Intellectual Property Bureau of the Ministry of Economy, Employees' Cooperatives, printed 476134 A7 B7__ V. Description of the invention (12). This temperature treatment allows the alloy components to blend tightly and in some cases atom It diffuses into the copper surface to provide chemical and metal pressure welding and to form superior adhesion to copper. Alternatively, the tempering step can be performed during or after dielectric deposition. In the third step of the process of the present invention The dielectric film is added on top of the metal film to form a double-layer structure. This situation is usually accomplished by a plasma enhanced chemical vapor deposition (PECVD) process. In this process, the dielectric material is deposited before Deposited on top of the Me-XP layer on the copper, and usually between 100 A and about 500 A in thickness. Preferred dielectric films have been found to be those based on silicon compounds such as SiCOH, SiCH or SiN membrane. Low dielectric constant materials such as diamond-like carbon (DLC) can also be used. A preferred dielectric material is SiCOH because it exhibits the lowest dielectric constant. In the fourth step of the treatment of the present invention, a tempering treatment is applied to the double layer for at least 300 hours at a temperature of at least 300 ° C, which is a reduced pressure of hydrogen, nitrogen, or a forming gas. This final tempering process removes metal overlay / dielectric interface organic impurities and possibly other volatile products, those impurities and volatile products are reduced to achieve good adhesion properties. The final structure formed by the various chemical steps treated by the present invention is shown in FIG. FIG. 1 illustrates an enlarged cross-sectional view of a dual-channel mosaic interconnect structure 10 incorporating a first preferred embodiment of the present invention. The structure 10 is shown having two dielectric interconnect levels 20 and 30, including dielectrics 22, 32 and trenches 24, 34. This structure is built on the semiconductor substrate 12 having the action means 14 formed on the top surface 16. On the substrate 12, the first dielectric layer 18 is deposited and patterned with the openings of the dielectric 32 and the openings of the trenches 34-15-This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Installation: 476134 A7 B7__ 5. Description of the invention (13). After the opening of the medium and the trench is aligned with the pad, that is, the barrier layer 36 is filled with metal 38, and planarized by a chemical mechanical polishing method to achieve a flat top surface 4 on the trench 34. . In a second step of this process in combination with the novel method of the present invention, the application of the electrolessly deposited capping layer 44 of c0_w_p is selectively deposited only on top of the metal trench 34. The cover layer 44 prevents the metal 38 from diffusing out into the dielectric layer 50 and prevents contamination of the trench 34 due to continuous processing. This metal layer 44 is used as a selective dielectric cover layer 52 as the primary shock source that isolates the trench metal from any interaction during subsequent processing or during operation of the semiconducting moon bean device. The selective dielectric covering layer 52 can be used to further improve the barrier layer properties of the Co_w_P metal alloy layer 40 or can be used as an integrated enhancement layer such as a reactive ion etching (RIE) stop layer. The second dielectric layer 50, as shown in FIG. 1, is used to form a dual-channel mosaic method of pits in the dielectric 22 and the trench 24 after the RIE process. In this case, the dielectric cover layer 52 is used as RIE stop. When it is used, the RIE stop layer 5 2 is etched to be opened to the second level trench 24 in the process starting with the chelate layer 36, and the process is repeated until the required number of interconnect levels are obtained. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives -I --- (Please read the note on the back? Matters before filling out this page > > Figure 2 is used for adhesion testing and has a double barrier layer formed according to the present invention. An enlarged cross-sectional view of a copper test tool for the effectiveness of the diffusion barrier layer on top. It is understood that on the top of the silicon substrate 12 is a barrier layer 36, which is composed of a metal halide layer of about 80 A thick, and a thickness of 2,000 A thick. A copper conductor 38 is then sputter deposited on top of the sacrificial pad layer 36. The electroless metal capping layer 44 deposited may be a Co-WP or Co-Sn-P layer having a thickness between 300 A and 500 A .The low-k dielectric layer of SiCOH with a thickness of 500 A is 52 to 16-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476134 A7 B7_ V. Description of the invention (14) is deposited on the top. To enhance the SIMS signal, a layer of diamond-like carbon 5 4 is deposited on top of the 3 丨 (3011 layer 5 2). Figures 3 and 4 explain the structure shown in Figure 2 The SIMS / drawings obtained above. As seen in Figure 3 and Figure 4, when only 300 A thick When the Co_W_P or Co_Sn-P electrolessly deposited metal layer and the 500 A thick SiCOH layer are deposited, after tempering, the copper is promoted to diffuse across the surface layer of the metal layer and into the SiCOH, and the copper remains completely in the electroless After deposition of the metal alloy layer 44 and below and without penetrating the layer 44 into the dielectric layer 52. These results indicate that the structure of the present invention stops the copper migration and because of the copper of oxygen molecules across the SiCOH layer 52 The potential oxidation effect is at least under thermal energy. Therefore, the structure shown is an effective system for copper and oxygen atom thermal migration stoppers. Figure 5 is an explanation of the use of various metal alloy films between copper conductors and SiN Data sheet obtained from the adhesion between the dielectric layers. It shows that the adhesion of copper to silicon nitride is strongly related to the pre-treatment of the copper surface before nitride application. The best result is by using Co-WP inner layer, Co-Sn -P inner layer, and high-density plasma (HDP) deposited nitride. Adhesion indicated in the table of Figure 5 is shown in units of Mpa X m 1/2. With an electrolessly deposited cover layer in a layer with a SiCOH dielectric layer Double on Copper The results of the coating adhesion test are shown in Figure 6. Six samples were performed with S i -Si02 / Small metal / Cu (2,000 A). These samples were Co-WP, Co-P, and Co-Sn-P One of them was electrolessly plated. These samplings were then performed using tools, of which 500 A of SiCOH dielectric material was applied on the surface of the cover. Some of the samples were after electroless deposition and after SiCOH precipitation Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) Factory-installed (Please read the precautions on the back before filling out this page) .. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 476134 A7 B7 5. Description of the invention (15) After the product is heated and tempered, the others are only after the SiCOH. The results shown in Figure 6 indicate that the Co-W-P produced the best adhesion. The sampling shown in Figure 6 was also tested by SIMS analysis to check for heated copper migration across the Co-W-P film. The SIMS data indicates that the copper remains behind the cover layer and does not migrate to the dielectric layer as predicted. The test results found that the increased adhesion by using the dielectric SiCOH of the Co-W-P inner layer to Cu is shown in FIG. 6. It has been found that the adhesion of a dielectric SiCOH layer to copper can be significantly increased after dielectric applications by pre-treatment using a reduced gas pressure. The best results are obtained after the SiCOH deposition by using a Co-W-P cap layer and tempering at 350 ° C for at least 2 hours in the formation gas. These samples appear attenuated at the correct interface, that is, SiCOH to the electrolessly deposited layer, as opposed to when the system is not tempered after SiCOH when the tempered film is attenuated below the copper layer when attached. Therefore, the novel method of the present invention and the device formed by the method have been described in detail in the above description and in Figs. It has been shown that technical issues and problems with the single use of low-k dielectric materials are due to the SiCOH's poor adhesion to copper and the SiCOH's permeability to oxygen to some extent. These two factors combine to cause copper oxidation and delamination on the dielectric / copper interface, resulting in reliability issues. Therefore, the novel method of the present invention utilizes two-layer barrier layers, such as Cu / Co-WP / SiCOH and Cu / Co-Sn-P / SiCOH, so that copper does not move through the layer of the electrolessly deposited cover layer of the metal alloy and remains there After that, even after tempering at 380 ° C for 2 hours. Although the invention has been explained in an explanatory manner, it must be understood that the terminology used is intended to be illustrative in nature and not restrictive. -18- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) Γ " Packing-(Please read the precautions on the back before filling this page) · Employee Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 476134 A7 B7 V. Description of the Invention (16) In addition, although the present invention has been described with preferred and alternative embodiments, those skilled in the art will readily apply these techniques to other possibilities of the present invention. Variety. The claimed unique properties or special benefits of specific embodiments of the present invention are defined as follows. -19-This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)