EP2433303A4 - Structure and method of forming electrically blown metal fuses for integrated circuits - Google Patents
Structure and method of forming electrically blown metal fuses for integrated circuitsInfo
- Publication number
- EP2433303A4 EP2433303A4 EP09845033.1A EP09845033A EP2433303A4 EP 2433303 A4 EP2433303 A4 EP 2433303A4 EP 09845033 A EP09845033 A EP 09845033A EP 2433303 A4 EP2433303 A4 EP 2433303A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- integrated circuits
- forming electrically
- metal fuses
- blown metal
- electrically blown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2009/044952 WO2010134922A1 (en) | 2009-05-22 | 2009-05-22 | Structure and method of forming electrically blown metal fuses for integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2433303A1 EP2433303A1 (en) | 2012-03-28 |
EP2433303A4 true EP2433303A4 (en) | 2014-09-17 |
Family
ID=43126415
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP09845033.1A Withdrawn EP2433303A4 (en) | 2009-05-22 | 2009-05-22 | Structure and method of forming electrically blown metal fuses for integrated circuits |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP2433303A4 (en) |
JP (1) | JP2012527768A (en) |
CN (1) | CN102428563B (en) |
WO (1) | WO2010134922A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104835800B (en) * | 2014-02-08 | 2019-01-22 | 北大方正集团有限公司 | A kind of fuse-wires structure and its manufacturing method of integrated circuit |
CN108666262B (en) * | 2017-03-31 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Fuse structure circuit and forming method thereof |
US11756882B2 (en) | 2020-12-31 | 2023-09-12 | Texas Instruments Incorporated | Semiconductor die with blast shielding |
US11935844B2 (en) | 2020-12-31 | 2024-03-19 | Texas Instruments Incorporated | Semiconductor device and method of the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080079113A1 (en) * | 2006-10-03 | 2008-04-03 | International Business Machines Corporation | Fuse structure including cavity and methods for fabrication thereof |
US20080099889A1 (en) * | 2006-10-26 | 2008-05-01 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
US20090042341A1 (en) * | 2007-08-08 | 2009-02-12 | International Business Machines Corporation | Electrical fuse with a thinned fuselink middle portion |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0969607A (en) * | 1995-09-01 | 1997-03-11 | Sony Corp | Semiconductor device and its manufacturing method |
TW476134B (en) * | 2000-02-22 | 2002-02-11 | Ibm | Method for forming dual-layer low dielectric barrier for interconnects and device formed |
US6603321B2 (en) | 2001-10-26 | 2003-08-05 | International Business Machines Corporation | Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring |
JP2007184347A (en) * | 2006-01-05 | 2007-07-19 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
JP4959267B2 (en) * | 2006-03-07 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | Method for increasing resistance value of semiconductor device and electric fuse |
JP4861051B2 (en) * | 2006-05-09 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and electrical fuse cutting method |
-
2009
- 2009-05-22 WO PCT/US2009/044952 patent/WO2010134922A1/en active Application Filing
- 2009-05-22 JP JP2012511797A patent/JP2012527768A/en active Pending
- 2009-05-22 CN CN200980159306.9A patent/CN102428563B/en not_active Expired - Fee Related
- 2009-05-22 EP EP09845033.1A patent/EP2433303A4/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080079113A1 (en) * | 2006-10-03 | 2008-04-03 | International Business Machines Corporation | Fuse structure including cavity and methods for fabrication thereof |
US20080099889A1 (en) * | 2006-10-26 | 2008-05-01 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
US20090042341A1 (en) * | 2007-08-08 | 2009-02-12 | International Business Machines Corporation | Electrical fuse with a thinned fuselink middle portion |
Non-Patent Citations (1)
Title |
---|
See also references of WO2010134922A1 * |
Also Published As
Publication number | Publication date |
---|---|
CN102428563B (en) | 2014-06-11 |
JP2012527768A (en) | 2012-11-08 |
WO2010134922A1 (en) | 2010-11-25 |
EP2433303A1 (en) | 2012-03-28 |
CN102428563A (en) | 2012-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20101216 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK TR |
|
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20140819 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 23/525 20060101AFI20140812BHEP |
|
17Q | First examination report despatched |
Effective date: 20161012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20181201 |