EP2433303A4 - Structure et procédé de formation de fusibles métalliques grillés électriquement pour des circuits intégrés - Google Patents

Structure et procédé de formation de fusibles métalliques grillés électriquement pour des circuits intégrés

Info

Publication number
EP2433303A4
EP2433303A4 EP09845033.1A EP09845033A EP2433303A4 EP 2433303 A4 EP2433303 A4 EP 2433303A4 EP 09845033 A EP09845033 A EP 09845033A EP 2433303 A4 EP2433303 A4 EP 2433303A4
Authority
EP
European Patent Office
Prior art keywords
integrated circuits
forming electrically
metal fuses
blown metal
electrically blown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09845033.1A
Other languages
German (de)
English (en)
Other versions
EP2433303A1 (fr
Inventor
Ronald Filippi
Theodorus E Standaert
Stephan Grunow
Sujatha Sankaran
Kaushik Chanda
Jeffrey P Gambino
Andrew H Simon
Chao-Kun Hu
Griselda Bonilla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP2433303A1 publication Critical patent/EP2433303A1/fr
Publication of EP2433303A4 publication Critical patent/EP2433303A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP09845033.1A 2009-05-22 2009-05-22 Structure et procédé de formation de fusibles métalliques grillés électriquement pour des circuits intégrés Withdrawn EP2433303A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2009/044952 WO2010134922A1 (fr) 2009-05-22 2009-05-22 Structure et procédé de formation de fusibles métalliques grillés électriquement pour des circuits intégrés

Publications (2)

Publication Number Publication Date
EP2433303A1 EP2433303A1 (fr) 2012-03-28
EP2433303A4 true EP2433303A4 (fr) 2014-09-17

Family

ID=43126415

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09845033.1A Withdrawn EP2433303A4 (fr) 2009-05-22 2009-05-22 Structure et procédé de formation de fusibles métalliques grillés électriquement pour des circuits intégrés

Country Status (4)

Country Link
EP (1) EP2433303A4 (fr)
JP (1) JP2012527768A (fr)
CN (1) CN102428563B (fr)
WO (1) WO2010134922A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104835800B (zh) * 2014-02-08 2019-01-22 北大方正集团有限公司 一种集成电路的熔丝结构及其制造方法
CN108666262B (zh) * 2017-03-31 2021-02-02 中芯国际集成电路制造(上海)有限公司 熔丝结构电路及其形成方法
US11756882B2 (en) 2020-12-31 2023-09-12 Texas Instruments Incorporated Semiconductor die with blast shielding
US11935844B2 (en) 2020-12-31 2024-03-19 Texas Instruments Incorporated Semiconductor device and method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079113A1 (en) * 2006-10-03 2008-04-03 International Business Machines Corporation Fuse structure including cavity and methods for fabrication thereof
US20080099889A1 (en) * 2006-10-26 2008-05-01 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090042341A1 (en) * 2007-08-08 2009-02-12 International Business Machines Corporation Electrical fuse with a thinned fuselink middle portion

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0969607A (ja) * 1995-09-01 1997-03-11 Sony Corp 半導体装置およびその製造方法
TW476134B (en) * 2000-02-22 2002-02-11 Ibm Method for forming dual-layer low dielectric barrier for interconnects and device formed
US6603321B2 (en) 2001-10-26 2003-08-05 International Business Machines Corporation Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring
JP2007184347A (ja) * 2006-01-05 2007-07-19 Renesas Technology Corp 半導体装置およびその製造方法
JP4959267B2 (ja) * 2006-03-07 2012-06-20 ルネサスエレクトロニクス株式会社 半導体装置および電気ヒューズの抵抗値の増加方法
JP4861051B2 (ja) * 2006-05-09 2012-01-25 ルネサスエレクトロニクス株式会社 半導体装置および電気ヒューズの切断方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079113A1 (en) * 2006-10-03 2008-04-03 International Business Machines Corporation Fuse structure including cavity and methods for fabrication thereof
US20080099889A1 (en) * 2006-10-26 2008-05-01 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090042341A1 (en) * 2007-08-08 2009-02-12 International Business Machines Corporation Electrical fuse with a thinned fuselink middle portion

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010134922A1 *

Also Published As

Publication number Publication date
WO2010134922A1 (fr) 2010-11-25
JP2012527768A (ja) 2012-11-08
CN102428563B (zh) 2014-06-11
CN102428563A (zh) 2012-04-25
EP2433303A1 (fr) 2012-03-28

Similar Documents

Publication Publication Date Title
GB2488265B (en) Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
TWI369771B (en) Leadless integrated circuit package having high density contacts and manufacturing method
TWI370473B (en) Switch structure mounted on the sidewall of circuit boards for electronic devices and manufacturing methods of the circuit boards thereof
EP2554693A4 (fr) Alliage de cuivre contenant cu-ni-si-co pour un matériau électronique et procédé de fabrication de ce dernier
EP2430466A4 (fr) Identification de circuits intégrés
EP2437879A4 (fr) Microparticules multiphase et leur procede de fabrication
PL2480052T3 (pl) Ceramiczna płytka drukowana oraz sposób jej wytwarzania
EP2395541A4 (fr) Motif conducteur et procédé de fabrication correspondant
GB0805021D0 (en) Apparatus and method for electronic circuit manufacture
EP2438610A4 (fr) Processus et structure d'encapsulation pour dispositifs electroniques
HK1146330A1 (en) Semiconductor component and method of manufacture
SG10201402096TA (en) Resist stripping compositions and methods for manufacturing electrical devices
TWI365391B (en) Circuit layout method and layout circuit
EP2475231A4 (fr) Procédé de fabrication d'une carte de circuits et carte de circuits
HK1141138A1 (zh) 半導體元件及製造方法
IL215954A0 (en) Resist stripping compositions and methods for manufacturing electrical devices
GB201119495D0 (en) Integrated circuit package having security feature and method of manufacturing same
EP2384101A4 (fr) Film de cuivre enroulé ou film de cuivre électrolytique pour circuit électronique, et procédé pour la formation de circuit électronique utilisant un tel film
EP2311078A4 (fr) Circuit intégré à motifs et procédé de production de celui-ci
PL2333122T3 (pl) Stop aluminium i metoda jego produkcji
EP2479297A4 (fr) Fil en alliage de cuivre et procédé de fabrication associé
HK1131696A1 (en) Semiconductor component and method of manufacture
HK1125739A1 (en) Semiconductor component and method of manufacture
GB201208342D0 (en) Microelectronic package and method of manufacturing same
EP2260968A4 (fr) Procédé et appareil de production d'étain ou d'un alliage de soudage pour des composants électroniques et alliage de soudage

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20101216

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20140819

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 23/525 20060101AFI20140812BHEP

17Q First examination report despatched

Effective date: 20161012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20181201