DE60336543D1 - Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur - Google Patents

Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur

Info

Publication number
DE60336543D1
DE60336543D1 DE60336543T DE60336543T DE60336543D1 DE 60336543 D1 DE60336543 D1 DE 60336543D1 DE 60336543 T DE60336543 T DE 60336543T DE 60336543 T DE60336543 T DE 60336543T DE 60336543 D1 DE60336543 D1 DE 60336543D1
Authority
DE
Germany
Prior art keywords
producing
microstructure
heteroepitaxial
carrier structure
heteroepitaxial microstructure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60336543T
Other languages
English (en)
Inventor
Bruce Faure
Fabrice Letertre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60336543D1 publication Critical patent/DE60336543D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE60336543T 2003-05-27 2003-05-27 Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur Expired - Lifetime DE60336543D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03291284A EP1482549B1 (de) 2003-05-27 2003-05-27 Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur

Publications (1)

Publication Number Publication Date
DE60336543D1 true DE60336543D1 (de) 2011-05-12

Family

ID=33104212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60336543T Expired - Lifetime DE60336543D1 (de) 2003-05-27 2003-05-27 Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur

Country Status (5)

Country Link
US (3) US6946317B2 (de)
EP (1) EP1482549B1 (de)
JP (1) JP2005047792A (de)
AT (1) ATE504082T1 (de)
DE (1) DE60336543D1 (de)

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FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
JP3881562B2 (ja) * 2002-02-22 2007-02-14 三井造船株式会社 ＳｉＣモニタウェハ製造方法
ATE504082T1 (de) * 2003-05-27 2011-04-15 Soitec Silicon On Insulator Verfahren zur herstellung einer heteroepitaktischen mikrostruktur
US9011598B2 (en) 2004-06-03 2015-04-21 Soitec Method for making a composite substrate and composite substrate according to the method
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DE102005024073A1 (de) * 2005-05-25 2006-11-30 Siltronic Ag Halbleiter-Schichtstruktur und Verfahren zur Herstellung einer Halbleiter-Schichtstruktur
DE112006001751B4 (de) * 2005-07-06 2010-04-08 International Rectifier Corporation, El Segundo Leistungs-Halbleiterbauteil und Verfahren zu Herstellung eines Halbleiterbauteils
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
US20070194342A1 (en) * 2006-01-12 2007-08-23 Kinzer Daniel M GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
TW200802544A (en) * 2006-04-25 2008-01-01 Osram Opto Semiconductors Gmbh Composite substrate and method for making the same
EP2016614A4 (de) * 2006-04-25 2014-04-09 Univ Singapore Verfahren eines auf der epitaxialen lateral-überwachstums-galliumnitrid vorlage gewachsenen zinkoxidfilms
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
JP5496540B2 (ja) * 2008-04-24 2014-05-21 株式会社半導体エネルギー研究所 半導体基板の作製方法
DE102009057020B4 (de) 2009-12-03 2021-04-29 Solaero Technologies Corp. Wachstumssubstrate für invertierte metamorphe Multijunction-Solarzellen
US9190560B2 (en) 2010-05-18 2015-11-17 Agency For Science Technology And Research Method of forming a light emitting diode structure and a light diode structure
GB2483702A (en) * 2010-09-17 2012-03-21 Ge Aviat Systems Ltd Method for the manufacture of a Silicon Carbide, Silicon Oxide interface having reduced interfacial carbon gettering
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
JP2012230969A (ja) * 2011-04-25 2012-11-22 Sumitomo Electric Ind Ltd ＧａＮ系半導体デバイスの製造方法
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
JP2013089741A (ja) * 2011-10-18 2013-05-13 Renesas Electronics Corp 半導体装置、半導体基板、半導体装置の製造方法、及び半導体基板の製造方法
FR3079531B1 (fr) * 2018-03-28 2022-03-18 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau pzt et substrat pour croissance par epitaxie d'une couche monocristalline de materiau pzt
FR3079533B1 (fr) * 2018-03-28 2021-04-09 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau lno et substrat pour croissance par epitaxie d'une couche monocristalline de materiau lno
FR3079532B1 (fr) * 2018-03-28 2022-03-25 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain
CN113223928B (zh) * 2021-04-16 2024-01-12 西安电子科技大学 一种基于转移键合的氧化镓外延生长方法
CN113658849A (zh) * 2021-07-06 2021-11-16 华为技术有限公司 复合衬底及其制备方法、半导体器件、电子设备

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FR2797713B1 (fr) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
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FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2817395B1 (fr) 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
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Also Published As

Publication number Publication date
EP1482549B1 (de) 2011-03-30
US6946317B2 (en) 2005-09-20
US20080210975A1 (en) 2008-09-04
US20050266626A1 (en) 2005-12-01
EP1482549A1 (de) 2004-12-01
US7646038B2 (en) 2010-01-12
US7288430B2 (en) 2007-10-30
ATE504082T1 (de) 2011-04-15
US20040241975A1 (en) 2004-12-02
JP2005047792A (ja) 2005-02-24

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