US9082948B2

US9082948B2 - Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods

Info

Publication number: US9082948B2
Application number: US13/336,853
Authority: US
Inventors: Christiaan J. Werkhoven; Chantal Arena
Original assignee: Soitec SA
Current assignee: Soitec SA
Priority date: 2011-02-03
Filing date: 2011-12-23
Publication date: 2015-07-14
Also published as: US20130161636A1

Abstract

Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The subject matter of this application is related to the subject matter of U.S. patent application Ser. No. 13/020,288, filed Feb. 3, 2011, now U.S. Pat. No. 8,436,363, issued May 7, 2013, which is hereby incorporated herein in its entirety by this reference. The present application is also related to U.S. patent application Ser. No. 13/336,883, filed Dec. 23, 2011, and entitled “Semiconductor Devices Including Substrate Layers And Overlying Semiconductor Layers Having Closely Matching Coefficients Of Thermal Expansion, And Related Methods,” which application is also hereby incorporated herein in its entirety by this reference.

FIELD

The present disclosure generally relates to the fabrication of engineered substrates for use in the fabrication of semiconductor structures or devices, intermediate structures formed during the fabrication of semiconductor structures or devices, and to semiconductor structures or devices using engineered substrates.

BACKGROUND

Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices) and discrete devices such as, radiation emitting devices (e.g., light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity surface emitting lasers (VCSELs)), and radiation sensing devices (e.g., optical sensors). Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on and/or in a surface of a semiconductor substrate.

Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is generally used to form active devices on the silicon wafer. However, in some device applications, the majority of the silicon wafer thickness may be included in the electrical path-way of one or more device structures formed from the silicon wafer, such device structures being commonly referred to as “vertical” device structures.

So-called “engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (SiO₂), silicon nitride (Si₃N₄), or aluminum oxide (Al₂O₃)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively thicker host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment. As a result, the base substrate is often referred to in the art as a “handle” or “handling” substrate. The base substrate may also comprise a semiconductor material other than silicon.

A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), III-V semiconductor materials, and II-VI semiconductor materials.

For example, an engineered substrate may include an epitaxial layer of III-V semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (Al₂O₃) (which may be referred to as “sapphire”). The epitaxial layer may be formed on the surface of the base substrate by a transfer process from a donor structure, for example a donor substrate or donor ingot. The transfer from a donor structure may be desirable when the donor material is highly valuable or in scarce supply. Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V semiconductor material to form one or more devices on the engineered substrate. However, the Coefficient of Thermal Expansion (CTE) mismatch (or difference) between the epitaxial layer and the base substrate comprising the engineered substrate, may influence the formation and processing of the additional layers of material. For example, if the CTE mismatch between the epitaxial layer and the base substrate is substantial, then the engineered substrate may be negatively impacted during the formation of additional layers of materials.

Examples of devices that can take advantage of engineered substrates are high power devices and photonic devices, such as, Light Emitting Diodes (LEDs) and laser diodes. FIG. 1 illustrates a conventional LED. A substrate 110, which may be an engineered substrate, includes an n-type layer 120 disposed thereon. An active region 130, which may include multiple layers, such as, for example, quantum wells, barrier layers, electron blocking layer(s) (EBL) etc., is disposed between the n-type layer 120 and a p-type layer 140. The result is an LED formed by the n-type layer 120, the active region 130, and the p-type layer 140. A first contact 160 provides an electrical connection to the n-type layer 120 and a second contact 150 provides another electrical connection to the to the p-type layer 140. These contacts may be opaque to the wavelength of light emitted by the LED and, as a result, may diminish the overall amount of light available from the LED. Thus, only the area between the first contact 160 and the second contact 150 may produce significant amounts of light. The physical layout of the second contact 150 relative to the n-type layer 120 may cause current crowding in the current flowing between the p-type layer 140 and the n-type layer 120. In addition, the physical layout may require that both p-type and n-type contacts are disposed on an upper surface of the LED structure, wherein such a physical layout may require removal of a portion of the device layers to expose regions for contacting. The removal of a portion of the device layers may increase the complexity of device fabrication, may reduce the area available for light generation and may also decrease device yield.

In view of the above, and for other reasons discussed below, there is a need for a substrate technology that provides a suitable base substrate for donated material from a donor structure. Moreover, there is a need for devices and methods that provide a support substrate with a closely matching CTE with that of an engineered substrate.

BRIEF SUMMARY

The various embodiments of the present disclosure generally relate to engineered substrates and methods of producing the engineered substrates that provide a suitable base substrate with a CTE that closely matches a CTE of the engineered substrate.

This summary is provided to introduce a selection of concepts in a simplified form that are further described in the detailed description below of some example embodiments of the disclosure. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In some embodiments, the present disclosure includes methods of fabricating a semiconductor substrate. The methods include forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A substrate layer is formed on the attachment surface. The substrate layer exhibits a CTE closely matching a CTE of the transfer layer, and has sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer and the substrate layer.

In additional embodiments, the present disclosure includes methods of fabricating a semiconductor substrate. The methods include forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. An ohmic contact is formed between the transfer layer and a contact layer disposed thereon. A low impedance coupling is formed between a substrate layer and the contact layer, wherein the substrate layer provides a structural support for the semiconductor substrate. The methods also include separating the transfer layer from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer, the contact layer, and the substrate layer.

In other embodiments, the present disclosure comprises a semiconductor substrate including a substrate layer configured to provide a sufficient stiffness to the semiconductor substrate. The semiconductor substrate also includes a transfer layer comprising a semiconductor material in contact with an attachment surface of the substrate layer. The transfer layer may be detached from a donor structure comprising the semiconductor material and including a weakened zone in the donor structure at a predetermined depth from the attachment surface to define the transfer layer between the attachment surface and the weakened zone. The substrate layer exhibits a CTE that closely matches a CTE exhibited by the transfer layer.

In additional embodiments, the disclosure includes methods of fabricating a semiconductor substrate. In accordance with such methods, a substrate layer is formed over a surface of a first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the substrate layer, and the substrate layer is formulated to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

In additional embodiments, the present disclosure includes semiconductor structures comprising a substrate layer, a first semiconductor layer disposed over a surface of the substrate layer, and at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the substrate layer. The substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

In additional embodiments, the present disclosure includes methods that may be used to fabricate a semiconductor structure. In accordance with such methods, a first substrate layer is formed over a surface of a first semiconductor layer. A second substrate layer is thermally sprayed on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer, and at least one of the first substrate layer and the second substrate layer is formulated to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

In yet further embodiments, the present disclosure includes semiconductor structures that comprise a substrate including a first substrate layer and at least a second substrate layer, a first semiconductor layer disposed over a surface of the first substrate layer, and at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Further aspects, details, and alternate combinations of the elements of embodiments of the disclosure will be apparent from the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure may be understood more fully by reference to the following detailed description of example embodiments of the present disclosure, which are illustrated in the appended figures in which:

FIG. 1 is a simplified cross-section drawing of a conventional LED structure;

FIG. 2 is a simplified cross-section drawing of a donor structure with a weakened zone to create a transfer layer;

FIGS. 3A-3B are simplified cross-section drawings illustrating development of a composite substrate with a substrate layer and a transfer layer according to additional embodiments of the disclosure;

FIGS. 4A-4C are simplified cross-section drawings illustrating development of a composite substrate with a substrate layer, a transfer layer, and a contact layer therebetween according to additional embodiments of the disclosure;

FIG. 5 is a simplified cross-section drawing illustrating additional semiconductor material deposited over a semiconductor material of the structure of FIG. 3B;

FIG. 6 is a simplified cross-section drawing illustrating additional semiconductor material deposited over the semiconductor material of the structure of FIG. 4C;

FIGS. 7A-7C illustrate a composite substrate with a silicon carbide (SiC) transfer layer and a high power electronic device formed on the composite substrate according to additional embodiments of the disclosure;

FIGS. 8A-8D illustrate a composite substrate with an n-doped gallium nitride (GaN) transfer layer and a photonic device formed on the composite substrate, which is flipped to form an n-layer-up photonic device according to additional embodiments of the disclosure; and

FIG. 9 is a simplified schematic illustration showing a thermal spray device spraying a substrate layer onto a donor structure that includes a semiconductor material.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE

The illustrations presented herein are not meant to be actual views of any particular material, device, or method, but are merely idealized representations that are employed to describe embodiments of the present disclosure.

It should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not limit the quantity or order of those elements, unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements may comprise one or more elements.

The following description provides specific details, such as material types and processing conditions, in order to provide a thorough description of embodiments of the present disclosure and implementation thereof. However, a person of ordinary skill in the art will understand that the embodiments of the present disclosure may be practiced without employing these specific details and in conjunction with conventional fabrication techniques. In addition, the description provided herein does not form a complete process flow for manufacturing a semiconductor device or system. Only those process acts and structures necessary to understand the embodiments of the present disclosure are described in detail herein. The materials described herein may be formed (e.g., deposited or grown) by any suitable technique including, but not limited to, spin-coating, blanket coating, Bridgeman and Czochralski processes, chemical vapor deposition (“CVD”), plasma enhanced chemical vapor deposition (“PECVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, or physical vapor deposition (“PVD”). While the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three-dimensional configurations.

Terms such as “horizontal” and “vertical,” as used herein, define relative positions of elements or structures with respect to a major plane or surface of a semiconductor structure (e.g., wafer, die, substrate, etc.), regardless of the orientation of the semiconductor structure, and are orthogonal dimensions interpreted with respect to the orientation of the structure being described. As used herein, the term “vertical” means and includes a dimension substantially perpendicular to the major surface of a semiconductor structure, and the term “horizontal” means a dimension substantially parallel to the major surface of the semiconductor structure.

As used herein, the term “semiconductor structure” means and includes any structure that is used in the formation of a semiconductor device. Semiconductor structures include, for example, dies and wafers (e.g., carrier substrates and device substrates), as well as assemblies or composite structures that include two or more dies and/or wafers three-dimensionally integrated with one another. Semiconductor structures also include fully fabricated semiconductor devices, as well as intermediate structures formed during fabrication of semiconductor devices. Semiconductor structures may comprise conductive materials, semiconductor materials, non-conductive materials (e.g., electrical insulators), and combinations thereof.

As used herein, the term “processed semiconductor structure” means and includes any semiconductor structure that includes one or more at least partially formed device structures. Processed semiconductor structures are a subset of semiconductor structures, and all processed semiconductor structures are semiconductor structures.

As used herein, the term “III-V semiconductor material” means and includes any semiconductor material that is at least predominantly comprised of one or more elements from group IIIA of the periodic table (e.g., B, Al, Ga, In, and Ti) and one or more elements from group VA of the periodic table (e.g., N, P, As, Sb, and Bi).

Unless specified differently, as used herein, the terms “coefficient of thermal expansion” and “CTE,” when used with respect to a material or structure, are synonymous and mean the average linear coefficient of thermal expansion of the material or structure at room temperature.

As used herein, the term “engineered substrate,” in its broadest sense, means and includes any substrate comprising two or more layers of material and that is intended to be used as a substrate for the fabrication of one or more semiconductor devices thereon. Engineered substrates include, as non-limiting examples, semiconductor-on-insulator type substrates.

As used herein, the term “sufficient stiffness” means a stiffness for a semiconductor structure that provides enough stiffness that significant structural damage due to plastic or elastic deformation does not occur to the semiconductor structure during subsequent processing or handling. As non-limiting examples, such structural damage may include dislocations, cracking, crystal lattice damage, warp, bow, and layer separation.

As used herein, the term “composite substrate layer” means a layer of a substrate comprising an alloy or mixture of two or more elemental constituents. The microstructure of some composite substrate layers may be at least substantially comprised of a single, generally homogeneous phase, or a single, inhomogeneous phase. The microstructure of other composite substrate layers may comprise two or more distinct phases, each of which may be homogeneous or inhomogeneous. Such composite substrate layers may comprise one or more metal phases, one or more ceramic phases, one or more semiconductor phases, or a mixture of one or more of metal phases, ceramic phases, and semiconductor phases. Thus, composite substrate layers may include, but are not limited to, metal-metal composite materials, ceramic-ceramic composite materials, and metal-ceramic composite materials.

The various embodiments of the present disclosure are concerned with engineered substrates and methods of producing the engineered substrates that provide a suitable base substrate layer with a CTE that closely matches a CTE of a semiconductor material carried on the base substrate layer.

Embodiments of the disclosure may have applications to engineered substrates comprising a wide range of semiconductor materials, such as silicon, germanium, silicon carbide, and III-V semiconductor materials. For example, the methods and structures of the embodiments of the disclosure may be applied to III-nitrides, III-arsenides, III-phosphides and III-antimonides, in binary, ternary, quaternary, and quinary form.

FIG. 2 is a simplified cross-section drawing of a donor structure 210 with a weakened zone 220 to create a first semiconductor layer 230. As non-limiting examples, a detachment process described herein may use SMARTCUT® technology. Such processes are described in detail in, for example, U.S. Pat. No. RE39,484, issued Feb. 6, 2007, to Bruel; U.S. Pat. No. 6,303,468, issued Oct. 16, 2001, to Aspar et al.; U.S. Pat. No. 6,335,258, issued Jan. 1, 2002, to Aspar et al.; U.S. Pat. No. 6,756,286, issued Jun. 29, 2004, to Moriceau et al.; U.S. Pat. No. 6,809,044, issued Oct. 26, 2004, to Aspar et al.; U.S. Pat. No. 6,946,365, issued Sep. 20, 2005, to Aspar et al.; U.S. Pat. No. 7,531,428, issued May 12, 2009, to Dupont; U.S. Pat. No. 6,858,107, issued Feb. 22, 2005, to Ghyselen et al.; and U.S. Pat. No. 6,867,067, issued Mar. 15, 2005, to Ghyselen et al.; the disclosures of each of which are incorporated herein in their entirety by this reference. However, it should be understood that other processes suitable for manufacturing a compound material wafer that include utilizing predetermined weakened areas could also be used.

To perform the detachment process, a predetermined weakened zone 220 may be farmed in the donor structure 210. FIG. 2 shows use of the SMARTCUT® technology wherein atomic species 250, such as one or more of hydrogen ions, helium ions or other inert gas ions, are implanted through an attachment surface 240 with a dose and energy to create the weakened zone 220 in the donor structure 130. The weakened zone 220 is substantially parallel to the main attachment surface 240 and at a predetermined depth based on parameters of the atomic species implant process.

The first semiconductor layer 230 is thus formed between the attachment surface 240 and the weakened zone 220. In addition, a residual donor structure is formed between the weakened zone 220 and an opposite surface from the attachment surface 240.

The donor structure 210 includes a semiconductor material such as silicon, germanium, a III-V semiconductor material such as a III-nitride (e.g., GaN, InGaN, AlGaN), a II-VI semiconductor material, or SiC. The semiconductor material may be un-doped or, for some applications, doped n-type or p-type (e.g., highly doped (n+ or p+), moderately doped (n or p), or lightly doped (n− or p−)). The semiconductor may be a freestanding wafer as shown in FIG. 2 or a multilayer wafer (e.g., GaN on a sapphire base). The donor structure 210 may also comprise at least a portion of an ingot (or boule) of semiconductor material, and, in some embodiments, the at least a portion of the ingot (or boule) may include any of the semiconductor materials mentioned above. The ingot (or boule) may comprise a structure such as those described in U.S. Pat. No. 6,858,107 issued Feb. 22, 2005 to Ghyselen et al., and U.S. Pat. No. 6,867,067 issued Mar. 15, 2005 to Ghyselen et al., the disclosures of each of which are incorporated herein in their entirety by this reference.

If the donor structure 210 is a III-nitride material, the polarity of the surface being implanted should be considered in determining the polarity of the final composite substrate. As a non-limiting example, a GaN donor structure may be used to develop a Gallium-polar face or a Nitrogen-polar face for subsequent processing. As a further non-limiting example, an InGaN donor structure may be used to develop a metal-polar face or a Nitrogen-polar face for subsequent processing.

For conventional layer transfer to a carrier wafer, typically a bonding process is used followed by splitting off of the implanted wafer by means of some heat treatment. The bonding process requires a high quality of the surfaces to be bonded to avoid large area defects (non-transferred areas) while the CTE of both wafers should not be too different to avoid wafer breakage as a result of the splitting process. For some applications, conductive bonding of a semiconductor material to a conductive substrate is desirable to construct vertical device structures, i.e., devices that have the active area near the surface of the semiconductor layer and a contact area near the interface of the semiconductor with the substrate or carrier wafer.

However, such an approach is difficult to realize as today many bonding processes involve layers of silicon dioxide (SiO₂) on the bonding faces to ensure a high quality bond. However, SiO₂is an insulator and will make electrical conduction difficult, if not impossible, and, in addition, impede efficient heat dissipation of the device to the substrate.

As a result, embodiments of the present disclosure provide structures and processes for providing a support structure that may provide heat dissipation and with a CTE that closely matches a CTE of the first semiconductor layer 230 or device structure formed thereon. In some embodiments, electrical contact may be provided (for example, an ohmic or Schottky contact) between the first semiconductor layer 230 and a first substrate layer, which may serve as an electrically conductive contact layer. Such a first substrate layer may comprise a metal or metal alloy in some embodiments. An ohmic contact (i.e., a contact with a voltage-independent resistance) is developed at a metal-semiconductor junction if the Schottky barrier height is zero or negative. In other words, an ohmic contact will have current-versus-voltage characteristics that are substantially linear and symmetric. In such cases, the carriers are free to flow in or out of the semiconductor so that there is a minimal resistance across the ohmic contact.

FIGS. 3A-3B are simplified cross-section drawings illustrating development of an engineered substrate that includes a base substrate layer 310 and a first semiconductor layer 230 according to some embodiments of the disclosure. The first semiconductor layer 230 may be transferred to the base substrate layer 310, as described herein, and thus may comprise a “transferred layer.” The base substrate layer 310 may be formed to a thickness sufficient to form a metallic support substrate with sufficient stiffness to provide structural support to the first semiconductor layer 230.

The base substrate layer 310 may have an average thickness (measured perpendicular to the major planar surfaces of the substrate layer) that is sufficient to provide sufficient stiffness for structurally supporting the first semiconductor layer 230. As non-limiting examples, the base substrate layer 310 may have an average thickness of at least about five (5) microns, or at least about ten (10) microns. In some embodiments, the base substrate layer 310 may have an average thickness between about ten (10) microns and about one hundred (100) microns, and, more likely, between about ten (10) microns and about twenty (20) microns.

The base substrate layer 310 may be formed on the attachment surface 240 with a process suitable for providing an electrical contact, for example ohmic contact, between the base substrate layer 310 and the first semiconductor layer 230. Prior to depositing the base substrate layer 310, the surface of the semiconductor may need treatment to remove any surface oxide or other surface layers that may impact the quality of the base substrate layer 310. For example, a thin gallium oxide layer may need to be removed from the first semiconductor layer 230 when the first semiconductor layer 230 comprises gallium nitride, prior to depositing the base substrate layer 310 and for the formation of an electrical contact, e.g., an ohmic contact.

As non-limiting examples, the base substrate layer 310 may be deposited using one or more of a physical deposition process (e.g., physical vapor deposition (PVD), sputtering, etc.), a thermal spray coating process (e.g., a plasma spraying process, a flame spraying process, etc.), a plating process (e.g., an electroless plating process and/or an electroplating process), and a chemical vapor deposition process (CVD).

By way of example and not limitation, the base substrate layer 310 may be deposited using a plasma spraying process. FIG. 9 is a schematic illustration of a plasma spray nozzle depositing a base substrate layer 310 on a donor structure 210 that includes the first semiconductor layer 230 (FIG. 2). As shown in FIG. 9, a plasma spray device 900 may be used to spray at least partially melted particles 910 onto the donor structure 210. The partially melted particles 910 may consolidate with one another and solidify over the donor structure 210 to form the base substrate layer 310 on the donor structure 210.

The plasma spray device 900 includes an outer body 920, which may be generally tubular in shape. A first electrode 930 (e.g., an anode) may be disposed at an end of the outer body 920. The first electrode 930 may be generally annular in structure, such that a passageway is defined through the center of the first electrode 930. A second electrode 940 (e.g., a cathode) may be disposed within the interior of the outer body 920, as shown in FIG. 9. Thus, a passageway 950 is defined in the annular space between the exterior surface of the second electrode 940 and the interior surface of the outer body 920. The passageway 950 communicates with the passageway extending through the center of the first electrode 930.

In this configuration, plasma-generating gas may be caused to flow through the passageway 950 and the passageway extending through the center of the first electrode 930, and out from the plasma spray device 900. A voltage may be applied between the first electrode 930 and the second electrode 940 to generate an electrical current (i.e., an electrical discharge, or spark) therebetween, which, in the presence of the plasma-generating gas flowing through the plasma spray device 900, results in the formation of a plasma 960. The plasma 960 is sprayed out from the plasma spray device 900 due to the flow of the plasma gas through the plasma spray device 900.

Particulate matter is introduced into the plasma 960 proximate the first electrode 930. For example, a conduit 970 may be used to convey powdered material from a powder source 980 to the plasma 960, as shown in FIG. 9. The powdered material may comprise particles of the material or materials that will ultimately form the base substrate layer 310. The powdered material may be carried through the conduit 970 by a carrier gas flowing through the conduit 970. As the powdered material leaves the conduit 970 and enters the plasma 960, the powdered material may be at least partially melted and carried toward the donor structure 210 by the plasma jet emanating from the plasma spray device 900. The particles impinge on the donor structure 210 (or on material previously deposited on the donor structure 210), where they cool and solidify to form the material of the base substrate layer 310.

Methods other than thermal spray methods may be used to form the base substrate layer 310 on or over the donor structure 210 in additional embodiments of the disclosure.

The base substrate layer 310 may have (i.e., exhibit) a CTE that closely matches a CTE of the first semiconductor layer 230 and/or additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes, which may reduce or prevent strain and cracking in the first semiconductor layer 230 and/or the additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes. Table 1 below lists CTE values for some non-limiting materials for the first semiconductor layer 230 and the base substrate layer 310 in some example embodiments of the disclosure.

TABLE 1

Material Class	Material	CTE (10⁻⁶/° K)

Semiconductors	GaN	5.6
	GaAs	5.4
	SiC	4.5
	Si	2.5
Metals	Tungsten	4.5
	Molybdenum	5.5
	Zirconium	5.7
	Hafnium	6.1
	Rhenium	6.2
	Tantalum	6.5
Ceramics	Silicon Oxide (SiO₂)	0.5
	Sapphire (Al₂O₃)	8.6

In some embodiments, the CTE of the base substrate layer 310 may be within about 20%, within about 10%, within about 5%, within about 2%, or even within about 1% of the CTE of the first semiconductor layer 230 and/or any additional semiconductor material or materials ultimately deposited over the first semiconductor layer 230, as described herein.

In some embodiments, the base substrate layer 310 may comprise a refractory metal or a refractory metal alloy. For these embodiments, tungsten, molybdenum, and zirconium (and particularly tungsten) used as the base substrate layer 310 would have a CTE closely matching a CTE of a SiC first semiconductor layer 230. Similarly, for these embodiments zirconium, hafnium, rhenium, and tantalum used as the base substrate layer 310 would closely match a GaN first semiconductor layer 230 and in some embodiments particularly molybdenum.

In additional embodiments, the base substrate layer 310 may comprise a composite substrate layer, which includes two or more elements so as to provide the base substrate layer 310 with a CTE between those of the two or more elements of which the base substrate layer 310 is composed. For example, the base substrate layer 310 may comprise an alloy or mixture of two or more elements. In such embodiments, the microstructure of the base substrate layer 310 may be at least substantially comprised of a single, generally homogeneous phase, the base substrate layer 310 may be at least substantially comprised of a single, inhomogeneous phase, or the base substrate layer 310 may comprise two or more distinct phases, each of which may be homogeneous or inhomogeneous. In such embodiments, the base substrate layer 310 may comprise one or more metal phases, one or more ceramic phases, one or more semiconductor phases, or a mixture of one or more of metal phases, ceramic phases, and semiconductor phases. Thus, the substrate layer may be formulated to comprise one of a metal-metal composite material, a ceramic-ceramic composite material, and a metal-ceramic composite material.

The entire structure including the donor structure 210 and the base substrate layer 310 shown in FIG. 3A may be placed into a furnace (not shown) and heated so that the weakened zone 220 may be further weakened. With the weakening, the first semiconductor layer 230 and accompanying base substrate layer 310 may be separated from the donor structure at the weakened zone 220. In addition to, or in place of thermal energy, other forms of energy, such as mechanical energy or chemical energy, may be used to weaken the structure along the weakened zone 220 and ultimately separate the first semiconductor layer 230 from the remainder of the donor structure 210.

The structures thus formed after the separation are a residual donor structure (not shown) capable of donating further thin transfer layers, and an engineered susbtrate 450 shown in FIG. 3B, which includes the base substrate layer 310 and the first semiconductor layer 230. As non-limiting examples, the first semiconductor layer 230 may have an average layer thickness measured perpendicular to the major planar surfaces of the engineered susbtrate 450 of about one thousand (1,000) nanometers or less, about five hundred (500) nanometers or less, or even about one hundred (100) nanometers or less.

As shown in FIG. 3B, the engineered susbtrate 450 may be flipped over for additional processing on the exposed surface of the first semiconductor layer 230. Prior to performing any further processing steps, the engineered susbtrate 450 may receive a surface treatment, such as, for example, polishing, cleaning, or combinations thereof. Additional processing may include, as a non-limiting example, adding device structures on the engineered susbtrate 450. The device structures may include multiple layers of doped semiconductor material, un-doped semiconductor material, and active areas as are known in the art to produce electronic elements, photonic elements, and combinations thereof.

FIGS. 4A-4C are simplified cross-section drawings illustrating development of an engineered susbtrate 450 with an intermediate substrate layer 410 disposed between the base substrate layer 310 and the first semiconductor layer 230. The intermediate substrate layer 410 may serve as an electrical contact layer and/or as a protective layer for protecting the first semiconductor layer 230 when the base substrate layer 310 is formed over the first semiconductor layer 230 using, for example, a thermal spray process like those previously described herein.

In the embodiments of FIGS. 4A-4C, an intermediate substrate layer 410 comprising a metal or metal alloy is deposited on the attachment surface 240 of the donor structure 210 (FIG. 2) to form the structure shown in FIG. 4A.

In some embodiments, the intermediate substrate layer 410 may be electrically conductive and configured to provide an ohmic contact that is of high quality (e.g., low resistance) between the first semiconductor layer 230 and the intermediate substrate layer 410. As a non-limiting example, if the donor material of the donor structure 210 is n+ doped GaN, then the intermediate substrate layer 410 may be, e.g., a Ti/Al/Ni/Au stack, or a Ti/Al stack when the use of gold may be detrimental to the device performance. As another non-limiting example, if the donor material of the donor structure 210 is p+ doped GaN, the intermediate substrate layer 410 may be, e.g., a Ni/Au stack or Ni (the first metal in the list being closest to the semiconductor).

In additional embodiments, the intermediate substrate layer 410 may be used to protect the first semiconductor layer 230 from damage that might otherwise result from formation of the base substrate layer 310 over the first semiconductor layer 230. For example, in embodiments in which the base substrate layer 310 is formed using a thermal spray process as previously described herein, the impingement of the hot, thermally sprayed particles onto the first semiconductor layer 230 might result in thermal damage to the first semiconductor layer 230, or defects created by the mechanical forces imparted on the first semiconductor layer 230 by the impinging particles.

Therefore, the intermediate substrate layer 410 may be formed over the first semiconductor layer 230 using low temperature processes and processes that will not impart such mechanical forces on the first semiconductor layer 230. As a non-limiting example, the intermediate substrate layer 410 may be deposited over the surface of the first semiconductor layer 230 at a temperature of about 900° C. or less. After first forming the intermediate substrate layer 410, the base substrate layer may be thermally sprayed on a side of the intermediate substrate layer 410 opposite the first semiconductor layer 230. For example, the intermediate substrate layer 410 may be deposited on the first semiconductor layer 230 using at least one of a physical vapor deposition process, a sputtering process, a spin-on process, an electroless plating process, and an electrical plating process.

In embodiments in which the intermediate substrate layer 410 is to serve as a protective layer during a thermal spray process used to form the base substrate layer 310, the intermediate substrate layer 410 may comprise a material that will conduct and dissipate the thermal energy brought to the structure by the impinging thermally sprayed particulate matter. For example, the intermediate substrate layer 410 may comprise a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm⁻¹K⁻¹). In some embodiments, the intermediate substrate layer 410 may comprise a material exhibiting a thermal conductivity of at least about one hundred watts per meter Kelvin (100 Wm⁻¹K⁻¹), at least about two hundred watts per meter Kelvin (200 Wm⁻¹K⁻¹), at least about three hundred watts per meter Kelvin (300 Wm⁻¹K⁻¹), or even at least about four hundred watts per meter Kelvin (400 Wm⁻¹K⁻¹).

Additionally, in such embodiments, the intermediate substrate layer 410 may comprise a material that is soft enough to absorb (by, for example, plastic deformation of the material of the intermediate substrate layer 410) the kinetic energy of the impinging thermally sprayed particulate matter so as to prevent damage to the first semiconductor layer 230. For example, the intermediate substrate layer 410 may comprise a material exhibiting a Vickers hardness of about 3500 MPa or less. In some embodiments, the intermediate substrate layer 410 may comprise a material exhibiting a Vickers hardness of about 2500 MPa or less, about 1800 MPa or less, or even about 1600 MPa or less.

In some embodiments, the intermediate substrate layer 410 may comprise a refractory metal (i.e., a commercially pure refractory metal or a metal alloy based on one or more refractory metals). By way of example and not limitation, the intermediate substrate layer 410 may comprise at least one of titanium, molybdenum, zirconium, and hafnium. Zirconium, molybdenum and hafnium may be particularly suitable in some applications, as they exhibit relatively low hardness values.

The intermediate substrate layer 410 may have an average thickness of about one micron (1.0 μm) or less, about five hundred nanometers (500 nm) or less, or about one hundred nanometers (100 nm) or less. In some embodiments, such as those in which the intermediate substrate layer 410 is used as an electrical contact layer but not as a protective layer, the intermediate substrate layer 410 may be as thin as a few monolayers of atoms. In some embodiments, the intermediate substrate layer 410 may have an average thickness of between about one (1) nanometer and about fifty (50) nanometers.

Prior to depositing the intermediate substrate layer 410, the surface 240 of the semiconductor layer 230 may need treatment to remove any surface oxide or other surface layers which may impact the quality of the intermediate substrate layer 410, e.g., a thin gallium oxide layer may need to be removed prior to depositing the intermediate substrate layer 410.

As shown in FIG. 4B, a base substrate layer 310 is formed on the intermediate substrate layer 410. For example, the base substrate layer 310 may be thermally sprayed on a side of the intermediate substrate layer 410 opposite the first semiconductor layer 230. In some embodiments, the process used to form the base substrate layer 310 on the intermediate substrate layer 410 may be suitable for providing a low-impedance coupling between the base substrate layer 310 and the intermediate substrate layer 410. In the embodiments of FIGS. 4A-4C, the combination of the intermediate substrate layer 410 and the base substrate layer 310 may be referred to herein as a multi-layer substrate 310A.

The entire structure of FIG. 4B, which includes the donor structure 210 and the multi-layer substrate 310A, may be placed into a furnace (not shown) and heated so that the weakened zone 220 may be further weakened. With the weakening, the first semiconductor layer 230 and accompanying multi-layer substrate 310A may be separated from the donor structure 210 at the weakened zone 220, as previously described with reference to FIG. 3A.

The structures thus formed after the separation are a residual donor structure (not shown) capable of donating further thin transfer layers and an engineered susbtrate 450 including the base substrate layer 310, the intermediate substrate layer 410, and the first semiconductor layer 230.

As shown in FIG. 4C, the engineered susbtrate 450 may be flipped over for additional processing on the exposed surface of the first semiconductor layer 230, as previously described with reference to FIG. 3B.

In the embodiments of FIGS. 3A-3B and FIGS. 4A-4C, the base substrate layer 310 (and, optionally, the intermediate substrate layer 410) should be able to remain chemically and physically stable at temperatures high enough for subsequent processing, such as, for example, the heating for the separation and growth/deposition/processing of additional layers of material. As a non-limiting example, for subsequent processing of addition GaN layers, the base substrate layer 310 (and the optional intermediate substrate layer 410) should be able to withstand temperatures in the range of about 900° C. to about 1100° C. In addition, for subsequent processing, the base substrate layer 310 (and the optional intermediate substrate layer 410) should be able to withstand the chemical environment within the additional growth/deposition/processing equipment.

As previously mentioned, the base substrate layer 310 and/or the intermediate substrate layer 410 may have (i.e., exhibit) a CTE that closely matches a CTE of the first semiconductor layer 230 and/or additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes, which may reduce or prevent strain and cracking in the first semiconductor layer 230 and/or the additional semiconductor material deposited on the first semiconductor layer 230 during subsequent growth processes. In other words, at least one of the first substrate layer and the second substrate layer may be formulated to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer 230 and at least one additional semiconductor layer deposited over the first semiconductor layer 230.

FIG. 5 illustrates a relatively thick volume of additional semiconductor material 470 epitaxially deposited over the first layer of semiconductor material 230 of FIG. 3B. Similarly, FIG. 6 illustrates a relatively thick volume of additional semiconductor material 470 epitaxially deposited over the first layer of semiconductor material 230 of FIG. 4C. The thick volume of additional semiconductor material 470 of FIGS. 5 and 6 may comprise a single additional layer of semiconductor material, or it may comprise a plurality of additional layers of semiconductor material epitaxially deposited over the first layer of semiconductor material 230, as described below with reference to FIGS. 7A-7C and 8A-8D.

As the CTE of the base substrate layer 310 and/or the intermediate substrate layer 410 closely matches the CTE of the first semiconductor layer 230 and/or the volume of additional semiconductor material 470, the volume of additional semiconductor material 470 may be grown to relatively high thickness without cracking in order to complete the fabrication of a device structure.

As a non-limiting example, the volume of additional semiconductor material 470 may have an average total thickness of at least about one hundred (100) nanometers or at least about five hundred (500) nanometers. In some embodiments, the volume of additional semiconductor material 470 may have an average total thickness of between about one (1) micron and about one hundred (100) microns.

Some non-limiting examples of compositions for the base substrate layer 310, the first semiconductor layer 230, and the volume of additional semiconductor material 470 are set forth in Table 2 below.

TABLE 2

		First	Additional
Example	Substrate layer	Semiconductor	Semiconductor
Number
310	Layer 230	Material 470

1	W	SiC	SiC
2	Mo	SiC	SiC
3	Mo	GaAs	GaAs
4	Zr	GaN	GaN
5	Zr	GaN	GaAs
6	Mo	GaN	GaN
7	Ta/W Alloy	GaN	GaN
8	Ta/W Alloy	GaN	SiC
9	Ta/W Alloy	SiC	GaN
10	Ta/W Alloy	SiC	SiC
11	SiO₂/Al₂O₃	Si	Si
	Composite
12	SiO₂/Al₂O₃	SiC	SiC
	Composite
13	SiO₂/Al₂O₃	GaN	GaN
	Composite

In the compositions of Example Numbers 7 through 10 set forth in Table 2, the percentages of the different elements or phases in the materials of the base substrate layers 310 may be tailored to render the CTE of the base substrate layer 310 closer to the CTE of the first semiconductor layer 230 and/or the volume of additional semiconductor material 470. For example, the Rule of Mixtures may be used to predict the CTE of the base substrate layer 310 when the base substrate layer 310 comprises a mixture of two or more phases using the relative volumetric percentages of the two or more phases in the composite material of such a base substrate layer 310. According to the rule of mixtures (for isotropic properties), the CTE of a two-phase composite material is given by the equation:
α_C=α₁(V ₁)+α₂(V ₂),
wherein α_Cis the CTE of the composite material, α₁is the CTE of the first phase in the composite material, α₂is the CTE of the second phase in the composite material, V₁is the volume fraction of the first phase in the composite material, and V₂is the volume fraction of the second phase in the composite material.

Thus, in the composition of Example Number 11, the composite base substrate layer 310 may comprise about seventy five (75) percent by volume silicon oxide (SiO₂) and about twenty five (25) percent by volume aluminum oxide (Al₂O₃), such that the composite material of the base substrate layer 310 including the 75 vol % SiO₂and the 25 vol % percent Al₂O₃is predicted to exhibit a CTE of about 2.5, which is equal to that exhibited by the silicon of the first semiconductor layer 230 and the volume of additional semiconductor material 470 according to the Rule of Mixtures (i.e., 2.5=0.5(0.75)+8.6(0.25)).

Similarly, in the composition of Example Number 12, the composite base substrate layer 310 may comprise about fifty one (51) percent by volume silicon oxide (SiO₂) and about forty nine (49) percent by volume aluminum oxide (Al₂O₃), such that the composite material of the base substrate layer 310 including the 51 vol % SiO₂and the 49 vol % percent Al₂O₃is predicted to exhibit a CTE of about 4.5, which is equal to that exhibited by the silicon carbide of the first semiconductor layer 230 and the volume of additional semiconductor material 470 according to the Rule of Mixtures (i.e., 4.5=0.5(0.51)+8.6(0.49)).

Any of Example Numbers 1 through 13 optionally may further comprise an intermediate substrate layer 410 comprising a material as previously described herein. For example, in embodiments in which at least one of the first semiconductor layer 230 and the additional semiconductor material 470 comprises gallium nitride (GaN), such as in Example Numbers 4 through 9 and 13 in Table 2, an intermediate substrate layer 410 may be included comprising at least one of titanium, zirconium, molybdenum, and hafnium. As shown in Table 1 above, gallium nitride (GaN) has a CTE of about 5.6×10⁻⁶/° K. Zirconium has a coefficient of thermal expansion of 5.7×10⁻⁶/° K, which is within about 1.8% of the CTE of gallium nitride. Molybdenum has a coefficient of thermal expansion of 5.5×10⁻⁶/° K, which is within about 1.8% of the CTE of gallium nitride.

FIGS. 7A-7C illustrate an engineered susbtrate 450S with a silicon carbide (SiC) first semiconductor layer 230S and a high power electronic device formed on the engineered susbtrate 450S according to additional embodiments of the disclosure. The engineered substrate 450S includes the SiC first semiconductor layer 230S on the base substrate layer 310. The substrate layer may comprise a tungsten layer 310T in some embodiments. As shown in Table 1, the SiC first semiconductor layer 230 and the tungsten layer 310T have closely matching in CTEs, such that the SiC first semiconductor layer 230 and high power electronic device formed thereon will experience little or no strain effects due to a CTE mismatch during device formation. In other embodiments, the base substrate layer 310 may comprise an SiO₂/Al₂O₃composite layer, as previously described.

As illustrated in FIG. 7B, a power device may be formed with one or more power device layers 710 on the SiC first semiconductor layer 230S. A contact layer 730 provides an electrical connection to the power device layer 710.

FIG. 7C illustrates an optional thick substrate 750 bonded to the engineered susbtrate 450S.

FIGS. 8A-8D illustrate a composite substrate with an n-doped gallium nitride (GaN) first semiconductor layer 230 and a photonic device formed on the engineered susbtrate 450, which is flipped to form an n-layer-up photonic device according to additional embodiments of the disclosure.

The layers in the embodiment of FIG. 8A are similar to those of the embodiments of FIG. 3B. A photonic device, such as, for example, an LED may be formed on the semiconductor material 230, which is formed as an n-doped gallium nitride (GaN) first semiconductor layer 230N in this embodiment.

As shown in FIG. 8B, the photonic device may include an active region 810, which may include multiple layers of semiconductor material, such as quantum wells, disposed on the n-type gallium nitride (GaN) first semiconductor layer 230N. One or more p-type GaN layers 820 may be disposed on the active layer 810. The result is an LED formed by the n-type gallium nitride (GaN) first semiconductor layer 230N, the active layer 810, and the p-type layer 820.

With the photonic device structure formed, a contact layer 840, such as those described above, may be formed on the p-type GaN layer 820 providing an electrical connection to the p-type layer 820. A heat sink, such as a thick substrate 850 comprising a metal may be formed on the contact layer 840. The resulting structure may be characterized as being flipped relative to previously described embodiments. The flipped configuration is illustrated in FIG. 8C. The base substrate layer 310 may then be removed to expose the n-type gallium nitride (GaN) first semiconductor layer 230N.

The resulting LED structure provides a vertical diode structure, which, in contrast to the diode structure in FIG. 1, does not need an additional electrical connection exposed on the top layers for connection to the p-side of the diode. Rather, the p-side of the diode may be contacted through the contact layer 840 and the thick substrate 850. A contact layer 830 may be formed to provide an electrical connection to an n-doped gallium nitride (GaN) first semiconductor layer 230N.

Additional non-limiting example embodiments are disclosed below.

Embodiment 1

A method of fabricating a semiconductor structure, comprising: forming a first substrate layer over a surface of a first semiconductor layer; thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer; epitaxially growing at least one additional semiconductor layer over the first semiconductor layer on a side thereof opposite the first substrate layer; and formulating at least one of the first substrate layer and the second substrate layer to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 2

The method of Embodiment 1, further comprising formulating the first substrate layer to comprise a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm⁻¹K⁻¹) and a Vickers hardness of about 3500 MPa or less.

Embodiment 3

The method of Embodiment 1 or Embodiment 2, further comprising selecting the first semiconductor layer to comprise a portion of a donor structure for donating the first semiconductor layer to another structure comprising the second substrate layer.

Embodiment 4

The method of Embodiment 3, further comprising forming a weakened zone in the donor structure at a predetermined depth to define the first semiconductor layer between the surface of the first semiconductor layer and the weakened zone and a residual donor structure between the weakened zone and a surface of the donor structure opposite the surface of the first semiconductor layer.

Embodiment 5

The method of Embodiment 4, further comprising separating the first semiconductor layer from the donor structure at the weakened zone to form a substrate structure comprising the first semiconductor layer, the first substrate layer, and the second substrate layer.

Embodiment 6

The method of any one of Embodiments 1 through 5, wherein forming the second substrate layer on the first substrate layer comprises plasma spraying the second substrate layer onto the first substrate layer.

Embodiment 7

The method of any one of Embodiments 1 through 6, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 5% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 8

The method of Embodiment 7, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 2% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 9

The method of Embodiment 8, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 1% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 10

The method of any one of Embodiments 1 through 9, further comprising forming the first substrate layer to have an average thickness of about one micron (1.0 μm) or less.

Embodiment 11

The method of any one of Embodiments 1 through 10, further comprising forming the second substrate layer to have an average thickness of at least about ten microns (10.0 μm).

Embodiment 12

The method of Embodiment 11, further comprising forming the second substrate layer to have an average thickness of between about ten microns (10.0 μm) and about one hundred microns (100.0 μm).

Embodiment 13

The method of any one of Embodiments 1 through 12, further comprising selecting the first semiconductor layer to have an average thickness of about five hundred nanometers (500 nm) or less.

Embodiment 14

The method of any one of Embodiments 1 through 13, further comprising forming the at least one additional semiconductor layer to have an average total thickness of at least one hundred nanometers (100 nm).

Embodiment 15

The method of Embodiment 14, further comprising forming the at least one additional semiconductor layer to have an average total thickness of between about one micron (1.0 μm) and about one hundred microns (100.0 μm).

Embodiment 16

The method of any one of Embodiments 1 through 15, further comprising selecting the first semiconductor layer to comprise a semiconductor material selected from the group consisting of silicon, germanium, III-V semiconductor material, and II-VI semiconductor material.

Embodiment 17

The method of any one of Embodiments 1 through 16, wherein formulating the first substrate layer further comprises formulating the first substrate layer to comprise a refractory metal.

Embodiment 18

The method of Embodiment 17, wherein formulating the first substrate layer further comprises formulating the first substrate layer to comprise at least one of titanium, molybdenum, zirconium, and hafnium.

Embodiment 19

The method of Embodiment 18, wherein formulating the first substrate layer to comprise at least one of titanium, molybdenum, zirconium, and hafnium comprises formulating the first substrate layer to comprise at least one of zirconium and molybdenum.

Embodiment 20

The method of Embodiment 19, further comprising selecting at least one of the first semiconductor layer and the at least one additional semiconductor layer to comprise gallium nitride (GaN).

Embodiment 21

The method of any one of Embodiments 1 through 20, wherein forming the first substrate layer over the surface of the first semiconductor layer comprises depositing the first substrate layer over the surface of the first semiconductor layer at a temperature of about 900° C. or less.

Embodiment 22

The method of any one of Embodiments 1 through 21, wherein forming the first substrate layer over the surface of the first semiconductor layer comprises depositing the first substrate layer over the surface of the first semiconductor layer using at least one of a physical vapor deposition process, a sputtering process, a spin-on deposition process, an electroless plating process, and an electrical plating process.

Embodiment 23

A semiconductor structure, comprising: a substrate comprising a first substrate layer and at least a second substrate layer; a first semiconductor layer disposed over a surface of the first substrate layer; and at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the first substrate layer; wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 24

The semiconductor structure of Embodiment 23, wherein the first substrate layer comprises a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm⁻¹K⁻¹) and a Vickers hardness of about 3500 MPa or less.

Embodiment 25

The semiconductor structure of Embodiment 23 or Embodiment 24, wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE within about 5% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 26

The semiconductor structure of Embodiment 25, wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE within about 2% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 27

The semiconductor structure of Embodiment 26, wherein at least one of the first substrate layer and the second substrate layer exhibits a CTE within about 1% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

Embodiment 28

The semiconductor structure of any one of Embodiments 23 through 27, wherein the first substrate layer has an average thickness of about one micron (1.0 μm) or less

Embodiment 29

The semiconductor structure of any one of Embodiments 23 through 28, wherein the second substrate layer has an average thickness of at least about ten microns (10.0 μm).

Embodiment 30

The semiconductor structure of Embodiment 29, wherein the second substrate layer has an average thickness of between about ten microns (10.0 μm) and about one hundred microns (100.0 μm).

Embodiment 31

The semiconductor structure of any one of Embodiments 23 through 30, wherein the first semiconductor layer has an average thickness of about five hundred nanometers (500 nm) or less.

Embodiment 32

The semiconductor structure of Embodiment 31, wherein the first semiconductor layer has an average thickness of about one hundred nanometers (100 nm) or less.

Embodiment 33

The semiconductor structure of any one of Embodiments 23 through 32, wherein the at least one additional semiconductor layer has an average total thickness of at least one hundred nanometers (100 nm).

Embodiment 34

The semiconductor structure of Embodiment 33, wherein the at least one additional semiconductor layer has an average total thickness of between about one micron (1.0 μm) and about one hundred microns (100.0 μm).

Embodiment 35

The semiconductor structure of any one of Embodiments 23 through 34, wherein the first semiconductor layer comprises a semiconductor material selected from the group consisting of silicon, germanium, III-V semiconductor material, and II-VI semiconductor material.

Embodiment 36

The semiconductor structure of any one of Embodiments 23 through 35, wherein the first substrate layer comprises a refractory metal.

Embodiment 37

The semiconductor structure of Embodiment 36, wherein the first substrate layer comprises at least one of titanium, molybdenum, zirconium, and hafnium.

Embodiment 38

The semiconductor structure of Embodiment 37, wherein the first substrate layer comprises at least one of zirconium and molybdenum.

Embodiment 39

The semiconductor structure of Embodiment 38, wherein at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises gallium nitride (GaN).

The embodiments of the disclosure described above do not limit the scope of the invention, since these embodiments are merely examples of embodiments of the invention, which is defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternate useful combinations of the elements described, will become apparent to those skilled in the art from the description. Such modifications are also intended to fall within the scope of the appended claims.

Claims

What is claimed is:

1. A method of fabricating a semiconductor structure, comprising:

depositing a first substrate layer over a surface of a first semiconductor layer using a process at a temperature of about 900° C. or less and establishing an ohmic contact between the first substrate layer and the first semiconductor layer;

thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer and establishing an ohmic contact between the second substrate layer and the first semiconductor layer through the first substrate layer;

epitaxially growing at least one additional semiconductor layer over the first semiconductor layer on a side thereof opposite the first substrate layer; and

formulating at least one of the first substrate layer and the second substrate layer to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.

2. The method of claim 1, further comprising formulating the first substrate layer to comprise a material exhibiting a thermal conductivity of at least about twenty watts per meter Kelvin (20 Wm⁻¹K⁻¹) and a Vickers hardness of about 3500 MPa or less.

3. The method of claim 1, wherein the first semiconductor layer comprises a portion of a donor structure, wherein at least one of the first substrate layer and the second substrate layer comprises a composite substrate layer, and wherein the method further comprises transferring the first semiconductor layer to the composite substrate layer from the donor structure after forming the composite substrate layer over the surface of the first semiconductor layer.

4. The method of claim 3, further comprising forming a weakened zone in the donor structure at a predetermined depth from a first surface of the donor structure to define the first semiconductor layer between the first surface of the donor structure and the weakened zone and a residual donor structure between the weakened zone and a second surface of the donor structure on an opposite side of the donor structure from the first surface.

5. The method of claim 4, further comprising separating the first semiconductor layer from the residual donor structure at the weakened zone.

6. The method of claim 1, wherein thermally spraying the second substrate layer on the side of the first substrate layer comprises plasma spraying the second substrate layer on the side of the first substrate layer.

7. The method of claim 1, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 5% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.

8. The method of claim 7, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 2% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.

9. The method of claim 8, wherein formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises formulating the at least one of the first substrate layer and the second substrate layer to exhibit a CTE within about 1% of a CTE of the at least one of the first semiconductor layer and the at least one additional semiconductor layer.

10. The method of claim 1, further comprising forming the first substrate layer to have an average thickness of about one micron (1.0 μm) or less.

11. The method of claim 1, further comprising forming the second substrate layer to have an average thickness of at least about ten microns (10.0 μm).

12. The method of claim 11, further comprising forming the second substrate layer to have an average thickness of between about ten microns (10.0 μm) and about one hundred microns (100.0 μm).

13. The method of claim 1, further comprising selecting the first semiconductor layer to have an average thickness of about five hundred nanometers (500 nm) or less.

14. The method of claim 1, further comprising forming the at least one additional semiconductor layer to have an average total thickness of at least one hundred nanometers (100 nm).

15. The method of claim 14, further comprising forming the at least one additional semiconductor layer to have an average total thickness of between about one micron (1.0 μm) and about one hundred microns (100.0 μm).

16. The method of claim 1, further comprising selecting the first semiconductor layer to comprise a semiconductor material selected from the group consisting of silicon, germanium, III-V semiconductor material, and II-VI semiconductor material.

17. The method of claim 1, wherein depositing the first substrate layer comprises formulating the first substrate layer to comprise a refractory metal.

18. The method of claim 17, wherein formulating the first substrate layer further comprises formulating the first substrate layer to comprise at least one of titanium, molybdenum, zirconium, and hafnium.

19. The method of claim 18, wherein formulating the first substrate layer to comprise at least one of titanium, molybdenum, zirconium, and hafnium comprises formulating the first substrate layer to comprise at least one of zirconium and molybdenum.

20. The method of claim 19, further comprising selecting at least one of the first semiconductor layer and the at least one additional semiconductor layer to comprise gallium nitride (GaN).

21. The method of claim 1, wherein depositing the first substrate layer over the surface of the first semiconductor layer using at least one of a physical vapor deposition process, a sputtering process, a spin-on deposition process, an electroless plating process, and an electrical plating process.

22. The method of claim 1, further comprising depositing the first substrate layer over the surface of the first semiconductor layer without imparting mechanical forces on the first substrate layer.