FR2972292A1 - Semiconductor substrate manufacturing method for forming e.g. semiconductor device, involves forming metal layer, and separating transfer layer from donor structure to form composite substrate comprising transfer layer and metal layer - Google Patents

Abstract

The method involves forming a weakened area (220) in a donor structure (210) to predetermined depth to define a transfer layer (230). A metal layer is formed on a mounting surface, where coefficient of thermal expansion of the metal layer corresponds closely to coefficient of thermal expansion of the transfer layer. The metal layer is allowed to provide sufficient rigidity to provide structural support to the transfer layer. The transfer layer is separated from the donor structure to form a composite substrate comprising the transfer layer and the metal layer.

Description

METAL SUPPORT FOR LAYER TRANSFER AND METHODS FOR FORMER.CE SUPPORT

Field The present invention relates generally to the manufacture of functional substrates for use in the manufacture of semiconductor structures or devices, intermediate structures formed during the fabrication of semiconductor structures or devices, and structures or devices. semiconductors using functional substrates.

Background Substrates that include one or more layers of semiconductor material are used to form a large number of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors). and memory devices) and discrete devices, such as radiation emitting devices (e.g., light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes emitting by the surface (VCSEL)), and radiation detection devices (for example, optical sensors). These semiconductor devices are conventionally layered (i.e., lithographically) formed on and / or in a surface of a semiconductor substrate. Historically, a majority of these semiconductor substrates that have been used in the semiconductor device manufacturing industry have included thin disks or "slices" of silicon-based material. These semiconductor wafers of silicon-based material are fabricated by first forming a large single-crystal silicon ingot generally cylindrical and subsequently cutting the monocrystalline ingot perpendicular to its longitudinal axis to form a plurality of silicon wafers. These silicon wafers can have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 inches) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) Semiconductor material on a main surface of the silicon wafer is generally used to form active devices on the silicon wafer. However, in some device applications, most of the thickness of the silicon wafer may be included in the electrical path of one or more device structures formed from the silicon wafer, such device structures being generally referred to as "vertical" device structures.

"So-called functional substrates" have been developed which include a relatively thin layer of semiconductor material (for example, a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a dielectric material layer (e.g. , silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to allow manipulation by conventional semiconductor device manufacturing equipment), and the semiconductor material and the dielectric material layer may be arranged on a relatively thicker host or base substrate to facilitate manipulation of the overall functional substrate by manufacturing equipment. As a result, the base substrate is often referred to in the "handle" art or "manipulation" substrate. The base substrate may also comprise a semiconductor material other than silicon. A large number of functional substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), III-V semiconductor materials and semiconductor materials of type II-VI. For example, a functional substrate may comprise an epitaxial layer of III-V semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (Al2O3) (which can be called "sapphire"). The epitaxial layer may be formed on the surface of the base substrate by a transfer process from a donor structure, for example a donor substrate or a donor ingot. Transfer from a donor structure may be desirable when the donor material is very valuable or rare. Using such a functional substrate, additional layers of material may be formed and processed (eg, drawn) on the III-V type semiconductor material epitaxial layer to form one or more devices on the functional substrate. However, a mismatch (or difference) in the coefficient of thermal expansion between the epitaxial layer and the base substrate comprising the functional substrate may influence the formation and processing of the additional layers of material. For example, if the thermal expansion coefficient mismatch between the epitaxial layer and the base substrate is large, then the functional substrate may be negatively influenced during the formation of additional layers of materials.

Examples of devices that can take advantage of functional substrates are high power devices and photonic devices, such as light emitting diodes (LEDs) and laser diodes. Figure 1 illustrates a conventional LED. A substrate 110, which may be a functional substrate, includes an n-type layer 120 disposed thereon. An active region 130, which may include multiple layers, such as quantum wells, barrier layers, electron blocking layers (EBLs), etc., is disposed between the n-type layer 120 and a layer of p type 140. This results in an LED formed by the n-type layer 120, the active region 130 and the p-type layer 140. A first contact 160 makes an electrical connection to the n-type layer 120 and a second contact 150 makes another electrical connection to the p-type layer 140. These contacts can be opaque to the wavelength of light emitted by the LED and, therefore, can decrease the overall amount of light that can be obtained from the LED. Thus, only the area between the first contact 160 and the second contact 150 can produce significant amounts of light. The physical arrangement of the second contact 150 with respect to the n-type layer 120 can cause a large current flow between the p-type layer 140 and the n-type layer 120. In addition, the physical arrangement may require that the Both p-type and n-type contacts are disposed on an upper surface of the LED structure, such a physical arrangement may require removal of a portion of the device layers to expose regions for contact. Withdrawing some of the device layers may increase the complexity of device manufacturing, may reduce the area available for light generation and may also decrease the production of devices. In view of the foregoing and for other reasons discussed below, there is a need for a substrate technology that provides a suitable base substrate for a given material from a donor structure. In addition, there is a need for devices and methods that provide a support substrate with a thermal expansion coefficient (CTE) corresponding closely to that of a functional substrate.

Brief Summary The various embodiments of the present invention generally relate to functional substrates and methods for producing functional substrates that provide a suitable base substrate with a CTE that closely matches a CTE of the functional substrate. This summary is proposed to introduce a selection of concepts in a simplified form which are further described in the following detailed description of some exemplary embodiments of the invention. This summary is not intended to identify key features or essential characteristics of the claimed subject matter nor is it intended to be used to limit the extent of the claimed subject matter. In some embodiments, the present invention includes methods of making a semiconductor substrate, the methods of forming a weakened area in a donor structure at a predetermined depth to define a transfer layer between a fixing surface and the weakened area and residual donor structure between the weakened area and a surface opposite the attachment surface. A metal layer is formed on the attachment surface and provides a thermal expansion coefficient (CTE) adapted for the metal layer that closely matches a CTE of the transfer layer, and sufficient rigidity to provide structural support to the transfer. The transfer layer is separated from the donor structure at the weakened region to form a composite substrate comprising the transfer layer and the metal layer. In further embodiments, the present invention includes methods of manufacturing a semiconductor substrate, the methods of forming a weakened area in a donor structure at a predetermined depth to define a transfer layer between a surface of fixation and the weakened area and a residual donor structure between the weakened area and a surface opposite to the attachment surface. An ohmic contact is formed between the transfer layer and a contact layer disposed thereon. A low impedance coupling is formed between a refractory metal layer and the contact layer, the refractory metal layer providing structural support for the semiconductor substrate. The methods also include separating the transfer layer from the donor structure at the weakened area to form a composite substrate comprising the transfer layer, the contact layer, and the refractory metal layer. In other embodiments, the present invention includes a semiconductor substrate comprising a metal support substrate configured to provide sufficient rigidity to the semiconductor substrate. The semiconductor substrate also includes a transfer layer comprising a semiconductor material in contact with an attachment surface of the metal support substrate, the transfer layer being detached from a donor structure comprising the semiconductor material and comprising a weakened area in the donor structure at a predetermined depth of the attachment surface to define the transfer layer between the attachment surface and the weakened area. A CTE adapted to the metal support substrate closely matches a CTE of the transfer layer. Other aspects, details and other combinations of the elements of the embodiments of the invention will be apparent from the following detailed description.

Brief Description of the Drawings The present invention may be more fully understood by reference to the following detailed description of exemplary embodiments of the present invention, which are illustrated in the accompanying drawings, in which: Figure 1 is a sectional drawing simplified cross-section of a conventional LED structure; Figure 2 is a simplified cross-sectional drawing of a donor structure with a weakened area to create a transfer layer; FIGS. 3A and 3B are simplified cross-sectional drawings illustrating the development of a composite substrate with a refractory metal support and a transfer layer according to one or more embodiments of the invention; Figs. 4A to 4C are simplified cross-sectional drawings illustrating the development of a composite substrate with a refractory metal support, a transfer layer and a contact layer therebetween in one or more embodiments; FIGS. 5A to 5C illustrate a composite substrate with an n-doped gallium nitride (GaN) transfer layer and a photonic device formed on the composite substrate according to one or more embodiments of the invention; FIGS. 6A to 6C illustrate a composite substrate with a p-doped gallium nitride (GaN) transfer layer and a photonic device formed on the composite substrate according to one or more embodiments of the invention; Figs. 7A to 7C illustrate a composite substrate with a silicon carbide transfer layer (SiC) and a high power electronic device formed on the composite substrate according to one or more embodiments of the invention; and Figs. 8A-8D illustrate a composite substrate with an n-doped gallium nitride (GaN) transfer layer and a photonic device formed on the composite substrate, which is inverted to form an upward n-layer photonic device in accordance with a or more embodiments of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The illustrations presented herein are not intended to be actual views of a particular material, device or process, but are merely idealized representations that are used to describe embodiments of the present invention. It should be understood that any reference in this document to an element using a designation such as "first", "second", etc. does not limit the quantity or order of these elements, unless this limitation is explicitly stated. Instead, these designations may be used in this document as a convenient method of distinguishing between two or more element elements or instances. Thus, a reference to first and second elements does not mean that only two elements can be used or that the first element must precede the second element in a certain way. In addition, unless otherwise specified, a set of elements may include one or more elements. The elements described herein may include multiple instances of the same element. These elements can generically by a designator be indicated numerically (eg, 110) and indicated the numerical indicator followed specifically by an alphabetic designator (eg, 110A) or a numerical indicator preceded by a "dash" ( for example, 110-1). To facilitate the following description, for the most part, element number indicators begin with the number of the drawing on which elements are introduced or examined most completely. Thus, for example, the item identifiers in Fig. 1 will mainly be in lxx numeric format and the elements in Fig. 4 will be mainly in 4xx numeric format.

The following description provides specific details, such as types of materials and processing conditions, to provide a thorough description of embodiments of the present invention and their implementation. However, one skilled in the art will appreciate that the embodiments of the present invention can be practiced without using these specific details and in conjunction with conventional manufacturing techniques. In addition, the description given herein does not form a complete process flow for the manufacture of a semiconductor device or system. Only the actions and process structures necessary to understand the embodiments of the present invention are described in detail in this document. The materials described herein may be formed (e.g., deposited or developed) by any suitable technique including, but not limited to, spin coating, doctor blade coating, Bridgeman and Czochralski treatment. , chemical vapor deposition ("CVD"), plasma enhanced chemical vapor deposition ("PECVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, or physical phase deposition steam ("PVD"). Although the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three-dimensional configurations.

Terms such as "horizontal" and "vertical", as used herein, define relative positions of elements or structures with respect to a main plane or a major surface of a semiconductor structure (for example, for example, a semiconductor wafer, a chip, a substrate, etc.), regardless of the orientation of the semiconductor structure, and are orthogonal dimensions interpreted with respect to the orientation of the described structure. As used herein, the term "vertical" refers to and includes a dimension substantially perpendicular to the major surface of a semiconductor structure, and the term "horizontal" refers to a dimension substantially parallel to the major surface of the semiconductor structure. semiconductor structure. As used herein, the term "semiconductor structure" refers to and includes any structure that is used for the formation of a semiconductor device. Semiconductor structures include, for example, chips and semiconductor wafers (for example, support substrates and device substrates), as well as composite assemblies or structures that include two chips and / or semi-wafers. -conductors or more integrated three-dimensionally with each other. Semiconductor structures also include fully-manufactured semiconductor devices, as well as intermediate structures formed during the fabrication of semiconductor devices. The semiconductor structures may include conductive materials, semiconductor materials, non-conductive materials (e.g., electrical insulators), and combinations thereof. As used herein, the term "treated semiconductor structure" includes any semicircle structure comprising one or more less partially formed structures. The semiconductors treated are a semiconductor substructure, and all semiconductors treated are semiconductor structures. As used herein, the term "III-V semiconductor" refers to and includes any semiconductor material that is at least predominantly composed of one or more elements of Group IIIA of the present invention. periodic table (e.g., B, Al, Ga, In and Ti) and one or more members of the group VA of the periodic table (e.g., N, P, As, Sb and Bi). Unless otherwise specified, as used herein, the term "coefficient of thermal expansion", when used in connection with a material or structure, refers to the average linear thermal expansion coefficient of the material or material. the structure at room temperature. As used herein, the term " functional substrate ", in its meaning, refers to and refers to any substrate comprising two or more layers of material. which is intended to be used as a substrate for the manufacture of one or more semiconductor devices thereon. Functional substrates include, as nonlimiting examples, semiconductor-on-insulator substrates. As used herein, the term "sufficient rigidity" refers to a stiffness for a semiconductor structure that provides sufficient rigidity for structural damage due to plastic or elastic deformation not to occur in the structure. the semiconductor structure during further processing or manipulation. As non-limiting examples, this structural damage may include dislocations, cracking, damage to the crystal lattice, buckling, longitudinal buckling, and layer separation.

The various embodiments of the present invention relate to functional substrates and methods for producing functional substrates that provide a suitable base substrate with a CTE that closely matches a CTE of the functional substrate. Embodiments of the invention may have applications in a wide range of silicon, germanium, silicon carbide and III-V semiconductor materials as substrates. For example, the methods and structures of the embodiments of the invention can be applied to nitrides III, arsenides III, phosphides III and antimonides III, in binary, ternary, quaternary and quinary forms.

FIG. 2 is a simplified cross-sectional drawing of a donor structure 210 with a weakened area 220 to create a transfer layer 230. As non-limiting examples, a detachment process described herein may be used. SMART-CUTTM technology. These processes are described in detail, for example, in US Pat. No. RE39,484 to Bruel, U.S. Patent No. 6,303,468 to Aspar and Others, U.S. Patent No. 6,335,258 to Aspar and US Pat. others, U.S. Patent No. 6,756,286 to Moriceau et al., U.S. Patent No. 6,809,044 to Aspar et al., U.S. Patent No. 6,946,365 to Aspar and others, U.S. Patent No. 7,531,428 to Dupont, U.S. Patent No. 6,858,107 to Ghyselen and others, and U.S. Patent No. 6,867,067 to Ghyselen and others. However, it should be understood that other suitable processes for manufacturing a semiconductor wafer of a composite material that include the use of predetermined weakened areas could also be used. To perform this detachment process, a predetermined weakened zone 220 may be formed in the donor structure 210. FIG. 2 shows the use of SMART-CUTTM technology in which atomic species 250, such as one or more hydrogen, helium ions, or other inert gas ions are implanted through a fixation surface 240 in a dose and with an energy to create the weakened zone 220 in the donor structure 130. The weakened zone 220 is substantially parallel to the main attachment surface 240 and at a predetermined depth based on the parameters of the atomic species implantation process. The transfer layer 230 is thus formed between the attachment surface 240 and the weakened area 220. In addition, a residual donor structure is formed between the weakened area 220 and a surface opposite the attachment surface 240. The donor structure 210 comprises a semiconductor material and, in some embodiments, may include silicon, germanium, group III nitride (eg, GaN, InGaN, AlGaN), and SiC. The semiconductor material may be undoped or, for some applications, doped n + or p +. The semiconductor may be a self-supporting semiconductor wafer as shown in Figure 2 or a template structure, for example, GaN on a sapphire base. The donor structure 210 may also comprise at least a portion of an ingot (or preform) of semiconductor material and, in some embodiments, said at least a portion of the ingot (or preform) may comprise silicon, germanium, a Group III nitride (eg, GaN, InGaN, AlGaN), and SiC. The ingot (or preform) may comprise a structure such as those described in U.S. Patent No. 6,858,107 to Ghyselen and others and U.S. Patent No. 6,867,067 to Ghyselen and others. If the donor structure 210 is a nitride material III, the polarity of the implanted surface should be considered to determine the polarity of the final composite substrate. As a non-limiting example, a GaN donor structure may be used to develop a polar gallium face or a polar nitrogen face for subsequent treatment. As another non-limiting example, an InGaN donor structure may be used to develop a polar metal face or a polar nitrogen face for subsequent treatment. For a conventional layer transfer on a support semiconductor wafer, a process of lia_on __e_scene ~ le ~ net uti] _is followed-dom la_sli ~ isi ~ n of the semiconductor wafer implanted by means of a certain heat treatment . The binding process requires that the surfaces to be bonded be of high quality to avoid defects of large areas (non-transferred areas), whereas the thermal expansion coefficients (CTE) of the two semiconductor wafers should not be too different for avoid a slice breakage as a result of the splitting process. For some applications, a conductive connection of a semiconductor material to a conductive substrate is desirable for constructing vertical device structures, i.e., devices that have the active area near the surface of the device. semiconductor layer and a contact area near the interface of the semiconductor with the substrate or with the carrier semiconductor wafer. However, such an approach is difficult to achieve since today most bonding processes involve layers of silicon dioxide (SiO2) on the bonding faces for high quality bonding. However, the one insulator will make electrical conduction more, will prevent efficient heat dissipation of the device to the substrate. Accordingly, the embodiments of the present invention provide structures and processes for providing a support structure that can perform heat dissipation and with a CTE that closely matches a CTE of the transfer layer 230. In one embodiment, an electrical contact may be developed, for example, ohmic or Schottky contact, between the SiO 2 layer is difficult, if not impossible, and transfer and a metal support layer. SZn - ohmic contact (ie, contact with voltage-independent resistance) is developed at a metal-semiconductor junction if the height of the Schottky barrier is zero or negative. In other words, an ohmic contact will have current characteristics as a function of the voltage that are substantially linear and symmetrical. In such cases, the carriers are free to flow in or out of the semiconductor so that there is minimal resistance across the ohmic contact. FIGS. 3A and 3B are simplified cross-sectional drawings illustrating the development of a composite substrate with a refractory metal layer 280 and a transfer layer 230 according to one or more embodiments of the invention. The refractory metal layer 310 may be formed with a thickness sufficient to form a metal support substrate with sufficient rigidity to provide structural support for the transfer layer 230. The refractory metal layer 310 is formed on the attachment surface 240 by a process suitable for making an electrical contact, for example an ohmic contact, between the refractory metal layer 310 and the transfer layer 230. Before the deposition of the refractory metal layer 310, the surface of the semiconductor may require treatment to remove any surface oxide which may impair the quality of the refractory metal layer 310, for example, a thin gallium oxide layer may have to be removed before depositing the refractory metal layer 310 and for the formation of an electrical contact, by example, ohmic contact. The structure of the donor structure 210 and the metal support substrate 310 can be placed in a furnace (not shown) and heated so that the weakened zone 220 can be further weakened. With the weakening, the transfer layer 230 and the associated metallic support substrate 310 can be separated from the donor structure at the weakened zone 220. Instead of providing thermal energy, additional energy in other forms for example, a mechanical energy, a chemical energy, or a combination of thermal, mechanical and chemical energies could be used during the weakening and detachment actions.

The structures thus formed after separation are a residual donor structure (not shown) capable of providing other thin transfer layers and a composite substrate 450 comprising the metal support substrate 310 and the transfer layer 230.

As non-limiting examples, the transfer layer 230 may have a thickness of less than 1000 nanometers and more likely a thickness of about 500 nanometers. As shown in FIG. 3B, the composite substrate 450 can be inverted for further processing on the exposed surface of the transfer layer 230. Prior to performing other processing steps, the composite substrate 450 can receive a surface treatment , such as, for example, polishing, cleaning or a combination thereof. Additional processing may include, as a non-limiting example, the addition of device structures to the composite structure. The device structures may include multiple layers of doped semiconductor material, undoped semiconductor material, and active areas as is known in the art for producing electronic elements, photonic elements, and combinations of those -this.

FIGS. 4A to 4C are simplified cross-sectional drawings illustrating the development of a composite substrate 450 with a refractory metal layer 310, a transfer layer 230 and a contact layer 410 therebetween according to one or more embodiments of the invention. 'invention. In the embodiments of Figs. 4A to 4C, a metal contact layer 410 is deposited on the attachment surface 240. This contact layer 410 is configured to provide ohmic contact which is of high quality (e.g. resistance) between the transfer layer 230 and the contact layer 410. As a non-limiting example, if the donor material is n + doped GaN, then the metal contact layer may be, for example, a Ti stack. / Al / Ni / Au or a stack of Ti / Al when the use of gold can be detrimental to the performance of the device. As another non-limiting example, if the donor material is p + doped GaN, then the metal contact layer may be, for example, a stack of Ni / Au or Ni (the first metal in the list being the closer to the semiconductor). Before the deposition of the contact layer 410, the surface of the semiconductor may need to be treated to remove any surface oxide or other surface layers that may adversely affect the quality of the contact layer 410, for example Thin gallium oxide may need to be removed prior to the deposition of the contact layer 410. The contact layer 410 may be deposited by spray coating, thermal evaporation, electron beam evaporation, etc. In some embodiments, the contact layer 410 may also function as a seed metal for the subsequent deposition of a thick metal support, such a seed can improve adhesion with the transfer layer 230 and improve the properties. electrical conduction with the transfer layer 230. The contact layer 410 may be as thin as some monolayers. In some embodiments, the contact layer 410 may have a thickness of about one nanometer to about 50 nanometers. As shown in FIG. 4B, a refractory metal layer 310 is formed on the contact layer 410 by a suitable process for performing a low impedance coupling between the refractory metal layer 310 and the contact layer 410. In embodiments of FIGS. 4A to 4C, the combination of the contact layer 410 and the refractory metal layer 310 may be referred to herein as metallic support substrate 310A. The entire structure of the donor structure 210 and the metal support substrate 310A can be placed in a furnace (not shown) and heated so that the weakened area 220 can be further weakened. With the weakening, the transfer layer 230 and the associated metal support substrate 310A can be separated from the donor structure at the weakened zone 220. Instead of providing thermal energy, additional energy in other forms for example, mechanical energy, chemical energy, or a combination of thermal, mechanical, and chemical energy could be used during the decay and detachment steps.

The capsules thus formed after its separation are a residual donor structure (not shown) capable of providing other thin transfer layers and a composite substrate 450 comprising the refractory metal layer 310, the contact layer. 410 and the transfer layer 230. As non-limiting examples, the transfer layer 230 may have a thickness of less than 1000 nanometers and more likely a thickness of about 500 nanometers. As shown in FIG. 4C, the composite substrate 450 can be inverted for further processing on the exposed surface of the transfer layer 230. Prior to performing other processing steps, the composite substrate 450 can receive a surface treatment , such as, for example, polishing, cleaning or a combination thereof. The additional processing may include, as a non-limiting example, the addition of device structures to the composite structure. The device structures may include multiple layers of doped semiconductor material, undoped semiconductor material, and active areas as known in the art to produce electronic elements, photonic elements, and combinations of those -this. The residual donor structure may be reused to form additional composite structures by repeating the process as illustrated in Figure 2 and Figures 3A and 3B or Figure 2 and Figures 4A and 4C. Prior to performing other processing steps, the residual donor structure may need to be surface treated, such as, for example, polishing, cleaning, or a combination thereof, in order to restore the surface quality of the surface. 'origin. In both embodiments of FIGS. 3A and 3B and FIGS. 4A to 4C, the refractory metal layer 310 should be able to remain chemically and physically stable at sufficiently high temperatures for subsequent processing, such as, for example, heating. for separation and growth / deposition / treatment of additional layers. As a non-limiting example, for subsequent GaN layer addition treatment, the refractory metal layer 310 should be capable of withstanding temperatures in the range of about 900 ° C to about 1100 ° C. In addition, for subsequent treatment, the refractory metal layer 310 should be able to withstand the chemical environment in the additional growth / deposition / processing equipment. The refractory metal layer 310 may be sufficiently thick to provide sufficient rigidity to provide structural support for the transfer layer 230. As non-limiting examples, the refractory metal layer 310 may have a thickness between about 10 microns and about 150 microns. microns and more likely a thickness between about 10 microns and about 20 microns. As non-limiting examples, the refractory metal layer 310 may be deposited by spray coating, plasma spray coating or deposition methods (e.g., electroless chemical deposition and electroplating). The refractory metal layer 310 may have a matched CTE that closely matches a CTE of the transfer layer 230, for example, to avoid stress and cracking of subsequent growth patterns. Table 1 lists CTE values for certain non-limiting materials for the transfer layer 230 and the refractory metal layer 310. Material CTE (10-6 / ° K) GaN 5.6 SiC 4.5 Tungsten 4.5 Molybdenum 5 , 4 Hafnium 6.1 Rhenium 6.2 Tantalum 6.5 Zirconium 5.9 TABLE 1

In some embodiments, the CTE of the refractory metal layer 310 may be within about 20% of the CTE, or within about 10% of the CTE of the semiconductor material of the transfer layer 230. Thus, for these embodiments, tungsten, molybdenum and zirconium used as the refractory metal layer 310 would closely match a SiC transfer layer 230 and, in some embodiments, particularly tungsten. Similarly, for these embodiments, zirconium, hafnium, rhenium and tantalum used as the refractory metal layer 310 would closely match a GaN transfer layer 230 and, in some embodiments, particularly molybdenum .

Since the semiconductor / metal stack is suitable for the CTE, thick epitaxial layers of semiconductor material can be developed on the stack without cracking in order to complete the fabrication of a device structure. If necessary, a thick metal wafer of the same type as the sputtered / evaporated metal layer can serve as a support for increasing the rigidity of the stack without losing its advantageous properties. FIGS. 5A to 5C illustrate a 450N composite substrate with a 230N-doped gallium nitride (GaN) transfer layer and a photonic device formed on the 450N composite substrate according to one or more embodiments of the invention. In FIG. 5A, the composite substrate 450N comprises a 230N transfer layer of an n-doped GaN layer which is polar Ga on a Ti / Al / Ni / Au contact layer 410 on a refractory metal layer 310 (by example, molybdenum). The transfer layer 230 may be provided by either of a GaN n + substrate or GaN n + (polar Ga) on a sapphire jig. A transfer from the GaN n + substrate can be carried out by ion implantation in the polar-face substrate n. The deposition of the contact layer 410 and the refractory metal layer 310 is followed by a transfer layer separation between the transfer layer 230 and the substrate. The transfer for GaN n + on a sapphire would be performed with a double transfer to provide a layer of GaN n + Ga of polar on the composite substrate.

Figure 5B illustrates an LED structure, as a type of photonic device, composed of an additional semiconductor device on the 450N composite substrate. The LED structure comprises an active region, which may comprise multiple layers, such as, for example, quantum wells disposed on the doped GaN transfer layer --n --- 230N. One or more p-type layers 520 are disposed on the active layer 510. The result is an LED formed by the n-doped GaN transfer layer 230N, the active layer 510 and the p-type layer 520. A contact layer 530 makes an electrical connection to the p-type layer 520. The resulting LED structure provides a vertical diode structure, which, as opposed to the diode structure of Fig. 1, does not require that an additional electrical connection be exposed on the upper layers for a connection to the n side of the diode. FIG. 5C illustrates another optional action to include a thick metal substrate 550. The thickness of the support metal can be increased by a metal-metal bond between the deposited metal refractory layer 310 and the thick metal substrate 550, this thickening of the support metal can be made prior to formation of the device layer if the thick metal substrate 550 is capable of withstanding corrosive reactor growth conditions. FIGS. 6A to 6C illustrate a composite substrate 450P with a 230P doped gallium nitride (GaN) transfer layer and a photonic device formed on the composite substrate 450P according to one or more embodiments of the invention. The layers in the embodiments of Figs. 6A-6C are similar to those of the embodiments of Figs. 5A-5C, except that the transfer layer 230 comprises a 230P p-doped GaN transfer layer. A corresponding contact layer 410 may be, for example, Ni / Au.

Figure 6_B illustrates an LED structure as a photonic device that includes an active region, which may include multiple layers, such as, for example, quantum wells disposed on the 230P p-doped GaN transfer layer. One or more n-type layers 620 are disposed on the active layer 610. The result is an LED formed by the p-doped GaN transfer layer 230P, the active layer 610 and the n-type layer 620. A contact layer 630 makes an electrical connection to the n-type layer 620. The resulting LED structure provides a vertical diode structure, which, as opposed to the diode structure of Fig. 1, does not require that an additional electrical connection be exposed on the upper layers for a connection to the p side of the diode. FIG. 6C illustrates an additional optional action to include a thick metal substrate 650. The thickness of the support metal can be increased by a metal-metal bond between the deposited metal refractory layer 310 and the thick metal substrate 650, this thickening of the support metal can be made prior to formation of the device layer if the thick metal substrate 650 is capable of withstanding corrosive reactor growth conditions. FIGS. 7A to 7C illustrate a composite substrate 450S with a 230S silicon carbide (SiC) transfer layer and a high power electronic device formed on the composite substrate 450S according to one or more embodiments of the invention. The composite substrate 450S comprises the SiC transfer layer 230S on the refractory metal layer 310, for example 310T tungsten. As can be seen from FIG. 1, the SiC transfer layer 230 and the 310T tungsten refractory metal layer are CTE adapted so that the SiC transfer layer 230 and the high power electronic device formed on this one undergo only few effects of constraint, or none of the effects of stress due to the absence of correspondence in the CTE during the formation of the device.

As illustrated in Fig. 7B, a power device may be formed with one or more power device layers 710 on the 230S SiC transfer layer. A contact layer 730 provides an electrical connection to the power device layer 710. Figure 7C illustrates an optional additional action to include a thick metal substrate 750. The thickness of the support metal can be increased by a metal-to-metal bond between the deposited refractory metal layer 310 and the thick metal substrate 750, this thickening of the metal support can be performed prior to formation of the device layer if the thick metal substrate 750 is capable of withstanding corrosive reactor growth conditions. FIGS. 8A-8D illustrate a composite substrate with an n-230 doped gallium nitride nitride (GaN) transfer layer and a photonic device formed on the composite substrate 450, which is inverted to form an upward n-layer photonic device according to one or more embodiments of the invention. The layers in the embodiment of Figure 8A are similar to those of the embodiments of Figure 3B. However, in contrast to the embodiments of Figs. 4A-6C, the embodiments of Figs. 8A-8D do not include a contact layer adjacent to the composite substrate 450. Instead, a photonic device, such as, for example, an LED, may be formed on the semiconductor material 230, which is formed as a n-230N doped gallium nitride (GaN) transfer layer in this embodiment. As shown in FIG. 8B, the photonic device may comprise an active region 810, which may comprise multiple layers, such as, for example, quantum wells disposed on the 230N n-type gallium nitride (GaN) transfer layer. . One or more p-type GaN layers 820 may be disposed on the active layer 810. This results in an LED formed by the 230N n-type gallium nitride nitride (GaN) transfer layer, the active layer 810 and the p type 820. The photonic device structure being formed, a contact layer 840, such as those described above, can be formed on the p-type GaN layer 820 by making an electrical connection with the p-type layer 820. A heat sink, such as, for example, a thick metal substrate 850 may be formed on the contact layer 810. The resulting structure may be considered as turned over. The returned configuration is illustrated in Figure 8C. The refractory metal 310 can then be removed to expose the 230N n-type gallium nitride (GaN) transfer layer. The resulting LED structure provides a vertical diode structure, which, as opposed to the diode structure of Fig. 1, does not require an additional electrical connection to be exposed on the upper layers for connection to the p side of the diode . Instead, contact with the p-side of the diode can be made through the contact layer 840 and the thick metal substrate 850. A contact layer 850 can be formed to provide an electrical connection to a transfer layer. gallium nitride (GaN) doped n 230N.

Claims (17)

REVENDICATIONS1. Method of manufacturing a semiconductor substrate, Claims 1. A method of manufacturing a semiconductor substrate comprising forming a weakened area in a donor structure at a predetermined depth to define a transfer layer between a fixation surface and the weakened zone and a residual donor structure between the weakened area and a surface opposite to the attachment surface; forming a metal layer on the attachment surface, wherein the metal layer provides: a thermal expansion coefficient (CTE) adapted for the metal layer that closely matches a CTE of the transfer layer; and sufficient rigidity to provide structural support to the transfer layer; and separating the transfer layer from the donor structure at the weakened region to form a composite substrate comprising the transfer layer and the metal layer. The method of claim 1, wherein forming the metal layer on the attachment surface further comprises forming the metal layer to provide ohmic contact between the metal layer and the transfer layer. The method of claim 1, wherein forming the metal layer on the attachment surface further comprises forming the metal layer to make a Schottky contact between the metal layer and the transfer layer. The method of claim 1, wherein forming the weakened area in the donor structure comprises forming the weakened zone in at least a portion of a semiconductor material ingot or a semi-material preform. -driver. The method of claim 1, further comprising forming the metal layer by forming a contact layer on the attachment surface, wherein the contact layer makes electrical contact with the transfer layer; and forming a refractory metal layer conductively coupled to and over the contact layer, wherein the refractory metal layer is relatively thick compared to the contact layer, provides sufficient rigidity and provides the adapted CTE. The method of claim 1, wherein the adapted CTE is within 10% of the CTE of the transfer layer. The method of claim 1, further comprising selecting the donor structure from the group consisting of silicon, germanium, SiC, GaN, AlN, InGaN and GaAs. The method of claim 7, wherein the selection of the donor structure further comprises selecting the donor structure with a sapphire base attached to the donor structure opposite to the attachment surface. The method of claim 1, further comprising selecting the donor structure to include SiC and selecting the metal layer to include tungsten or molybdenum. . The method of claim 9, further comprising selecting the donor structure to include SiC and selecting the metal layer to include tungsten. The method of claim 1, further comprising selecting the donor structure to include GaN and selecting the metal layer to include molybdenum, zirconium, hafnium, rhenium or tantalum. The method of claim 11, further comprising selecting the donor structure to include GaN and selecting the metal layer to include molybdenum. The method of claim 1, further comprising forming additional semiconductor structures in the transfer layer, on the transfer layer, or a combination thereof. A semiconductor substrate, comprising: a metal support substrate configured to provide sufficient rigidity to the semiconductor substrate; and a transfer layer comprising. a semiconductor material in contact with an attachment surface of the metal support substrate, wherein the transfer layer is detached from a donor structure comprising the semiconductor material and comprising a weakened area in the donor structure at a predetermined depth of the attachment surface for defining the transfer layer between the attachment surface and the weakened area; wherein a thermal expansion coefficient (CTE) matched to the metal support substrate closely corresponds to a CTE of the transfer layer. The semiconductor substrate of claim 14, wherein the metal support substrate comprises: a contact layer adjacent to the attachment surface and providing conductive contact with the transfer layer; and a refractory metal layer conductively coupled to and adjacent the contact layer, wherein the refractory metal layer provides sufficient rigidity to provide structural support for the semiconductor substrate and provides the adapted CTE. The semiconductor substrate of claim 15, wherein the conductive contact comprises an ohmic contact. The semiconductor substrate of claim 15, wherein the conductive contact comprises a Schottky contact. The method according to claim 15, wherein the adapted CTE is within 20% of the CTE of the transfer layer. The semiconductor substrate of claim 15, wherein the transfer layer comprises SiC and the refractory metal layer comprises at least one of tungsten, molybdenum and zirconium. The semiconductor substrate of claim 15, wherein the transfer layer comprises GaN and the refractory metal layer comprises at least one of zirconium, hafnium, rhenium and tantalum. The semiconductor substrate of claim 15, wherein the transfer layer comprises n-doped GaN and the contact layer comprises at least one of titanium, aluminum, nickel and gold. The semiconductor substrate of claim 15, wherein the transfer layer comprises p-doped GaN and the contact layer comprises at least one of nickel and gold. The semiconductor substrate of claim 15, further comprising a thick metal substrate conductively coupled to and adjacent to the refractory metal layer. 24. The semiconductor substrate according to claim 14, wherein the transfer layer comprises n-doped GaN and further comprises layer-integrated layers on the transfer layer to form at least one photonic element. The semiconductor substrate of claim 14, wherein the transfer layer comprises p-doped GaN and further comprises semiconductor device layers integrated on the transfer layer to form at least one photonic element. The semiconductor substrate of claim 14, wherein the transfer layer comprises SiC and further comprises semiconductor device layers integrated on the transfer layer to form at least one high power electronic device.