EP1535346A2 - Quasi-vertical power semiconductor device on a composite substrate - Google Patents

Quasi-vertical power semiconductor device on a composite substrate

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Publication number
EP1535346A2
EP1535346A2 EP03780259A EP03780259A EP1535346A2 EP 1535346 A2 EP1535346 A2 EP 1535346A2 EP 03780259 A EP03780259 A EP 03780259A EP 03780259 A EP03780259 A EP 03780259A EP 1535346 A2 EP1535346 A2 EP 1535346A2
Authority
EP
European Patent Office
Prior art keywords
layer
support substrate
sic
semiconductor material
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03780259A
Other languages
German (de)
French (fr)
Inventor
François Templier
Léa Di Cioccio
Thierry Billon
Fabrice Letertre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1535346A2 publication Critical patent/EP1535346A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a quasi-vertical power semiconductor device on a composite substrate.
  • the manufacturing channels for Sic-based power devices are currently carried out on massive monocrystalline Sic substrates, of polytype 4H and of low electrical volume resistivity.
  • This type of substrate allows the manufacture of electronic devices, for example, of the Schottky diode, PIN diode or transistor type such as power MOS, JFET or MESFET, components using during their operation a vertical passage of electric current between the front face. and the back side of this substrate.
  • Figure 1 is a cross-sectional view of such a power semiconductor device.
  • the diode is produced from a solid substrate 1 of n + type Sic on which two layers of SiC 2 and 3 have been successively epitaxied.
  • Layer 2 is n + doped and layer 3 is n " doped.
  • the rear face of substrate 1 is metallized to provide ohmic contact 4.
  • a metal pad 5 is deposited on layer 3 to make a Schottky contact.
  • a localized implantation of the layer 3 provides a p-type zone 6 ensuring peripheral protection.
  • This vertical design of the device is particularly suitable for discrete components which, after collective manufacture on an entire slice of monocrystalline Sic, are separated from each other by cutting chips.
  • the electrical connection of these chips with the housing is then made in a standard manner by contacting the front and rear faces, in the same way as for discrete silicon components.
  • the advantages of the "solid substrate” sector consist in the vertical structure of the device (ease of admission of high currents and assembly in a housing similar to the silicon standard) and in the fact that the substrate allows homoepitaxy of SiC.
  • the disadvantages of this sector are the cost, the small diameter of the substrates, their low availability and the impossibility of integrating the components in a system approach.
  • An alternative route of substrates for the above applications is the use of composite substrates having a semiconductor thin film bonded to a substrate and obtained by Smar-Cut method. "This method is disclosed in FR-A-2 681 472 (corresponding to US Pat. No. 5,374,564).
  • the thin layer and the initial substrate can be made of different materials thanks to the complete freedom offered for the production of composite substrates by this process. among others, to produce substrates called SiCOI (from the English "Sic On Insulator") made up of a thin layer of Sic glued on an electrically insulating substrate seen from the thin layer, like, for example, an oxidized silicon substrate .
  • the thickness of the monocrystalline Sic layer is less than 1 ⁇ m, typically 0.5 ⁇ m.
  • This SiCOI structure enables electrical components to be produced using the transferred thin layer as an active layer.
  • the electronic components are confined in this very thin layer, with the inherent advantages and disadvantages.
  • the advantages are constituted by the simplicity of the manufacturing process and by the fact that, the components being isolated, it is possible to produce integrated circuits.
  • This sector has the following drawbacks. Since the electrical contacts exit on the same side of the component, it is therefore not possible to integrate them into standard silicon packages.
  • the thin thickness of the thin film limits the performance of the components in terms of current flow through the thin film.
  • an electronic device with vertical conduction is proposed, produced on a composite substrate of the semiconductor-over-insulator type and comprising two electrical contacts taken on the front face with electrical connection of one of the contacts to an electrically conductive support substrate, after opening of the insulating layer.
  • the subject of the invention is therefore a power semiconductor device produced in epitaxial semiconductor material on a stacked structure, characterized in that:
  • the stacked structure comprises a layer of semiconductor material transferred onto a first face of a support substrate and secured to the support substrate by means of an electrically insulating layer, the support substrate comprising means of electrical conduction between said first face and a second face, the layer of transferred semiconductor material serving as epitaxial support for the epitaxial semiconductor material, means for electrical connection of the device are provided, on the one hand on the epitaxial semiconductor material, and on the other hand, on the second face of the support substrate, an electrical connection through the electrically insulating layer and said means of electrical conduction of the support substrate electrically connecting the epitaxial semiconductor material to the electrical connection means provided on the second face of the support substrate.
  • the means of electrical conduction of the support consist of the support substrate itself which is made of electrically conductive material.
  • the epitaxial semiconductor material can comprise several different doping layers.
  • the support substrate is overdoped on the side of the interface with the electrically insulating layer.
  • the electrical conduction means of the device can comprise at least one Schottky contact and / or at least one ohmic contact.
  • the support substrate is made of semiconductor material, chosen for example from SiC, GaN, AIN, Si, GaAs, ZnO and Ge.
  • the electrically insulating layer can be of a material chosen from Si0 2 , Si 3 N 4 and diamond.
  • the thin layer of transferred semiconductor material can be of a material chosen from SiC, GaN, AIN, Si, ZnO and diamond.
  • the epitaxial semiconductor material can be chosen from SiC, GaN, AlGaN, InGaN and diamond.
  • the invention also relates to a semiconductor circuit, characterized in that it combines, on the same stacked structure at least one power semiconductor device as defined above and at least one semiconductor device which is not electrically connected to the second face of the support substrate.
  • FIG. 1, already described, is a cross-section view of a power semiconductor device according to the prior art
  • FIG. 2 is a cross-section view of a power semiconductor device according to the invention
  • FIGS. 3A to 3J are cross-sectional views illustrating a method for producing a power semiconductor device according to
  • Figure 4 is a cross-sectional view of another power semiconductor device according to the invention
  • Figure 5 is a cross-sectional view of a semiconductor device can be associated with a power semiconductor device according to the invention in order to produce an integrated circuit.
  • Figure 2 is a cross-sectional view of a power semiconductor device according to the invention.
  • the device is manufactured on the front face of a composite substrate 10.
  • the support substrate 11 is made of silicon and supports a silicon oxide layer 12 and an SiC layer 13 transferred, for example, by the Smart-Cut method ", on the support substrate 11 and integral with the supporting substrate by the oxide layer 12.
  • the transferred Sic layer 13 serves as an epitaxial support for the n + doped SiC 14 layer and for the n " doped SiC 15 layer.
  • the inventors of the present invention have succeeded in carrying out epitaxies of SiC on this composite substrate unexpectedly.
  • the silicon oxide did not deteriorate for epitaxy temperatures slightly lower than the melting temperature of the silicon and the epitaxies obtained are of good quality, comparable to epitaxies on solid SiC.
  • the device also comprises a Schottky contact 16 disposed on the SiC layer 15 and an ohmic contact 17 disposed on the rear face of the support substrate 11.
  • Ohmic contacts 18 are arranged on the upper face of the SiC layer 14. They allow a electrical connection of the SiC layer 14 with the ohmic contact 17 on the rear face thanks to metallizations 19 deposited on the ohmic contacts 18, making contact with the support substrate 11 through the oxide layer 12, and thanks to the support substrate 11 which is sufficiently conductive. Of more, the contact between the metallizations 19 and the support substrate 11 is an ohmic contact.
  • This power device can therefore be described as a quasi-vertical device.
  • FIGS. 3A to 3J are cross-sectional views illustrating a method for producing a power semiconductor device according to the invention.
  • the device produced in this example comprises layers of SiC epitaxially grown on a layer of SiC transferred onto a silicon support substrate.
  • FIG. 3A shows a composite substrate 100 formed of a silicon support substrate 101 supporting a layer of silicon oxide 102 used for bonding a layer of transferred SiC 103.
  • the transferred SiC layer 103 serves as an epitaxial support for the SiC layer 104 and for the SiC layer 105 epitaxied on the layer 104.
  • the transferred SiC layer 103 has an n doping of the order of 10 17 to 10 19 atoms / cm 3 and a thickness of between 0.5 and 1 ⁇ m.
  • the support substrate 101 has an n doping of the order of 10 20 atoms / cm 3 and a thickness between 200 and 500 ⁇ m.
  • the oxide layer 103 has a thickness of between 2 and 4 ⁇ m, for example 2 ⁇ m.
  • the support substrate 101 can, on the side of the interface with the oxide layer 102, be overdoped if necessary before assembly of the composite substrate 100 in order to facilitate posterior ohmic contact (see FIG. 3G).
  • the SiC layers 104 and 105 are successively epitaxial.
  • the epitaxy is carried out below 1410 ° C. for a support substrate 101 made of silicon.
  • the layer of SiC 104 is doped n + (doping between 5.10 18 and 5.10 20 atoms / cm 3 ) and has a thickness of approximately 4 ⁇ m
  • the layer of SiC 105 is doped n " (doping of the order of 10 16 atoms / cm 3 ) and has a thickness of approximately 6 ⁇ m. This pair of values is given for information for a Schottky diode of the 600 volt type. These values are at adjust according to the desired tensile strength.
  • FIG. 3B relates to a first level of lithography making it possible to define “Mesa” structures by etching the layer of SiC 105 until reaching the layer of SiC 104.
  • the “Mesa” structure allows the voltage withstand of the component and the fact of exposing the layer of SiC 104 will subsequently make it possible to produce an ohmic contact. Etching can be done by plasma.
  • the next step consists in depositing an inorganic layer 106, for example a layer of Si0 2 or Si 3 N, with a thickness of several ⁇ m, for example from 2 to 4 ⁇ m. This layer will have, among other things, the passivation function of the component (see Figure 3C).
  • FIG. 3D relates to a second level of lithography making it possible to define the etching zones of the layers 106, 104 and 103. This is a first step towards making contact with the support substrate 101. This also makes it possible to electrically isolate the component from its neighbors in the case where you want to integrate several on the same circuit.
  • layer 106 is etched.
  • the etching can be obtained by wet etching in HF solution or by plasma etching.
  • the masking resin is then removed and the SiC layers 104 and 103 are then successively etched using the layer 106 as a mask.
  • the etching is done by plasma.
  • the structure obtained is shown in Figure 3D.
  • FIG. 3E relates to a third level of lithography making it possible to define different openings in the layers 102 and 106 for future electrical contacts.
  • FIG. 3E shows the structure obtained after development of the resin layer 107.
  • FIG. 3G relates to a fourth level of lithography making it possible to produce an ohmic contact.
  • the deposited metal can be, Ni or Ti. Its thickness can be between 100 and 500 nm. The deposition can be done by evaporation or sputtering. Lithography makes it possible to define the ohmic contact zones with the layer of SiC 104 at 116 and also the connection to the ohmic contact with the support substrate 101 at 112.
  • Figure 3G shows the structure obtained with etching of the deposited metal and removal of the resin. It shows the metallic deposit 109 connecting the SiC layer 104 to the support substrate 101.
  • the etching of the metal can be done in a conventional manner, for example by wet etching for Ni and Ti or by plasma for W.
  • An annealing is then applied in view to activate the ohmic contact with the SiC of layer 104, in the range between 900 and 1100 ° C for Ni and Ti, in the range between 1000 and 1300 ° C for W. Simultaneously, the ohmic contact with silicon of the support substrate 101 is activated.
  • FIG. 3H relates to a fifth level of lithography making it possible to obtain a Schottky contact.
  • a Schottky contact metal which can be Ti or Ni, is deposited on the structure obtained above, by sputtering or by evaporation, over a thickness of between 100 and
  • a lithography is carried out, then an etching of this metal so as to form Schottky contact pads 108 on the layer of SiC 105.
  • a Schottky contact annealing is then applied, for example, at a temperature between 400 to 600 ° C.
  • a metallization layer 117 is deposited on the rear face of the support substrate 101 (see FIG. 31) in order to make an ohmic contact on the rear face.
  • This layer can be made of Al, Ti or Ni. Annealing may be necessary to improve the ohmic contact.
  • an over-metallization may be necessary to reinforce the metallizations of the front face of the device.
  • FIG. 3J shows an over-metallization 118 reinforcing the Schottky contact pad 108 and an over-metallization 119 reinforcing the deposit 109 ensuring the ohmic contact towards the SiC layer 104 and the connection towards the support substrate 101.
  • This over-metallization can be aluminum, with a thickness between 0.5 and 5 ⁇ m.
  • Figure 3J shows the structure obtained after lithography and etching.
  • a variant of this production method is made possible if the doping of the SiC layer 104 is sufficiently high to allow good ohmic contact with Ti annealed at around 500 ° C.
  • the doping necessary for this is of the order of 5.10 19 atoms / cm 3 or more. This doping is accessible on Sic obtained by epitaxy. It is important to note that such doping cannot be obtained on a solid SiC substrate. However, it is on this substrate that the ohmic contact is made in the prior art. In the case of the present invention, the same metal can be used for Schottky contact and for ohmic contact, with a single annealing at approximately 500 ° C. This variant is implemented from the structure illustrated in FIG. 3F.
  • a single metallic deposit is made, for example, of Ti or Ni or a bilayer of one of these metals and of another metal.
  • a lithography is carried out. It makes it possible to simultaneously define the Schottky pads and the ohmic contact pads. After engraving and annealing to approximately 500 ° C., the structure illustrated in FIG. 3H is obtained directly with one complete level of lithography less (one deposit, one lithography, one etching and one annealing less). The end of the process remains identical with the rear side metallization and possibly an over-metallization.
  • peripheral protections which consist of p-doping zones produced at the periphery of the Schottky contact. These protections can either be carried out by localized implantation, or by an additional epitaxial type p made in the wake of the epitaxial layer of SiC 105, the layer p then being locally etched in the area of the Schottky contact.
  • peripheral protections 120 It is possible to produce these peripheral protections in the context of the present invention, without particular difficulty compared to conventional components of the vertical type.
  • implanted peripheral protections 120 In FIG. 3J, implanted peripheral protections 120 have been shown in broken lines.
  • the invention also allows the production of a device comprising layers of SiC epitaxially grown on a layer of SiC transferred onto a support substrate of SiC.
  • a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate in Sic.
  • the epitaxy is carried out on the transferred SiC layer.
  • As many layers of SiC as necessary are epitaxied.
  • the structure then consists of a support substrate 101 made of SiC, an oxide layer 102, a layer of transferred SiC 103, a first layer of epitaxied SiC 104 and a second layer of epitaxied SiC 105.
  • Epitaxy can be performed above 1410 ° C, typically in the range between 1400 and 1600 ° C.
  • the layer of SiC 104 can be doped n + according to a doping of 10 19 atoms / cm 3 and can have a thickness of approximately 4 ⁇ m.
  • the SiC 105 layer can be doped n " according to a doping of 10 16 atoms / cm 3 and can have a thickness of approximately 6 ⁇ m.
  • the invention also allows the production of a device comprising layers of GaN epitaxially grown on a layer of Sic transferred onto a support substrate of SiC. For this, a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate of SiC. The epitaxy is carried out on the transferred SiC layer. As many layers of GaN as necessary are epitaxied.
  • the structure then consists of a support substrate 101 in SiC, a layer of oxide 102, a layer of transferred SiC 103, a first layer of epitaxial GaN 104 and of a second layer of epitaxial GaN 105.
  • An AIN buffer layer can be interposed between the transferred SiC layer and the GaN to improve epitaxial growth.
  • the support substrate 101 made of SiC can be overdoped as described above.
  • the technique applied is similar to the cases described above, but with adaptations relating to ohmic contacts and GaN etchings instead of SiC.
  • the invention also allows the production of a device comprising layers of GaN epitaxially grown on a layer of Si ⁇ III ⁇ transferred onto a support substrate of SiC.
  • a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate of SiC.
  • the epitaxy is carried out on the transferred Si ⁇ lll ⁇ layer.
  • As many layers of GaN as necessary are epitaxied.
  • the structure then consists of a support substrate 101 in SiC, a layer of oxide 102, a layer of transferred Si ⁇ lll ⁇ 103, a first layer of epitaxial GaN 104 and a second layer of epitaxial GaN 105.
  • the epitaxy can be carried out by MOCVD above 1000 ° C., typically in the range between 1050 and 1150 ° C.
  • the layers 104 and 105 can be similar to the same layers of the previous example.
  • An AIN buffer layer can also be interposed between the transferred Si ⁇ lll ⁇ layer and the GaN to improve epitaxial growth.
  • the support substrate 101 in SiC can be overdoped as has already been described above.
  • the thin layer of transferred semiconductor material is chosen from the following materials: SiC of polytype 3C, 4H or 6H, GaN, AIN, Si, ZnO and diamond.
  • the intermediate bonding layer is made of a material chosen from Si0 2 , Si 3 N 4 and diamond.
  • the electrically conductive support substrate, monocrystalline or not, is chosen from the following materials: SiC, GaN, AIN, Si, GaAs, ZnO and Ge.
  • Figure 4 is a cross-sectional view of another power semiconductor device according to the invention. It is a bipolar PIN type diode.
  • This device is produced on a silicon support substrate 201 supporting a transferred layer 203 of SiC made integral with the support substrate by a layer of silicon oxide 202.
  • a layer of SiC 204 On the transferred layer 203 are successively epitaxied a layer of SiC 204, a layer of SiC 205 doped n "and a doped SiC layer 210 p.
  • the thickness and doping of the SiC layer 205 are adapted to the desired breakdown voltage, as in the case of conventional vertical PIN diodes.
  • the manufacturing process is analogous to the manufacturing process for the structures described above, the main difference being the presence of the epitaxial layer 210 made of p-type SiC on which we must make an ohmic contact 208 under the same conditions as on a vertical PIN diode.
  • a semiconductor support substrate 301 supporting a transferred layer 303 of semiconductor material is recognized, made integral with the support substrate by an electrically insulating layer 302.
  • a semiconductor layer 304 for example doped n +
  • a semiconductor layer 305 for example n " doped.
  • the layer 305 supports a Schottky contact 308 while the layer 304 supports an ohmic contact 309.

Abstract

The invention relates to a power semiconductor device made of an epitaxied semiconductor material on a stacked structure (10), comprising a semiconductor material layer (13) which is applied to a first surface of a support substrate (11) and is integral with the support substrate (11) by means of an insulating layer (12), said support substrate comprising electric conduction means between the first surface and the second surface, the applied semiconductor material layer (13) acting as an epitaxy support layer for the epitaxied semiconductor material (14, 15).Means for electric connection (16, 17) of said device are provided on the epitaxied semiconductor material and on the second surface of the support substrate, whereby an electric connection via the electrically insulating layer and electric conduction means electrically links the epitaxied semiconductor material (14, 15) to electric connection means (17) provided on the second surface of the support substrate (11).

Description

DISPOSITIF SEMICONDUCTEUR DE PUISSANCE QUASI-VERTICAL QUASI-VERTICAL SEMICONDUCTOR DEVICE
SUR SUBSTRAT COMPOSITEON COMPOSITE SUBSTRATE
DESCRIPTIONDESCRIPTION
DOMAINE TECHNIQUETECHNICAL AREA
La présente invention concerne un dispositif semiconducteur de puissance quasi-vertical sur substrat composite.The present invention relates to a quasi-vertical power semiconductor device on a composite substrate.
ETAT DE LA TECHNIQUE ANTERIEURESTATE OF THE PRIOR ART
Les filières de fabrication de dispositifs de puissance à base de Sic sont actuellement réalisées sur des substrats massifs de Sic monocristallin, de polytype 4H et de faible résistivité électrique volumique. Ce type de substrat permet la fabrication de dispositifs électroniques, par exemple, de type diode Schottky, diode PIN ou de transistor tels que MOS de puissance, JFET ou MESFET, composants utilisant lors de leur fonctionnement un passage vertical de courant électrique entre la face avant et la face arrière de ce substrat .The manufacturing channels for Sic-based power devices are currently carried out on massive monocrystalline Sic substrates, of polytype 4H and of low electrical volume resistivity. This type of substrate allows the manufacture of electronic devices, for example, of the Schottky diode, PIN diode or transistor type such as power MOS, JFET or MESFET, components using during their operation a vertical passage of electric current between the front face. and the back side of this substrate.
La figure 1 est une vue en coupe transversale d'un tel dispositif semiconducteur de puissance. En l'occurrence, il s'agit d'une diode Schottky. La diode est réalisée à partir d'un substrat massif 1 en Sic de type n+ sur lequel deux couches de SiC 2 et 3 ont été successivement épitaxiées. La couche 2 est dopée n+ et la couche 3 est dopée n" . La face arrière du substrat 1 est métallisée pour offrir un contact ohmique 4. Un plot métallique 5 est déposé sur la couche 3 pour réaliser un contact Schottky. Une implantation localisée de la couche 3 fournit une zone 6 de type p assurant une protection périphérique.Figure 1 is a cross-sectional view of such a power semiconductor device. In this case, it is a Schottky diode. The diode is produced from a solid substrate 1 of n + type Sic on which two layers of SiC 2 and 3 have been successively epitaxied. Layer 2 is n + doped and layer 3 is n " doped. The rear face of substrate 1 is metallized to provide ohmic contact 4. A metal pad 5 is deposited on layer 3 to make a Schottky contact. A localized implantation of the layer 3 provides a p-type zone 6 ensuring peripheral protection.
Cette conception verticale du dispositif est particulièrement adaptée à des composants discrets qui, après fabrication collective sur une tranche entière de Sic monocristallin, sont séparés les uns des autres par découpe de puces. La connexion électrique de ces puces avec le boîtier se fait alors de façon standard par prise de contact en faces avant et arrière, de la même façon que pour des composants discrets en silicium.This vertical design of the device is particularly suitable for discrete components which, after collective manufacture on an entire slice of monocrystalline Sic, are separated from each other by cutting chips. The electrical connection of these chips with the housing is then made in a standard manner by contacting the front and rear faces, in the same way as for discrete silicon components.
Les avantages de la filière "substrat massif" consistent dans la structure verticale du dispositif (facilité d'admission de forts courants et assemblage en -boîtier similaire au standard silicium) et dans le fait que le substrat permet 1 ' homoépitaxie de SiC. Les inconvénients de cette filière sont le coût, le faible diamètre des substrats, leur faible disponibilité et l'impossibilité d'intégrer les composants dans une approche système .The advantages of the "solid substrate" sector consist in the vertical structure of the device (ease of admission of high currents and assembly in a housing similar to the silicon standard) and in the fact that the substrate allows homoepitaxy of SiC. The disadvantages of this sector are the cost, the small diameter of the substrates, their low availability and the impossibility of integrating the components in a system approach.
Une voie alternative de substrats pour les applications précitées, est l'utilisation de substrats composites comportant une couche mince de semiconducteur collée sur un substrat et obtenus par le procédé Smar-Cut". Ce procédé est divulgué dans le document FR-A-2 681 472 (correspondant du brevet américain n°5 374 564) . La couche mince et le substrat initial peuvent être en des matériaux différents grâce à l'entière liberté offerte pour la réalisation de substrats composites par ce procédé. Ce procédé permet, entre autres, de réaliser des substrats dénommés SiCOI (de l'anglais "Sic On Insulator") constitués d'une couche mince de Sic collée sur un substrat électriquement isolant vu de la couche mince, comme, par exemple, un susbtrat de silicium oxydé. L'épaisseur de la couche de Sic monocristallin est inférieure à 1 μm, typiquement 0,5 μm. Cette structure SiCOI permet de réaliser des composants électriques en utilisant la couche mince transférée comme couche active. Dans ce cas, les composants électroniques sont confinés dans cette couche très mince, avec les avantages et les inconvénients inhérents. Les avantages sont constitués par la simplicité du procédé de fabrication et par le fait que, les composants étant isolés, il est possible de réaliser des circuits intégrés. Cette filière présente les inconvénients suivants. Les contacts électriques sortant sur une même face du composant, il n'est donc pas possible de les intégrer dans des boîtiers standard silicium. La faible épaisseur du film mince limite des performances des composants en terme de passage de courant dans le film mince.An alternative route of substrates for the above applications, is the use of composite substrates having a semiconductor thin film bonded to a substrate and obtained by Smar-Cut method. "This method is disclosed in FR-A-2 681 472 (corresponding to US Pat. No. 5,374,564). The thin layer and the initial substrate can be made of different materials thanks to the complete freedom offered for the production of composite substrates by this process. among others, to produce substrates called SiCOI (from the English "Sic On Insulator") made up of a thin layer of Sic glued on an electrically insulating substrate seen from the thin layer, like, for example, an oxidized silicon substrate . The thickness of the monocrystalline Sic layer is less than 1 μm, typically 0.5 μm. This SiCOI structure enables electrical components to be produced using the transferred thin layer as an active layer. In this case, the electronic components are confined in this very thin layer, with the inherent advantages and disadvantages. The advantages are constituted by the simplicity of the manufacturing process and by the fact that, the components being isolated, it is possible to produce integrated circuits. This sector has the following drawbacks. Since the electrical contacts exit on the same side of the component, it is therefore not possible to integrate them into standard silicon packages. The thin thickness of the thin film limits the performance of the components in terms of current flow through the thin film.
Le problème technique qui se pose est de pouvoir fabriquer des composants électroniques sur unThe technical problem which arises is to be able to manufacture electronic components on a
® substrat composite de type Smart-Cut , composants possédant des performances électroniques (en terme de courant en particulier) au moins équivalentes à celles obtenues classiquement sur des substrats entièrement monocristallins. De plus, une partie du problème est de pouvoir fabriquer, sur une même structure, des composants de puissance isolés électriquement les uns avec les autres, l'un d'entre eux pouvant être relié électriquement au substrat support de l'empilement composite.® Smart-Cut type composite substrate, components with electronic performance (in terms of current in particular) at least equivalent to that conventionally obtained on entirely monocrystalline substrates. In addition, part of the problem is being able to manufacture, on the same structure, power components electrically isolated from each other, one of which can be connected electrically to the support substrate of the composite stack.
EXPOSÉ DE L'INVENTION Pour remédier aux inconvénients de l'art antérieur, il est proposé un dispositif électronique à conduction verticale, réalisé sur un substrat composite du type semiconducteur-sur-isolant et comprenant deux contacts électriques pris en face avant avec connexion électrique de l'un des contacts vers un substrat support conducteur électrique, après ouverture de la couche isolante. Cela permet ainsi de tirer profit des avantages des substrats composites de type semiconducteur-sur- isolant tout en permettant un assemblage en boîtier classique.PRESENTATION OF THE INVENTION To remedy the drawbacks of the prior art, an electronic device with vertical conduction is proposed, produced on a composite substrate of the semiconductor-over-insulator type and comprising two electrical contacts taken on the front face with electrical connection of one of the contacts to an electrically conductive support substrate, after opening of the insulating layer. This thus makes it possible to take advantage of the advantages of composite substrates of the semiconductor-over-insulator type while allowing assembly in a conventional package.
L'invention permet d'obtenir les avantages suivants :The invention provides the following advantages:
- possibilité d'avoir un substrat support de grande taille et moins cher qu'un substrat Sic massif, possibilité d'avoir, par une structure quasi-verticale des dispositifs, des densités de courant équivalentes, et même supérieures à celles obtenues sur substrat massif, - possibilité d'avoir un assemblage en boîtier classique avec connexion face avant et l'autre face arrière (cas des diodes) , possibilité d'avoir un procédé de fabrication plus simple (un seul métal pour contact ohmique et contact Schottky) , possibilité de concevoir des systèmes intégrés de puissance en bénéficiant d'une isolation galvanique naturelle lorsque la couche mince est collée sur un support via une couche isolante électrique (oxyde et nitrure de silicium par exemple) , possibilité de pouvoir relier électriquement un composant au substrat présent sous la couche d'isolation électronique.- possibility of having a large support substrate and less expensive than a solid Sic substrate, possibility of having, by a quasi-vertical structure of the devices, equivalent current densities, and even greater than those obtained on solid substrate , - possibility of having an assembly in a conventional box with connection of the front face and the other rear face (case of diodes), possibility of having a simpler manufacturing process (a single metal for ohmic contact and Schottky contact), possibility of designing integrated power systems benefiting from natural galvanic isolation when the thin layer is bonded to a support via an electrical insulating layer (silicon oxide and nitride for example), possibility of being able to electrically connect a component to the substrate present under the electronic insulation layer.
L'invention a donc pour objet un dispositif semiconducteur de puissance réalisé dans du matériau semiconducteur épitaxié sur une structure empilée, caractérisé en ce que :The subject of the invention is therefore a power semiconductor device produced in epitaxial semiconductor material on a stacked structure, characterized in that:
- la structure empilée comprend une couche de matériau semiconducteur reportée sur une première face d'un substrat support et solidaire du substrat support par l'intermédiaire d'une couche électriquememt isolante, le substrat support comprenant des moyens de conduction électrique entre ladite première face et une deuxième face, la couche de matériau semiconducteur reportée servant de support d' épitaxié pour le matériau semiconducteur épitaxié, des moyens de connexion électrique du dispositif sont prévus, d'une part sur le matériau semiconducteur épitaxié, et d'autre part, sur la deuxième face du substrat support, une liaison électrique au travers de la couche électriquement isolante et lesdits moyens de conduction électrique du substrat support reliant électriquement le matériau semiconducteur épitaxié aux moyens de connexion électrique prévus sur la deuxième face du substrat support . Avantageusement, les moyens de conduction électrique du support sont constitués par le substrat support lui-même qui est en matériau conducteur électrique . Le matériau semiconducteur épitaxié peut comporter plusieurs couches de dopage différent.the stacked structure comprises a layer of semiconductor material transferred onto a first face of a support substrate and secured to the support substrate by means of an electrically insulating layer, the support substrate comprising means of electrical conduction between said first face and a second face, the layer of transferred semiconductor material serving as epitaxial support for the epitaxial semiconductor material, means for electrical connection of the device are provided, on the one hand on the epitaxial semiconductor material, and on the other hand, on the second face of the support substrate, an electrical connection through the electrically insulating layer and said means of electrical conduction of the support substrate electrically connecting the epitaxial semiconductor material to the electrical connection means provided on the second face of the support substrate. Advantageously, the means of electrical conduction of the support consist of the support substrate itself which is made of electrically conductive material. The epitaxial semiconductor material can comprise several different doping layers.
Eventuellement, le substrat support est surdopé du côté de 1 ' interface avec la couche électriquement isolante. Les moyens de conduction électrique du dispositif peuvent comprendre au moins un contact Schottky et/ou au moins un contact ohmique.Optionally, the support substrate is overdoped on the side of the interface with the electrically insulating layer. The electrical conduction means of the device can comprise at least one Schottky contact and / or at least one ohmic contact.
Avantageusement, le substrat support est en matériau semiconducteur, choisi par exemple parmi SiC, GaN, AIN, Si, GaAs, ZnO et Ge .Advantageously, the support substrate is made of semiconductor material, chosen for example from SiC, GaN, AIN, Si, GaAs, ZnO and Ge.
La couche électriquement isolante peut être en matériau choisi parmi Si02, Si3N4 et le diamant.The electrically insulating layer can be of a material chosen from Si0 2 , Si 3 N 4 and diamond.
La couche mince de matériau semiconducteur reportée peut être en un matériau choisi parmi SiC, GaN, AIN, Si, ZnO et le diamant.The thin layer of transferred semiconductor material can be of a material chosen from SiC, GaN, AIN, Si, ZnO and diamond.
Le matériau semiconducteur épitaxié peut être choisi parmi SiC, GaN, AlGaN, InGaN et le diamant.The epitaxial semiconductor material can be chosen from SiC, GaN, AlGaN, InGaN and diamond.
L'invention a aussi pour objet un circuit semiconducteur, caractérisé en ce qu'il associe, sur une même structure empilée au moins un dispositif semiconducteur de puissance tel que défini ci-dessus et au moins un dispositif semiconducteur qui n'est pas électriquement relié à la deuxième face du substrat support . BREVE DESCRIPTION DES DESSINSThe invention also relates to a semiconductor circuit, characterized in that it combines, on the same stacked structure at least one power semiconductor device as defined above and at least one semiconductor device which is not electrically connected to the second face of the support substrate. BRIEF DESCRIPTION OF THE DRAWINGS
L'invention sera mieux comprise et d'autres avantages et particularités apparaîtront à la lecture de la description qui va suivre, donnée à titre d'exemple non limitatif, accompagnée des dessins annexés parmi lesquels :The invention will be better understood and other advantages and features will appear on reading the description which follows, given by way of nonlimiting example, accompanied by the appended drawings among which:
- la figure 1, déjà décrite, est une vue en coupe transversale d'un dispositif semiconducteur de puissance selon l'art antérieur, - la figure 2 est une vue en coupe transversale d'un • dispositif semiconducteur de puissance selon l'invention, les figures 3A à 3J sont des vues en coupe transversale illustrant un procédé de réalisation d'un dispositif semiconducteur de puissance selonFIG. 1, already described, is a cross-section view of a power semiconductor device according to the prior art, FIG. 2 is a cross-section view of a power semiconductor device according to the invention, FIGS. 3A to 3J are cross-sectional views illustrating a method for producing a power semiconductor device according to
1 ' invention, la figure 4 est une vue en coupe transversale d'un autre dispositif semiconducteur de puissance selon l'invention, - la figure 5 est une vue en coupe transversale d'un dispositif semiconducteur pouvant être associé avec un dispositif semiconducteur de puissance selon l'invention en vue de réaliser un circuit intégré.1 invention, Figure 4 is a cross-sectional view of another power semiconductor device according to the invention, - Figure 5 is a cross-sectional view of a semiconductor device can be associated with a power semiconductor device according to the invention in order to produce an integrated circuit.
DESCRIPTION DETAILLEE DE MODES DE REALISATION DEDETAILED DESCRIPTION OF EMBODIMENTS OF
L ' INVENTIONTHE INVENTION
La figure 2 est une vue en coupe transversale d'un dispositif semiconducteur de puissance selon l'invention. Le dispositif est fabriqué sur la face avant d'un substrat composite 10. Dans cet exemple, le substrat support 11 est en silicium et supporte une couche d'oxyde de silicium 12 et une couche de SiC 13 transférée, par exemple par le procédé Smart-Cut", sur le substrat support 11 et solidaire de ce substrat support par la couche d'oxyde 12.Figure 2 is a cross-sectional view of a power semiconductor device according to the invention. The device is manufactured on the front face of a composite substrate 10. In this example, the support substrate 11 is made of silicon and supports a silicon oxide layer 12 and an SiC layer 13 transferred, for example, by the Smart-Cut method ", on the support substrate 11 and integral with the supporting substrate by the oxide layer 12.
La couche de Sic transférée 13 sert de support d' épitaxié pour la couche de SiC 14 dopée n+ et pour la couche de SiC 15 dopée n" .The transferred Sic layer 13 serves as an epitaxial support for the n + doped SiC 14 layer and for the n " doped SiC 15 layer.
Les inventeurs de la présente invention sont parvenus à réaliser des epitaxies de SiC sur ce substrat composite de façon inattendue. L'oxyde de silicium ne s'est pas détérioré pour des températures d' épitaxié un peu inférieures à la température de fusion du silicium et les epitaxies obtenues sont de bonne qualité, comparables aux epitaxies sur du SiC massif .The inventors of the present invention have succeeded in carrying out epitaxies of SiC on this composite substrate unexpectedly. The silicon oxide did not deteriorate for epitaxy temperatures slightly lower than the melting temperature of the silicon and the epitaxies obtained are of good quality, comparable to epitaxies on solid SiC.
Par abus de langage, on pourra appeler contact Schottky ou ohmique le métal dont 1 ' interface avec le matériau semiconducteur en contact est un contact Schottky ou ohmique.By abuse of language, we can call Schottky or ohmic contact the metal whose interface with the semiconductor material in contact is a Schottky or ohmic contact.
Le dispositif comprend aussi un contact Schottky 16 disposé sur la couche de SiC 15 et un contact ohmique 17 disposé sur la face arrière du substrat support 11. Des contacts ohmiques 18 sont disposés sur la face supérieure de la couche de SiC 14. Ils permettent une liaison électrique de la couche de SiC 14 avec le contact ohmique 17 en face arrière grâce à des métallisations 19 déposées sur les contacts ohmiques 18, prenant contact avec le substrat support 11 au travers de la couche d'oxyde 12, et grâce au substrat support 11 qui est suffisamment conducteur. De plus, le contact entre les métallisations 19 et le substrat support 11 est un contact ohmique. Ce dispositif de puissance peut donc être qualifié de dispositif quasi-vertical. Les figures 3A à 3J sont des vues en coupe transversales illustrant un procédé de réalisation d'un dispositif semiconducteur de puissance selon l'invention. Le dispositif réalisé dans cet exemple comporte des couches de SiC épitaxiées sur une couche de SiC transférée sur un substrat support en silicium.The device also comprises a Schottky contact 16 disposed on the SiC layer 15 and an ohmic contact 17 disposed on the rear face of the support substrate 11. Ohmic contacts 18 are arranged on the upper face of the SiC layer 14. They allow a electrical connection of the SiC layer 14 with the ohmic contact 17 on the rear face thanks to metallizations 19 deposited on the ohmic contacts 18, making contact with the support substrate 11 through the oxide layer 12, and thanks to the support substrate 11 which is sufficiently conductive. Of more, the contact between the metallizations 19 and the support substrate 11 is an ohmic contact. This power device can therefore be described as a quasi-vertical device. FIGS. 3A to 3J are cross-sectional views illustrating a method for producing a power semiconductor device according to the invention. The device produced in this example comprises layers of SiC epitaxially grown on a layer of SiC transferred onto a silicon support substrate.
La figure 3A montre un substrat composite 100 formé d'un substrat support 101 en silicium supportant une couche d'oxyde de silicium 102 servant au collage d'une couche de SiC 103 transférée. La couche de SiC transférée 103 sert de support d' épitaxié pour la couche de SiC 104 et pour la couche de SiC 105 épitaxiëe sur la couche 104.FIG. 3A shows a composite substrate 100 formed of a silicon support substrate 101 supporting a layer of silicon oxide 102 used for bonding a layer of transferred SiC 103. The transferred SiC layer 103 serves as an epitaxial support for the SiC layer 104 and for the SiC layer 105 epitaxied on the layer 104.
La couche de SiC transférée 103 a un dopage n de l'ordre de 1017 à 1019 atomes/cm3 et une épaisseur comprise entre 0,5 et 1 μm. Le substrat support 101 a un dopage n de l'ordre de 1020 atomes/cm3 et une épaisseur comprise entre 200 et 500 μm. La couche d'oxyde 103 a une épaisseur comprise entre 2 et 4 μm, par exemple 2 μm. Le substrat support 101 peut, du côté de l'interface avec la couche d'oxyde 102, être surdopé si nécessaire avant l'assemblage du substrat composite 100 afin de faciliter un contact ohmique postérieur (voir la figure 3G) .The transferred SiC layer 103 has an n doping of the order of 10 17 to 10 19 atoms / cm 3 and a thickness of between 0.5 and 1 μm. The support substrate 101 has an n doping of the order of 10 20 atoms / cm 3 and a thickness between 200 and 500 μm. The oxide layer 103 has a thickness of between 2 and 4 μm, for example 2 μm. The support substrate 101 can, on the side of the interface with the oxide layer 102, be overdoped if necessary before assembly of the composite substrate 100 in order to facilitate posterior ohmic contact (see FIG. 3G).
Sur la couche de SiC transférée, les couches de SiC 104 et 105 sont successivement épitaxiées. L' épitaxié est réalisée en-dessous de 1410°C pour un substrat support 101 en silicium.On the transferred SiC layer, the SiC layers 104 and 105 are successively epitaxial. The epitaxy is carried out below 1410 ° C. for a support substrate 101 made of silicon.
Si le dispositif à réaliser est une diode Schottky de puissance, la couche de SiC 104 est dopée n+ (dopage compris entre 5.1018 et 5.1020 atomes/cm3) et a une épaisseur d'environ 4 μm, la couche de SiC 105 est dopée n" (dopage de l'ordre de 1016 atomes/cm3) et a une épaisseur d'environ 6 μm. Ce couple de valeurs est donné à titre indicatif pour une diode Schottky de type 600 volts. Ces valeurs sont à ajuster en fonction de la tenue en tension souhaitée.If the device to be produced is a power Schottky diode, the layer of SiC 104 is doped n + (doping between 5.10 18 and 5.10 20 atoms / cm 3 ) and has a thickness of approximately 4 μm, the layer of SiC 105 is doped n " (doping of the order of 10 16 atoms / cm 3 ) and has a thickness of approximately 6 μm. This pair of values is given for information for a Schottky diode of the 600 volt type. These values are at adjust according to the desired tensile strength.
La figure 3B est relative à un premier niveau de lithographie permettant de définir des structures "Mesa" par la gravure de la couche de SiC 105 jusqu'à atteindre la couche de SiC 104. La structure "Mesa" permet la tenue en tension du composant et le fait d'exposer la couche de SiC 104 permettra ultérieurement la réalisation d'un contact ohmique. La gravure peut se faire par plasma. L'étape suivante consiste à déposer une couche inorganique 106, par exemple une couche de Si02 ou de Si3N , d'une épaisseur de plusieurs μm, par exemple de 2 à 4 μm. Cette couche aura, entre autres, la fonction de passivation du composant (voir la figure 3C) .FIG. 3B relates to a first level of lithography making it possible to define “Mesa” structures by etching the layer of SiC 105 until reaching the layer of SiC 104. The “Mesa” structure allows the voltage withstand of the component and the fact of exposing the layer of SiC 104 will subsequently make it possible to produce an ohmic contact. Etching can be done by plasma. The next step consists in depositing an inorganic layer 106, for example a layer of Si0 2 or Si 3 N, with a thickness of several μm, for example from 2 to 4 μm. This layer will have, among other things, the passivation function of the component (see Figure 3C).
La figure 3D est relative à un deuxième niveau de lithographie permettant de définir les zones de gravure des couches 106, 104 et 103. C'est une première étape vers la réalisation d'un contact avec le substrat support 101. Cela permet aussi d'isoler électriquement le composant de ses voisins dans le cas où l'on souhaite en intégrer plusieurs sur un même circuit .FIG. 3D relates to a second level of lithography making it possible to define the etching zones of the layers 106, 104 and 103. This is a first step towards making contact with the support substrate 101. This also makes it possible to electrically isolate the component from its neighbors in the case where you want to integrate several on the same circuit.
Après définition de ce niveau de lithographie, la couche 106 est gravée. Dans le cas d'une couche de Si02, la gravure peut être obtenue par gravure humide en solution HF ou par gravure plasma. La résine de masquage est alors retirée et les couches de SiC 104 et 103 sont ensuite successivement gravées en utilisant comme masque la couche 106. La gravure est faite par plasma. La structure obtenue est représentée à la figure 3D.After defining this level of lithography, layer 106 is etched. In the case of a layer of Si0 2 , the etching can be obtained by wet etching in HF solution or by plasma etching. The masking resin is then removed and the SiC layers 104 and 103 are then successively etched using the layer 106 as a mask. The etching is done by plasma. The structure obtained is shown in Figure 3D.
La figure 3E est relative à un troisième niveau de lithographie permettant de définir différentes ouvertures dans les couches 102 et 106 pour de futurs contacts électriques. La figure 3E montre la structure obtenue après développement de la couche de résine 107.FIG. 3E relates to a third level of lithography making it possible to define different openings in the layers 102 and 106 for future electrical contacts. FIG. 3E shows the structure obtained after development of the resin layer 107.
On procède ensuite à la gravure des couches 102 et 106 pour obtenir la structure illustrée par la figure 3F après retrait de la résine. La couche 102 est gravée en 112, ce qui permettra un contact ultérieur vers le substrat support 101. La couche 106 est gravée en 116, ce qui permettra un futur contact ohmique. Elle est aussi gravée en 126 pour le futur contact Schottky. La- figure 3G est relative à un quatrième niveau de lithographie permettant de réaliser un contact ohmique. Le métal déposé peut être , Ni ou Ti . Son épaisseur peut être comprise entre 100 et 500 nm. Le dépôt peut se faire par evaporation ou pulvérisation cathodique. La lithographie permet de définir les zones de contact ohmique avec la couche de SiC 104 en 116 et aussi la connexion vers le contact ohmique avec le substrat support 101 en 112.Next, layers 102 and 106 are etched to obtain the structure illustrated in FIG. 3F after removal of the resin. The layer 102 is etched at 112, which will allow subsequent contact to the support substrate 101. The layer 106 is etched at 116, which will allow future ohmic contact. It is also engraved in 126 for the future Schottky contact. FIG. 3G relates to a fourth level of lithography making it possible to produce an ohmic contact. The deposited metal can be, Ni or Ti. Its thickness can be between 100 and 500 nm. The deposition can be done by evaporation or sputtering. Lithography makes it possible to define the ohmic contact zones with the layer of SiC 104 at 116 and also the connection to the ohmic contact with the support substrate 101 at 112.
La figure 3G montre la structure obtenue avec gravure du métal déposé et retrait de la résine. Elle montre le dépôt métallique 109 reliant la couche de SiC 104 au substrat support 101. La gravure du métal peut être faite de façon conventionnelle, par exemple par gravure humide pour Ni et Ti ou par plasma pour W. On applique ensuite un recuit en vue d'activer le contact ohmique avec le SiC de la couche 104, dans la gamme comprise entre 900 et 1100°C pour Ni et Ti, dans la gamme comprise entre 1000 et 1300°C pour W. Simultanément, le contact ohmique avec le silicium du substrat support 101 est activé. La figure 3H est relative à un cinquième niveau de lithographie permettant d'obtenir un contact Schottky. On dépose sur la structure obtenue précédemment, par pulvérisation cathodique ou par evaporation, du métal de contact Schottky qui peut être Ti ou Ni, sur une épaisseur comprise entre 100 etFigure 3G shows the structure obtained with etching of the deposited metal and removal of the resin. It shows the metallic deposit 109 connecting the SiC layer 104 to the support substrate 101. The etching of the metal can be done in a conventional manner, for example by wet etching for Ni and Ti or by plasma for W. An annealing is then applied in view to activate the ohmic contact with the SiC of layer 104, in the range between 900 and 1100 ° C for Ni and Ti, in the range between 1000 and 1300 ° C for W. Simultaneously, the ohmic contact with silicon of the support substrate 101 is activated. FIG. 3H relates to a fifth level of lithography making it possible to obtain a Schottky contact. A Schottky contact metal, which can be Ti or Ni, is deposited on the structure obtained above, by sputtering or by evaporation, over a thickness of between 100 and
500 nm. On procède à une lithographie, puis à une gravure de ce métal de sorte à former des plots de contact Schottky 108 sur la couche de SiC 105. Un recuit de contact Schottky est ensuite appliqué, par exemple, à une température comprise entre 400 à 600°C.500 nm. A lithography is carried out, then an etching of this metal so as to form Schottky contact pads 108 on the layer of SiC 105. A Schottky contact annealing is then applied, for example, at a temperature between 400 to 600 ° C.
Une couche de métallisation 117 est déposée en face arrière du substrat support 101 (voir la figure 31) en vue de réaliser un contact ohmique face arrière. Cette couche peut être en Al, en Ti ou en Ni. Un recuit peut être nécessaire pour améliorer le contact ohmique. Enfin, une sur-métallisation peut être nécessaire pour renforcer les métallisations de la face avant du dispositif. La figure 3J montre une sur- métallisation 118 renforçant le plot de contact Schottky 108 et une sur-métallisation 119 renforçant le dépôt 109 assurant le contact ohmique vers la couche de SiC 104 et la connexion vers le substrat support 101. Cette sur-métallisation peut être de l'aluminium, d'une épaisseur comprise entre 0,5 et 5 μm. La figure 3J montre la structure obtenue après lithographie et gravure .A metallization layer 117 is deposited on the rear face of the support substrate 101 (see FIG. 31) in order to make an ohmic contact on the rear face. This layer can be made of Al, Ti or Ni. Annealing may be necessary to improve the ohmic contact. Finally, an over-metallization may be necessary to reinforce the metallizations of the front face of the device. FIG. 3J shows an over-metallization 118 reinforcing the Schottky contact pad 108 and an over-metallization 119 reinforcing the deposit 109 ensuring the ohmic contact towards the SiC layer 104 and the connection towards the support substrate 101. This over-metallization can be aluminum, with a thickness between 0.5 and 5 μm. Figure 3J shows the structure obtained after lithography and etching.
Une variante de ce procédé de réalisation est rendue possible si le dopage de la couche de SiC 104 est suffisamment élevé pour permettre un bon contact ohmique avec du Ti recuit à environ 500°C. Le dopage nécessaire pour cela est de l'ordre de 5.1019 atomes/cm3 ou plus. Ce dopage est accessible sur du Sic obtenu par épitaxié. Il est important de noter qu'un tel dopage ne peut être obtenu sur un substrat de SiC massif. Or, c'est sur ce substrat qu'est réalisé le contact ohmique dans l'art antérieur. Dans le cas de la présente invention, le même métal peut servir au contact Schottky et au contact ohmique, avec un seul recuit à environ 500°C. Cette variante est mise en œuvre à partir de la structure illustrée par la figure 3F. Un seul dépôt métallique est effectué, par exemple, du Ti ou du Ni ou un bicouche de l'un de ces métaux et d'un autre métal. Une lithographie est effectuée. Elle permet de définir simultanément les plots Schottky et les plots de contact ohmique. Après gravure et recuit à environ 500 °C, on obtient directement la structure illustrée par la figure 3H avec un niveau complet de lithographie en moins (un dépôt, une lithographie, une gravure et un recuit en moins) . La fin du procédé reste identique avec la métallisation face arrière et éventuellement une sur-métallisation.A variant of this production method is made possible if the doping of the SiC layer 104 is sufficiently high to allow good ohmic contact with Ti annealed at around 500 ° C. The doping necessary for this is of the order of 5.10 19 atoms / cm 3 or more. This doping is accessible on Sic obtained by epitaxy. It is important to note that such doping cannot be obtained on a solid SiC substrate. However, it is on this substrate that the ohmic contact is made in the prior art. In the case of the present invention, the same metal can be used for Schottky contact and for ohmic contact, with a single annealing at approximately 500 ° C. This variant is implemented from the structure illustrated in FIG. 3F. A single metallic deposit is made, for example, of Ti or Ni or a bilayer of one of these metals and of another metal. A lithography is carried out. It makes it possible to simultaneously define the Schottky pads and the ohmic contact pads. After engraving and annealing to approximately 500 ° C., the structure illustrated in FIG. 3H is obtained directly with one complete level of lithography less (one deposit, one lithography, one etching and one annealing less). The end of the process remains identical with the rear side metallization and possibly an over-metallization.
Pour améliorer la tenue en tension, il est bon de prévoir des protections périphériques qui consistent en des zones de dopage p réalisées à la périphérie du contact Schottky. Ces protections peuvent être soit réalisées par implantation localisée, soit par une épitaxié supplémentaire de type p faite dans la foulée de l' épitaxié de la couche de SiC 105, la couche p étant alors gravée localement dans la zone du contact Schottky.To improve the voltage withstand, it is good to provide peripheral protections which consist of p-doping zones produced at the periphery of the Schottky contact. These protections can either be carried out by localized implantation, or by an additional epitaxial type p made in the wake of the epitaxial layer of SiC 105, the layer p then being locally etched in the area of the Schottky contact.
Il est possible de réaliser ces protections périphériques dans le cadre de la présente invention, sans difficulté particulière par rapports aux composants classiques de type vertical. Sur la figure 3J, des protections périphériques implantées 120 ont été représentées en traits interrompus.It is possible to produce these peripheral protections in the context of the present invention, without particular difficulty compared to conventional components of the vertical type. In FIG. 3J, implanted peripheral protections 120 have been shown in broken lines.
L'invention permet également la réalisation d'un dispositif comportant des couches de SiC épitaxiées sur une couche de SiC transférée sur un substrat support en SiC.The invention also allows the production of a device comprising layers of SiC epitaxially grown on a layer of SiC transferred onto a support substrate of SiC.
Pour cela, une couche de SiC est transférée et collée par l'intermédiaire d'une couche d'oxyde de silicium sur un substrat support en Sic. L' épitaxié est réalisée sur la couche de SiC transférée. Autant de couches de SiC que nécessaire sont épitaxiées. A titre d'exemple, en revenant sur la figure 3A, la structure se compose alors d'un substrat support 101 en SiC, d'une couche d'oxyde 102, d'une couche de SiC transférée 103, d'une première couche de SiC épitaxiée 104 et d'une deuxième couche de SiC épitaxiée 105. L'épitaxie peut être réalisée au-dessus de 1410°C, typiquement dans la gamme comprise entre 1400 et 1600°C. Par exemple, pour obtenir une diode Schottky, la couche de SiC 104 peut être dopée n+ selon un dopage de 1019 atomes/cm3 et peut avoir une épaisseur d'environ 4 μm. La couche de SiC 105 peut être dopée n" selon un dopage de 1016 atomes/cm3 et peut avoir une épaisseur d'environ 6 μm.For this, a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate in Sic. The epitaxy is carried out on the transferred SiC layer. As many layers of SiC as necessary are epitaxied. By way of example, returning to FIG. 3A, the structure then consists of a support substrate 101 made of SiC, an oxide layer 102, a layer of transferred SiC 103, a first layer of epitaxied SiC 104 and a second layer of epitaxied SiC 105. Epitaxy can be performed above 1410 ° C, typically in the range between 1400 and 1600 ° C. For example, to obtain a Schottky diode, the layer of SiC 104 can be doped n + according to a doping of 10 19 atoms / cm 3 and can have a thickness of approximately 4 μm. The SiC 105 layer can be doped n " according to a doping of 10 16 atoms / cm 3 and can have a thickness of approximately 6 μm.
Le substrat support 101 en SiC peut être surdopé du côté de l'interface avec la couche d'oxyde 102 pour améliorer, par exemple, le contact ohmique entre le dépôt métallique 109 et le substrat support 101 (voir la figure 3G) . Ce surdopage peut être réalisé avant assemblage de la structure empilée, par épitaxié ou par implantation pleine plaque ou encore par dépôt polycristallin ou amorphe très dopé.The SiC support substrate 101 can be overdoped on the side of the interface with the oxide layer 102 to improve, for example, the ohmic contact between the metal deposit 109 and the support substrate 101 (see FIG. 3G). This overdoping can be carried out before assembly of the stacked structure, by epitaxy or by full-plate implantation or else by highly doped polycrystalline or amorphous deposition.
Le procédé de réalisation est similaire à celui décrit pour le dispositif précédent avec substrat support en silicium. Une différence existe néanmoins pour le contact ohmique face arrière. Le métal du contact ohmique face arrière est déposé plus tôt, en même temps que le contact ohmique sur SiC face avant. Un même recuit est effectué pour les contacts ohmiques face avant et face arrière.The production method is similar to that described for the previous device with silicon support substrate. A difference nevertheless exists for the ohmic contact on the rear face. The metal of the ohmic contact on the back side is deposited earlier, at the same time as the ohmic contact on SiC on the front side. The same annealing is carried out for the ohmic contacts on the front and rear faces.
Les mêmes variantes que précédemment s'appliquent également. L'invention permet aussi la réalisation d'un dispositif comportant des couches de GaN épitaxiées sur une couche de Sic transférée sur un substrat support en SiC. Pour cela, une couche de SiC est transférée et collée par l'intermédiaire d'une couche d'oxyde de silicium sur un substrat support en SiC. L'épitaxie est réalisée sur la couche de SiC transférée. Autant de couches de GaN que nécessaire sont épitaxiées. A titre d'exemple, en revenant sur la figure 3A, la structure se compose alors d'un substrat support 101 en SiC, d'une couche d'oxyde 102, d'une couche de SiC transférée 103, d'une première couche de GaN épitaxiée 104 et d'une deuxième couche de GaN épitaxiée 105. L'épitaxie peut être réalisée par MOCVD au-dessus de 1000°C, typiquement dans la gamme comprise entre 1050 et 1150°C. Par exemple, pour obtenir une diode Schottky GaN, la couche de GaN 104 peut être dopée n+ selon un dopage de 1019 atomes/cm3 et peut avoir une épaisseur comprise entre environ 1 et environ 4 μm. La couche deThe same variants as above also apply. The invention also allows the production of a device comprising layers of GaN epitaxially grown on a layer of Sic transferred onto a support substrate of SiC. For this, a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate of SiC. The epitaxy is carried out on the transferred SiC layer. As many layers of GaN as necessary are epitaxied. By way of example, returning to FIG. 3A, the structure then consists of a support substrate 101 in SiC, a layer of oxide 102, a layer of transferred SiC 103, a first layer of epitaxial GaN 104 and of a second layer of epitaxial GaN 105. The epitaxy can be carried out by MOCVD above 1000 ° C., typically in the range between 1050 and 1150 ° C. For example, to obtain a Schottky GaN diode, the GaN layer 104 can be doped n + according to a doping of 10 19 atoms / cm 3 and can have a thickness of between approximately 1 and approximately 4 μm. The layer of
GaN 105 peut être dopée n" selon un dopage de 1016 atomes/cm3 et peut avoir une épaisseur d'environ 6 μm.GaN 105 can be doped n " according to a doping of 10 16 atoms / cm 3 and can have a thickness of approximately 6 μm.
Une couche tampon en AIN peut être intercalée entre la couche de SiC transférée et le GaN pour améliorer la croissance épitaxiale.An AIN buffer layer can be interposed between the transferred SiC layer and the GaN to improve epitaxial growth.
Le substrat support 101 en SiC peut être surdopé comme il a été décrit ci-dessus.The support substrate 101 made of SiC can be overdoped as described above.
Pour la réalisation du dispositif, la technique appliquée est similaire aux cas décrits précédemment, mais avec des adaptations relatives aux contacts ohmiques et aux gravures de GaN au lieu du SiC.For the realization of the device, the technique applied is similar to the cases described above, but with adaptations relating to ohmic contacts and GaN etchings instead of SiC.
L'invention permet aussi la réalisation d'un dispositif comportant des couches de GaN épitaxiées sur une couche de Si {lll} transférée sur un substrat support en SiC.The invention also allows the production of a device comprising layers of GaN epitaxially grown on a layer of Si {III} transferred onto a support substrate of SiC.
Pour cela, une couche de SiC est transférée et collée par l'intermédiaire d'une couche d'oxyde de silicium sur un substrat support en SiC. L'épitaxie est réalisée sur la couche de Si {lll} transférée. Autant de couches de GaN que nécessaire sont épitaxiées. A titre d'exemple, en revenant sur la figure 3A, la structure se compose alors d'un substrat support 101 en SiC, d'une couche d'oxyde 102, d'une couche de Si {lll} transférée 103, d'une première couche de GaN épitaxiée 104 et d'une deuxième couche de GaN épitaxiée 105. L'épitaxie peut être réalisée par MOCVD au-dessus de 1000°C, typiquement dans la gamme comprise entre 1050 et 1150°C. Par exemple, pour obtenir une diode Schottky GaN, les couches 104 et 105 peuvent être similaires aux mêmes couches de 1 ' exemple précédent .For this, a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate of SiC. The epitaxy is carried out on the transferred Si {lll} layer. As many layers of GaN as necessary are epitaxied. By way of example, returning to FIG. 3A, the structure then consists of a support substrate 101 in SiC, a layer of oxide 102, a layer of transferred Si {lll} 103, a first layer of epitaxial GaN 104 and a second layer of epitaxial GaN 105. The epitaxy can be carried out by MOCVD above 1000 ° C., typically in the range between 1050 and 1150 ° C. For example, to obtain a Schottky GaN diode, the layers 104 and 105 can be similar to the same layers of the previous example.
Une couche tampon en AIN peut également être intercalée entre la couche de Si {lll} transférée et le GaN pour améliorer la croissance épitaxiale. Le substrat support 101 en SiC peut être surdopé comme il a déjà été décrit plus haut.An AIN buffer layer can also be interposed between the transferred Si {lll} layer and the GaN to improve epitaxial growth. The support substrate 101 in SiC can be overdoped as has already been described above.
Pour la réalisation du dispositif, la technique appliquée est similaire au cas précédent.For the realization of the device, the technique applied is similar to the previous case.
D'une manière générale, la couche mince de matériau semiconducteur transférée est choisie parmi les matériaux suivants : SiC de polytype 3C, 4H ou 6H, GaN, AIN, Si, ZnO et le diamant. La couche intermédiaire de collage est en un matériau choisi parmi Si02, Si3N4 et le diamant. Le substrat support électriquement conducteur, monocristallin ou non, est choisi parmi les matériaux suivants : SiC, GaN, AIN, Si, GaAs, ZnO et Ge .In general, the thin layer of transferred semiconductor material is chosen from the following materials: SiC of polytype 3C, 4H or 6H, GaN, AIN, Si, ZnO and diamond. The intermediate bonding layer is made of a material chosen from Si0 2 , Si 3 N 4 and diamond. The electrically conductive support substrate, monocrystalline or not, is chosen from the following materials: SiC, GaN, AIN, Si, GaAs, ZnO and Ge.
La figure 4 est une vue en coupe transversale d'un autre dispositif semiconducteur de puissance selon l'invention. Il s'agit d'une diode bipolaire de type PIN. Ce dispositif est réalisé sur un substrat support 201 en silicium supportant une couche transférée 203 en SiC rendue solidaire du substrat support par une couche d'oxyde de silicium 202. Sur la couche transférée 203 sont épitaxiées successivement une couche de SiC 204, une couche de SiC 205 dopée n" et une couche de SiC 210 dopée p. L'épaisseur et le dopage de la couche de SiC 205 sont adaptés à la tenue en tension désirée, comme dans le cas de diodes PIN verticales classiques. On peut ainsi obtenir des tenues en tension de l'ordre de 1000 à 5000 V ou plus. Le procédé de fabrication est analogue au procédé de fabrication des structures décrites précédemment, la différence principale étant la présence de la couche épitaxiée 210 en SiC de type p sur laquelle on doit réaliser un contact ohmique 208 dans les mêmes conditions que sur une diode PIN verticale.Figure 4 is a cross-sectional view of another power semiconductor device according to the invention. It is a bipolar PIN type diode. This device is produced on a silicon support substrate 201 supporting a transferred layer 203 of SiC made integral with the support substrate by a layer of silicon oxide 202. On the transferred layer 203 are successively epitaxied a layer of SiC 204, a layer of SiC 205 doped n "and a doped SiC layer 210 p. the thickness and doping of the SiC layer 205 are adapted to the desired breakdown voltage, as in the case of conventional vertical PIN diodes. One can thus obtain withstand voltage of the order of 1000 to 5000 V. or more. The manufacturing process is analogous to the manufacturing process for the structures described above, the main difference being the presence of the epitaxial layer 210 made of p-type SiC on which we must make an ohmic contact 208 under the same conditions as on a vertical PIN diode.
Sur la figure 4, on reconnaît la couche de métallisation 217 en face arrière du substrat support 201, le dépôt métallique 209 assurant le contact ohmique vers la couche de SiC 204 et la connexion vers le substrat support 201. On reconnaît également la couche de passivation 206.In FIG. 4, we recognize the metallization layer 217 on the rear face of the support substrate 201, the metal deposit 209 ensuring the ohmic contact towards the SiC layer 204 and the connection towards the support substrate 201. The passivation layer 206 is also recognized.
La figure 5 et une vue en coupe transversale d'un dispositif semiconducteur pouvant être associé avec un dispositif semiconducteur de puissance selon l'invention en vue de réaliser un circuit intégré . Un tel composant présente des caractéristiques similaires à ceux de l'invention (conduction verticale notamment) , mais il ne dispose pas d'une reprise de contact en face arrière. La couche isolante sur le substrat support n'étant pas percée, de tels composants restent isolés électriquement les uns des autres : plusieurs d'entre eux peuvent donc être intégrés avec un dispositif selon l'invention pour former un circuit avec reprises de contact classiques en faces avant et arrière du circuit.Figure 5 and a cross-sectional view of a semiconductor device which can be associated with a power semiconductor device according to the invention in order to produce an integrated circuit. Such a component has characteristics similar to those of the invention (vertical conduction in particular), but it does not have contact recovery on the rear face. Since the insulating layer on the support substrate is not pierced, such components remain electrically isolated from each other: several of them can therefore be integrated with a device according to the invention to form a circuit with conventional contact pickups in front and back sides of the circuit.
Sur la figure 5, on reconnaît un substrat support semiconducteur 301 supportant une couche transférée 303 en matériau semiconducteur, rendue solidaire du substrat support par une couche électriquement isolante 302. Sur la couche transférée sont épitaxiées successivement une couche semiconductrice 304 (par exemple dopée n+) et une couche semiconductrice 305 (par exemple dopée n") . La couche 305 supporte un contact Schottky 308 tandis que la couche 304 supporte un contact ohmique 309. In FIG. 5, a semiconductor support substrate 301 supporting a transferred layer 303 of semiconductor material is recognized, made integral with the support substrate by an electrically insulating layer 302. On the transferred layer are successively epitaxied a semiconductor layer 304 (for example doped n + ) and a semiconductor layer 305 (for example n " doped). The layer 305 supports a Schottky contact 308 while the layer 304 supports an ohmic contact 309.

Claims

REVENDICATIONS
1. Dispositif semiconducteur de puissance réalisé dans du matériau semiconducteur épitaxié sur une structure empilée, caractérisé en ce que : - la structure empilée comprend une couche de matériau semiconducteur (13, 103, 203) reportée sur une première face d'un substrat support (11, 101, 201) et solidaire du substrat support par l'intermédiaire d'une couche électriquement isolante (12, 102, 202), le substrat support comprenant des moyens de conduction électrique entre ladite première face et une deuxième face, la couche de matériau semiconducteur reportée servant de support d' épitaxié pour le matériau semiconducteur épitaxié (14, 15 ; 104, 105 ; 204, 205, 210) ,1. Power semiconductor device produced in epitaxial semiconductor material on a stacked structure, characterized in that: - the stacked structure comprises a layer of semiconductor material (13, 103, 203) transferred onto a first face of a support substrate ( 11, 101, 201) and integral with the support substrate by means of an electrically insulating layer (12, 102, 202), the support substrate comprising means of electrical conduction between said first face and a second face, the layer of deferred semiconductor material serving as an epitaxial support for the epitaxial semiconductor material (14, 15; 104, 105; 204, 205, 210),
- des moyens de connexion électrique (16, 17 ; 117, 118 ; 217, 208) du dispositif sont prévus, d'une part sur le matériau semiconducteur épitaxié, et d'autre part, sur la deuxième face du substrat support, une liaison électrique (19, 109, 209) au travers de la couche électriquement isolante et lesdits moyens de conduction électrique du substrat support reliant électriquement le matériau semiconducteur épitaxié aux moyens de connexion électrique (17, 117, 217) prévus sur la deuxième face du substrat support.- electrical connection means (16, 17; 117, 118; 217, 208) of the device are provided, on the one hand on the epitaxial semiconductor material, and on the other hand, on a second face of the support substrate, a connection electrical (19, 109, 209) through the electrically insulating layer and said electrical conduction means of the support substrate electrically connecting the epitaxial semiconductor material to the electrical connection means (17, 117, 217) provided on the second face of the support substrate .
2. Dispositif selon la revendication 1, caractérisé en ce que les moyens de conduction électrique du substrat support (11, 101, 201) sont constitués par le substrat support lui-même qui est en matériau conducteur électrique. 2. Device according to claim 1, characterized in that the electrical conduction means of the support substrate (11, 101, 201) consist of the support substrate itself which is made of electrically conductive material.
3. Dispositif selon la revendication 1, caractérisé en ce que le matériau semiconducteur épitaxié comporte plusieurs couches de dopage différent (14, 15 ; 104, 105 ; 204, 205, 210) .3. Device according to claim 1, characterized in that the epitaxial semiconductor material comprises several different doping layers (14, 15; 104, 105; 204, 205, 210).
4. Dispositif selon la revendication 1, caractérisé en ce que le substrat support (11, 101, 201) est surdopé du côté de l'interface avec la couche électriquement isolante (12, 102, 202) .4. Device according to claim 1, characterized in that the support substrate (11, 101, 201) is overdoped on the side of the interface with the electrically insulating layer (12, 102, 202).
5. Dispositif selon la revendication 1, caractérisé les moyens de connexion électrique du dispositif comprennent au moins un contact Schottky (108) .5. Device according to claim 1, characterized the electrical connection means of the device comprise at least one Schottky contact (108).
6. Dispositif selon la revendication 1, caractérisé en ce que les moyens de conduction électrique du dispositif comprennent au moins un contact ohmique (16, 17 ; 117 ; 208, 217) .6. Device according to claim 1, characterized in that the electrical conduction means of the device comprise at least one ohmic contact (16, 17; 117; 208, 217).
7. Dispositif selon la revendication 1, caractérisé en ce que le substrat support est en matériau semiconducteur.7. Device according to claim 1, characterized in that the support substrate is made of semiconductor material.
8. Dispositif selon la revendication 7, caractérisé en ce que le substrat support (11, 101, 201) est en un matériau semiconducteur choisi parmi SiC, GaN, AIN, Si, GaAs, ZnO et Ge . 258. Device according to claim 7, characterized in that the support substrate (11, 101, 201) is made of a semiconductor material chosen from SiC, GaN, AIN, Si, GaAs, ZnO and Ge. 25
9. Dispositif selon la revendication 1, caractérisé en ce que la couche électriquement isolante (12, 102, 202) est en matériau choisi parmi Si02, Si3N4 et le diamant.9. Device according to claim 1, characterized in that the electrically insulating layer (12, 102, 202) is made of a material chosen from Si0 2 , Si 3 N 4 and diamond.
10. Dispositif selon la revendication 1, caractérisé en ce que la couche mince de matériau semiconducteur reportée (13, 103, 203) est en un matériau choisi parmi SiC, GaN, AIN, Si, ZnO et le diamant.10. Device according to claim 1, characterized in that the thin layer of transferred semiconductor material (13, 103, 203) is made of a material chosen from SiC, GaN, AIN, Si, ZnO and diamond.
11. Dispositif selon la revendication 1, caractérisé en ce que le matériau semiconducteur épitaxié est choisi parmi SiC, GaN, AlGaN, InGaN et le diamant.11. Device according to claim 1, characterized in that the epitaxial semiconductor material is chosen from SiC, GaN, AlGaN, InGaN and diamond.
12. Circuit semiconducteur, caractérisé en ce qu'il associe, sur une même structure empilée au moins un dispositif semiconducteur de puissance selon l'une quelconque des revendications 1 à 11 et au moins un dispositif semiconducteur qui n'est pas électriquement relié à la deuxième face du substrat support . 12. Semiconductor circuit, characterized in that it combines, on the same stacked structure at least one power semiconductor device according to any one of claims 1 to 11 and at least one semiconductor device which is not electrically connected to the second face of the support substrate.
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