Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/50—PIN diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• the present invention relates to a quasi-vertical power semiconductor device on a composite substrate.
• the manufacturing channels for Sic-based power devices are currently carried out on massive monocrystalline Sic substrates, of polytype 4H and of low electrical volume resistivity.
• This type of substrate allows the manufacture of electronic devices, for example, of the Schottky diode, PIN diode or transistor type such as power MOS, JFET or MESFET, components using during their operation a vertical passage of electric current between the front face. and the back side of this substrate.
• Figure 1 is a cross-sectional view of such a power semiconductor device.
• the diode is produced from a solid substrate 1 of n + type Sic on which two layers of SiC 2 and 3 have been successively epitaxied.
• Layer 2 is n + doped and layer 3 is n " doped.
• the rear face of substrate 1 is metallized to provide ohmic contact 4.
• a metal pad 5 is deposited on layer 3 to make a Schottky contact.
• a localized implantation of the layer 3 provides a p-type zone 6 ensuring peripheral protection.
• This vertical design of the device is particularly suitable for discrete components which, after collective manufacture on an entire slice of monocrystalline Sic, are separated from each other by cutting chips.
• the electrical connection of these chips with the housing is then made in a standard manner by contacting the front and rear faces, in the same way as for discrete silicon components.
• the advantages of the "solid substrate” sector consist in the vertical structure of the device (ease of admission of high currents and assembly in a housing similar to the silicon standard) and in the fact that the substrate allows homoepitaxy of SiC.
• the disadvantages of this sector are the cost, the small diameter of the substrates, their low availability and the impossibility of integrating the components in a system approach.
• An alternative route of substrates for the above applications is the use of composite substrates having a semiconductor thin film bonded to a substrate and obtained by Smar-Cut method. "This method is disclosed in FR-A-2 681 472 (corresponding to US Pat. No. 5,374,564).
• the thin layer and the initial substrate can be made of different materials thanks to the complete freedom offered for the production of composite substrates by this process. among others, to produce substrates called SiCOI (from the English "Sic On Insulator") made up of a thin layer of Sic glued on an electrically insulating substrate seen from the thin layer, like, for example, an oxidized silicon substrate .
• the thickness of the monocrystalline Sic layer is less than 1 ⁇ m, typically 0.5 ⁇ m.
• This SiCOI structure enables electrical components to be produced using the transferred thin layer as an active layer.
• the electronic components are confined in this very thin layer, with the inherent advantages and disadvantages.
• the advantages are constituted by the simplicity of the manufacturing process and by the fact that, the components being isolated, it is possible to produce integrated circuits.
• This sector has the following drawbacks. Since the electrical contacts exit on the same side of the component, it is therefore not possible to integrate them into standard silicon packages.
• the thin thickness of the thin film limits the performance of the components in terms of current flow through the thin film.
• an electronic device with vertical conduction is proposed, produced on a composite substrate of the semiconductor-over-insulator type and comprising two electrical contacts taken on the front face with electrical connection of one of the contacts to an electrically conductive support substrate, after opening of the insulating layer.
• the subject of the invention is therefore a power semiconductor device produced in epitaxial semiconductor material on a stacked structure, characterized in that:
• the stacked structure comprises a layer of semiconductor material transferred onto a first face of a support substrate and secured to the support substrate by means of an electrically insulating layer, the support substrate comprising means of electrical conduction between said first face and a second face, the layer of transferred semiconductor material serving as epitaxial support for the epitaxial semiconductor material, means for electrical connection of the device are provided, on the one hand on the epitaxial semiconductor material, and on the other hand, on the second face of the support substrate, an electrical connection through the electrically insulating layer and said means of electrical conduction of the support substrate electrically connecting the epitaxial semiconductor material to the electrical connection means provided on the second face of the support substrate.
• the means of electrical conduction of the support consist of the support substrate itself which is made of electrically conductive material.
• the epitaxial semiconductor material can comprise several different doping layers.
• the support substrate is overdoped on the side of the interface with the electrically insulating layer.
• the electrical conduction means of the device can comprise at least one Schottky contact and / or at least one ohmic contact.
• the support substrate is made of semiconductor material, chosen for example from SiC, GaN, AIN, Si, GaAs, ZnO and Ge.
• the electrically insulating layer can be of a material chosen from Si0 2 , Si 3 N 4 and diamond.
• the thin layer of transferred semiconductor material can be of a material chosen from SiC, GaN, AIN, Si, ZnO and diamond.
• the epitaxial semiconductor material can be chosen from SiC, GaN, AlGaN, InGaN and diamond.
• the invention also relates to a semiconductor circuit, characterized in that it combines, on the same stacked structure at least one power semiconductor device as defined above and at least one semiconductor device which is not electrically connected to the second face of the support substrate.
• FIG. 1, already described, is a cross-section view of a power semiconductor device according to the prior art
• FIG. 2 is a cross-section view of a power semiconductor device according to the invention
• FIGS. 3A to 3J are cross-sectional views illustrating a method for producing a power semiconductor device according to
• Figure 4 is a cross-sectional view of another power semiconductor device according to the invention
• Figure 5 is a cross-sectional view of a semiconductor device can be associated with a power semiconductor device according to the invention in order to produce an integrated circuit.
• Figure 2 is a cross-sectional view of a power semiconductor device according to the invention.
• the device is manufactured on the front face of a composite substrate 10.
• the support substrate 11 is made of silicon and supports a silicon oxide layer 12 and an SiC layer 13 transferred, for example, by the Smart-Cut method ", on the support substrate 11 and integral with the supporting substrate by the oxide layer 12.
• the transferred Sic layer 13 serves as an epitaxial support for the n + doped SiC 14 layer and for the n " doped SiC 15 layer.
• the inventors of the present invention have succeeded in carrying out epitaxies of SiC on this composite substrate unexpectedly.
• the silicon oxide did not deteriorate for epitaxy temperatures slightly lower than the melting temperature of the silicon and the epitaxies obtained are of good quality, comparable to epitaxies on solid SiC.
• the device also comprises a Schottky contact 16 disposed on the SiC layer 15 and an ohmic contact 17 disposed on the rear face of the support substrate 11.
• Ohmic contacts 18 are arranged on the upper face of the SiC layer 14. They allow a electrical connection of the SiC layer 14 with the ohmic contact 17 on the rear face thanks to metallizations 19 deposited on the ohmic contacts 18, making contact with the support substrate 11 through the oxide layer 12, and thanks to the support substrate 11 which is sufficiently conductive. Of more, the contact between the metallizations 19 and the support substrate 11 is an ohmic contact.
• This power device can therefore be described as a quasi-vertical device.
• FIGS. 3A to 3J are cross-sectional views illustrating a method for producing a power semiconductor device according to the invention.
• the device produced in this example comprises layers of SiC epitaxially grown on a layer of SiC transferred onto a silicon support substrate.
• FIG. 3A shows a composite substrate 100 formed of a silicon support substrate 101 supporting a layer of silicon oxide 102 used for bonding a layer of transferred SiC 103.
• the transferred SiC layer 103 serves as an epitaxial support for the SiC layer 104 and for the SiC layer 105 epitaxied on the layer 104.
• the transferred SiC layer 103 has an n doping of the order of 10 17 to 10 19 atoms / cm 3 and a thickness of between 0.5 and 1 ⁇ m.
• the support substrate 101 has an n doping of the order of 10 20 atoms / cm 3 and a thickness between 200 and 500 ⁇ m.
• the oxide layer 103 has a thickness of between 2 and 4 ⁇ m, for example 2 ⁇ m.
• the support substrate 101 can, on the side of the interface with the oxide layer 102, be overdoped if necessary before assembly of the composite substrate 100 in order to facilitate posterior ohmic contact (see FIG. 3G).
• the SiC layers 104 and 105 are successively epitaxial.
• the epitaxy is carried out below 1410 ° C. for a support substrate 101 made of silicon.
• the layer of SiC 104 is doped n + (doping between 5.10 18 and 5.10 20 atoms / cm 3 ) and has a thickness of approximately 4 ⁇ m
• the layer of SiC 105 is doped n " (doping of the order of 10 16 atoms / cm 3 ) and has a thickness of approximately 6 ⁇ m. This pair of values is given for information for a Schottky diode of the 600 volt type. These values are at adjust according to the desired tensile strength.
• FIG. 3B relates to a first level of lithography making it possible to define “Mesa” structures by etching the layer of SiC 105 until reaching the layer of SiC 104.
• the “Mesa” structure allows the voltage withstand of the component and the fact of exposing the layer of SiC 104 will subsequently make it possible to produce an ohmic contact. Etching can be done by plasma.
• the next step consists in depositing an inorganic layer 106, for example a layer of Si0 2 or Si 3 N, with a thickness of several ⁇ m, for example from 2 to 4 ⁇ m. This layer will have, among other things, the passivation function of the component (see Figure 3C).
• FIG. 3D relates to a second level of lithography making it possible to define the etching zones of the layers 106, 104 and 103. This is a first step towards making contact with the support substrate 101. This also makes it possible to electrically isolate the component from its neighbors in the case where you want to integrate several on the same circuit.
• layer 106 is etched.
• the etching can be obtained by wet etching in HF solution or by plasma etching.
• the masking resin is then removed and the SiC layers 104 and 103 are then successively etched using the layer 106 as a mask.
• the etching is done by plasma.
• the structure obtained is shown in Figure 3D.
• FIG. 3E relates to a third level of lithography making it possible to define different openings in the layers 102 and 106 for future electrical contacts.
• FIG. 3E shows the structure obtained after development of the resin layer 107.
• FIG. 3G relates to a fourth level of lithography making it possible to produce an ohmic contact.
• the deposited metal can be, Ni or Ti. Its thickness can be between 100 and 500 nm. The deposition can be done by evaporation or sputtering. Lithography makes it possible to define the ohmic contact zones with the layer of SiC 104 at 116 and also the connection to the ohmic contact with the support substrate 101 at 112.
• Figure 3G shows the structure obtained with etching of the deposited metal and removal of the resin. It shows the metallic deposit 109 connecting the SiC layer 104 to the support substrate 101.
• the etching of the metal can be done in a conventional manner, for example by wet etching for Ni and Ti or by plasma for W.
• An annealing is then applied in view to activate the ohmic contact with the SiC of layer 104, in the range between 900 and 1100 ° C for Ni and Ti, in the range between 1000 and 1300 ° C for W. Simultaneously, the ohmic contact with silicon of the support substrate 101 is activated.
• FIG. 3H relates to a fifth level of lithography making it possible to obtain a Schottky contact.
• a Schottky contact metal which can be Ti or Ni, is deposited on the structure obtained above, by sputtering or by evaporation, over a thickness of between 100 and
• a lithography is carried out, then an etching of this metal so as to form Schottky contact pads 108 on the layer of SiC 105.
• a Schottky contact annealing is then applied, for example, at a temperature between 400 to 600 ° C.
• a metallization layer 117 is deposited on the rear face of the support substrate 101 (see FIG. 31) in order to make an ohmic contact on the rear face.
• This layer can be made of Al, Ti or Ni. Annealing may be necessary to improve the ohmic contact.
• an over-metallization may be necessary to reinforce the metallizations of the front face of the device.
• FIG. 3J shows an over-metallization 118 reinforcing the Schottky contact pad 108 and an over-metallization 119 reinforcing the deposit 109 ensuring the ohmic contact towards the SiC layer 104 and the connection towards the support substrate 101.
• This over-metallization can be aluminum, with a thickness between 0.5 and 5 ⁇ m.
• Figure 3J shows the structure obtained after lithography and etching.
• a variant of this production method is made possible if the doping of the SiC layer 104 is sufficiently high to allow good ohmic contact with Ti annealed at around 500 ° C.
• the doping necessary for this is of the order of 5.10 19 atoms / cm 3 or more. This doping is accessible on Sic obtained by epitaxy. It is important to note that such doping cannot be obtained on a solid SiC substrate. However, it is on this substrate that the ohmic contact is made in the prior art. In the case of the present invention, the same metal can be used for Schottky contact and for ohmic contact, with a single annealing at approximately 500 ° C. This variant is implemented from the structure illustrated in FIG. 3F.
• a single metallic deposit is made, for example, of Ti or Ni or a bilayer of one of these metals and of another metal.
• a lithography is carried out. It makes it possible to simultaneously define the Schottky pads and the ohmic contact pads. After engraving and annealing to approximately 500 ° C., the structure illustrated in FIG. 3H is obtained directly with one complete level of lithography less (one deposit, one lithography, one etching and one annealing less). The end of the process remains identical with the rear side metallization and possibly an over-metallization.
• peripheral protections which consist of p-doping zones produced at the periphery of the Schottky contact. These protections can either be carried out by localized implantation, or by an additional epitaxial type p made in the wake of the epitaxial layer of SiC 105, the layer p then being locally etched in the area of the Schottky contact.
• peripheral protections 120 It is possible to produce these peripheral protections in the context of the present invention, without particular difficulty compared to conventional components of the vertical type.
• implanted peripheral protections 120 In FIG. 3J, implanted peripheral protections 120 have been shown in broken lines.
• the invention also allows the production of a device comprising layers of SiC epitaxially grown on a layer of SiC transferred onto a support substrate of SiC.
• a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate in Sic.
• the epitaxy is carried out on the transferred SiC layer.
• As many layers of SiC as necessary are epitaxied.
• the structure then consists of a support substrate 101 made of SiC, an oxide layer 102, a layer of transferred SiC 103, a first layer of epitaxied SiC 104 and a second layer of epitaxied SiC 105.
• Epitaxy can be performed above 1410 ° C, typically in the range between 1400 and 1600 ° C.
• the layer of SiC 104 can be doped n + according to a doping of 10 19 atoms / cm 3 and can have a thickness of approximately 4 ⁇ m.
• the SiC 105 layer can be doped n " according to a doping of 10 16 atoms / cm 3 and can have a thickness of approximately 6 ⁇ m.
• the invention also allows the production of a device comprising layers of GaN epitaxially grown on a layer of Sic transferred onto a support substrate of SiC. For this, a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate of SiC. The epitaxy is carried out on the transferred SiC layer. As many layers of GaN as necessary are epitaxied.
• the structure then consists of a support substrate 101 in SiC, a layer of oxide 102, a layer of transferred SiC 103, a first layer of epitaxial GaN 104 and of a second layer of epitaxial GaN 105.
• An AIN buffer layer can be interposed between the transferred SiC layer and the GaN to improve epitaxial growth.
• the support substrate 101 made of SiC can be overdoped as described above.
• the technique applied is similar to the cases described above, but with adaptations relating to ohmic contacts and GaN etchings instead of SiC.
• the invention also allows the production of a device comprising layers of GaN epitaxially grown on a layer of Si ⁇ III ⁇ transferred onto a support substrate of SiC.
• a layer of SiC is transferred and bonded via a layer of silicon oxide on a support substrate of SiC.
• the epitaxy is carried out on the transferred Si ⁇ lll ⁇ layer.
• As many layers of GaN as necessary are epitaxied.
• the structure then consists of a support substrate 101 in SiC, a layer of oxide 102, a layer of transferred Si ⁇ lll ⁇ 103, a first layer of epitaxial GaN 104 and a second layer of epitaxial GaN 105.
• the epitaxy can be carried out by MOCVD above 1000 ° C., typically in the range between 1050 and 1150 ° C.
• the layers 104 and 105 can be similar to the same layers of the previous example.
• An AIN buffer layer can also be interposed between the transferred Si ⁇ lll ⁇ layer and the GaN to improve epitaxial growth.
• the support substrate 101 in SiC can be overdoped as has already been described above.
• the thin layer of transferred semiconductor material is chosen from the following materials: SiC of polytype 3C, 4H or 6H, GaN, AIN, Si, ZnO and diamond.
• the intermediate bonding layer is made of a material chosen from Si0 2 , Si 3 N 4 and diamond.
• the electrically conductive support substrate, monocrystalline or not, is chosen from the following materials: SiC, GaN, AIN, Si, GaAs, ZnO and Ge.
• Figure 4 is a cross-sectional view of another power semiconductor device according to the invention. It is a bipolar PIN type diode.
• This device is produced on a silicon support substrate 201 supporting a transferred layer 203 of SiC made integral with the support substrate by a layer of silicon oxide 202.
• a layer of SiC 204 On the transferred layer 203 are successively epitaxied a layer of SiC 204, a layer of SiC 205 doped n "and a doped SiC layer 210 p.
• the thickness and doping of the SiC layer 205 are adapted to the desired breakdown voltage, as in the case of conventional vertical PIN diodes.
• the manufacturing process is analogous to the manufacturing process for the structures described above, the main difference being the presence of the epitaxial layer 210 made of p-type SiC on which we must make an ohmic contact 208 under the same conditions as on a vertical PIN diode.
• a semiconductor support substrate 301 supporting a transferred layer 303 of semiconductor material is recognized, made integral with the support substrate by an electrically insulating layer 302.
• a semiconductor layer 304 for example doped n +
• a semiconductor layer 305 for example n " doped.
• the layer 305 supports a Schottky contact 308 while the layer 304 supports an ohmic contact 309.

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• 2002
  • 2002-09-03 FR FR0210883A patent/FR2844099B1/fr not_active Expired - Fee Related
• 2003
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  • 2003-09-01 EP EP03780259A patent/EP1535346A2/de not_active Withdrawn
  • 2003-09-01 WO PCT/FR2003/050045 patent/WO2004027878A2/fr not_active Ceased
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