DE69933777D1 - Verfahren zur herstellung von einem silizium wafer mit idealem sauerstoffniederschlagverhalten - Google Patents

Verfahren zur herstellung von einem silizium wafer mit idealem sauerstoffniederschlagverhalten

Info

Publication number
DE69933777D1
DE69933777D1 DE69933777T DE69933777T DE69933777D1 DE 69933777 D1 DE69933777 D1 DE 69933777D1 DE 69933777 T DE69933777 T DE 69933777T DE 69933777 T DE69933777 T DE 69933777T DE 69933777 D1 DE69933777 D1 DE 69933777D1
Authority
DE
Germany
Prior art keywords
producing
silicon wafer
oxygen layer
layer behavior
ideal oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69933777T
Other languages
English (en)
Other versions
DE69933777T2 (de
Inventor
J Falster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SunEdison Inc
Original Assignee
SunEdison Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SunEdison Inc filed Critical SunEdison Inc
Publication of DE69933777D1 publication Critical patent/DE69933777D1/de
Application granted granted Critical
Publication of DE69933777T2 publication Critical patent/DE69933777T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE69933777T 1998-09-02 1999-08-27 Verfahren zur herstellung von einem silizium wafer mit idealem sauerstoffausfällungsverhalten Expired - Lifetime DE69933777T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9886198P 1998-09-02 1998-09-02
US98861P 1998-09-02
PCT/US1999/019842 WO2000013226A1 (en) 1998-09-02 1999-08-27 Process for preparing an ideal oxygen precipitating silicon wafer

Publications (2)

Publication Number Publication Date
DE69933777D1 true DE69933777D1 (de) 2006-12-07
DE69933777T2 DE69933777T2 (de) 2007-09-13

Family

ID=22271299

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69933777T Expired - Lifetime DE69933777T2 (de) 1998-09-02 1999-08-27 Verfahren zur herstellung von einem silizium wafer mit idealem sauerstoffausfällungsverhalten

Country Status (8)

Country Link
US (3) US6191010B1 (de)
EP (1) EP1110240B1 (de)
JP (1) JP4405083B2 (de)
KR (1) KR100957729B1 (de)
CN (1) CN1155064C (de)
DE (1) DE69933777T2 (de)
TW (1) TW425636B (de)
WO (1) WO2000013226A1 (de)

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US6436846B1 (en) * 1998-09-03 2002-08-20 Siemens Aktiengesellscharft Combined preanneal/oxidation step using rapid thermal processing
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US6897084B2 (en) * 2001-04-11 2005-05-24 Memc Electronic Materials, Inc. Control of oxygen precipitate formation in high resistivity CZ silicon
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US7196022B2 (en) * 2001-12-20 2007-03-27 Kimberly-Clark Worldwide, Inc. Products for controlling microbial generated odors
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WO2004044276A1 (en) * 2002-11-12 2004-05-27 Memc Electronic Materials, Inc. A crystal puller and method for growing a monocrystalline ingot
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US6955718B2 (en) 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
DE10336271B4 (de) * 2003-08-07 2008-02-07 Siltronic Ag Siliciumscheibe und Verfahren zu deren Herstellung
KR101045309B1 (ko) * 2004-02-03 2011-06-29 신에쯔 한도타이 가부시키가이샤 반도체 웨이퍼의 제조 방법 및 반도체 잉곳의 절단 위치결정 시스템
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JP4617751B2 (ja) * 2004-07-22 2011-01-26 株式会社Ｓｕｍｃｏ シリコンウェーハおよびその製造方法
US7846822B2 (en) * 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
JP5117671B2 (ja) * 2004-10-19 2013-01-16 シルトロン インク 高品質単結晶及びその成長方法
US20060138601A1 (en) * 2004-12-27 2006-06-29 Memc Electronic Materials, Inc. Internally gettered heteroepitaxial semiconductor wafers and methods of manufacturing such wafers
CN100437941C (zh) * 2005-03-21 2008-11-26 北京有色金属研究总院 一种获得洁净区的硅片快速热处理工艺方法及其产品
JP2008545605A (ja) * 2005-05-19 2008-12-18 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 高抵抗率シリコン構造体およびその製造方法
US7485928B2 (en) * 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
US7968440B2 (en) * 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
JP2009231429A (ja) * 2008-03-21 2009-10-08 Covalent Materials Corp シリコンウェーハの製造方法
JP5561918B2 (ja) * 2008-07-31 2014-07-30 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハの製造方法
US8476149B2 (en) * 2008-07-31 2013-07-02 Global Wafers Japan Co., Ltd. Method of manufacturing single crystal silicon wafer from ingot grown by Czocharlski process with rapid heating/cooling process
US7939432B2 (en) * 2008-12-15 2011-05-10 Macronix International Co., Ltd. Method of improving intrinsic gettering ability of wafer
JP5062217B2 (ja) * 2009-04-30 2012-10-31 株式会社Ｓｕｍｃｏ 半導体ウェーハの製造方法
US8871670B2 (en) 2011-01-05 2014-10-28 The Board Of Trustees Of The University Of Illinois Defect engineering in metal oxides via surfaces
TWI614808B (zh) 2012-11-19 2018-02-11 太陽愛迪生公司 藉由活化非活性氧沉澱核製造高沉澱密度晶圓之方法
CN105316767B (zh) * 2015-06-04 2019-09-24 上海超硅半导体有限公司 超大规模集成电路用硅片及其制造方法、应用
WO2018125565A1 (en) 2016-12-28 2018-07-05 Sunedison Semiconductor Limited Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield
EP4010519A4 (de) 2019-08-09 2023-09-13 Leading Edge Equipment Technologies, Inc. Herstellung eines bandes oder wafers mit bereichen mit geringer sauerstoffkonzentration

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Also Published As

Publication number Publication date
KR20010082183A (ko) 2001-08-29
TW425636B (en) 2001-03-11
CN1317152A (zh) 2001-10-10
US6713370B2 (en) 2004-03-30
JP2002524852A (ja) 2002-08-06
WO2000013226A1 (en) 2000-03-09
EP1110240A1 (de) 2001-06-27
US6579779B1 (en) 2003-06-17
US6191010B1 (en) 2001-02-20
EP1110240B1 (de) 2006-10-25
KR100957729B1 (ko) 2010-05-12
WO2000013226A9 (en) 2001-11-22
JP4405083B2 (ja) 2010-01-27
DE69933777T2 (de) 2007-09-13
CN1155064C (zh) 2004-06-23
US20030221609A1 (en) 2003-12-04

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