DE69807054D1 - Ein ionen-implantierungsschritt vervendentes verfahren zur herstellung von einem-insbesondere halbleiter- dünnschicht mit einem gegen ionen geschüzte gebiet - Google Patents
Ein ionen-implantierungsschritt vervendentes verfahren zur herstellung von einem-insbesondere halbleiter- dünnschicht mit einem gegen ionen geschüzte gebietInfo
- Publication number
- DE69807054D1 DE69807054D1 DE69807054T DE69807054T DE69807054D1 DE 69807054 D1 DE69807054 D1 DE 69807054D1 DE 69807054 T DE69807054 T DE 69807054T DE 69807054 T DE69807054 T DE 69807054T DE 69807054 D1 DE69807054 D1 DE 69807054D1
- Authority
- DE
- Germany
- Prior art keywords
- ion
- producing
- thin layer
- semiconductor thin
- protected against
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005468 ion implantation Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9700837A FR2758907B1 (fr) | 1997-01-27 | 1997-01-27 | Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique |
PCT/FR1998/000129 WO1998033209A1 (fr) | 1997-01-27 | 1998-01-26 | Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69807054D1 true DE69807054D1 (de) | 2002-09-12 |
DE69807054T2 DE69807054T2 (de) | 2003-04-17 |
Family
ID=9502995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69807054T Expired - Lifetime DE69807054T2 (de) | 1997-01-27 | 1998-01-26 | Ein ionen-implantierungsschritt vervendentes verfahren zur herstellung von einem-insbesondere halbleiter- dünnschicht mit einem gegen ionen geschüzte gebiet |
Country Status (7)
Country | Link |
---|---|
US (1) | US6316333B1 (de) |
EP (1) | EP0972304B1 (de) |
JP (1) | JP4310503B2 (de) |
KR (1) | KR100452056B1 (de) |
DE (1) | DE69807054T2 (de) |
FR (1) | FR2758907B1 (de) |
WO (1) | WO1998033209A1 (de) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
TW437078B (en) | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
KR100294637B1 (ko) * | 1998-06-29 | 2001-10-19 | 박종섭 | 모스펫의폴리사이드게이트형성방법 |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
US6346459B1 (en) | 1999-02-05 | 2002-02-12 | Silicon Wafer Technologies, Inc. | Process for lift off and transfer of semiconductor devices onto an alien substrate |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
FR2818010B1 (fr) * | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
FR2823596B1 (fr) * | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
FR2823599B1 (fr) | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
US7045878B2 (en) * | 2001-05-18 | 2006-05-16 | Reveo, Inc. | Selectively bonded thin film layer and substrate layer for processing of useful devices |
US6956268B2 (en) | 2001-05-18 | 2005-10-18 | Reveo, Inc. | MEMS and method of manufacturing MEMS |
US7163826B2 (en) | 2001-09-12 | 2007-01-16 | Reveo, Inc | Method of fabricating multi layer devices on buried oxide layer substrates |
US6875671B2 (en) * | 2001-09-12 | 2005-04-05 | Reveo, Inc. | Method of fabricating vertical integrated circuits |
FR2830983B1 (fr) | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
US7176108B2 (en) | 2002-11-07 | 2007-02-13 | Soitec Silicon On Insulator | Method of detaching a thin film at moderate temperature after co-implantation |
FR2848336B1 (fr) | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2850390B1 (fr) * | 2003-01-24 | 2006-07-14 | Soitec Silicon On Insulator | Procede d'elimination d'une zone peripherique de colle lors de la fabrication d'un substrat composite |
US7122095B2 (en) * | 2003-03-14 | 2006-10-17 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Methods for forming an assembly for transfer of a useful layer |
JP4794810B2 (ja) * | 2003-03-20 | 2011-10-19 | シャープ株式会社 | 半導体装置の製造方法 |
FR2856844B1 (fr) | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
FR2857953B1 (fr) | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7772087B2 (en) | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
JP4545449B2 (ja) * | 2004-01-28 | 2010-09-15 | シャープ株式会社 | 半導体装置の製造方法 |
JP4319078B2 (ja) | 2004-03-26 | 2009-08-26 | シャープ株式会社 | 半導体装置の製造方法 |
US7179719B2 (en) * | 2004-09-28 | 2007-02-20 | Sharp Laboratories Of America, Inc. | System and method for hydrogen exfoliation |
JP5113999B2 (ja) * | 2004-09-28 | 2013-01-09 | シャープ株式会社 | 水素イオン注入剥離方法 |
US7071047B1 (en) * | 2005-01-28 | 2006-07-04 | International Business Machines Corporation | Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions |
JP4943663B2 (ja) * | 2005-04-06 | 2012-05-30 | シャープ株式会社 | 半導体装置の製造方法及び半導体装置並びに液晶表示装置 |
FR2886051B1 (fr) | 2005-05-20 | 2007-08-10 | Commissariat Energie Atomique | Procede de detachement d'un film mince |
FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
DE102005052358A1 (de) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
DE102005052357A1 (de) | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
FR2891281B1 (fr) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
DE102005054218B4 (de) * | 2005-11-14 | 2011-06-09 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiterelements und Halbleiterelement |
DE102005054219B4 (de) * | 2005-11-14 | 2011-06-22 | Infineon Technologies AG, 81669 | Verfahren zum Herstellen eines Feldeffekttransistors und Feldeffekttransistor |
FR2899378B1 (fr) | 2006-03-29 | 2008-06-27 | Commissariat Energie Atomique | Procede de detachement d'un film mince par fusion de precipites |
FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
US7662680B2 (en) * | 2007-09-28 | 2010-02-16 | Infineon Technologies Ag | Method of producing a semiconductor element in a substrate and a semiconductor element |
US8455331B2 (en) * | 2007-10-10 | 2013-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US20090124038A1 (en) * | 2007-11-14 | 2009-05-14 | Mark Ewing Tuttle | Imager device, camera, and method of manufacturing a back side illuminated imager |
FR2925221B1 (fr) | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
US20090212397A1 (en) * | 2008-02-22 | 2009-08-27 | Mark Ewing Tuttle | Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit |
US7749884B2 (en) * | 2008-05-06 | 2010-07-06 | Astrowatt, Inc. | Method of forming an electronic device using a separation-enhancing species |
EP2294607A2 (de) * | 2008-05-17 | 2011-03-16 | Astrowatt, Inc. | Verfahren zur bildung einer elektronischen anordnung unter verwendung einer trennungstechnik |
CN102099894B (zh) * | 2008-08-27 | 2014-04-16 | S.O.I.Tec绝缘体上硅技术公司 | 制造半导体结构或使用具有选择或受控晶格参数的半导体材料层的器件的方法 |
FR2936357B1 (fr) * | 2008-09-24 | 2010-12-10 | Commissariat Energie Atomique | Procede de report de puces sur un substrat. |
JP4519932B2 (ja) * | 2008-10-23 | 2010-08-04 | シャープ株式会社 | 半導体装置 |
JP5277999B2 (ja) * | 2009-01-29 | 2013-08-28 | 株式会社村田製作所 | 複合基板の製造方法 |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
JP4515525B2 (ja) * | 2009-04-16 | 2010-08-04 | シャープ株式会社 | 半導体装置 |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
WO2011061580A1 (en) | 2009-11-18 | 2011-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods |
FR2978600B1 (fr) | 2011-07-25 | 2014-02-07 | Soitec Silicon On Insulator | Procede et dispositif de fabrication de couche de materiau semi-conducteur |
TWI573198B (zh) * | 2011-09-27 | 2017-03-01 | 索泰克公司 | 在三度空間集積製程中轉移材料層之方法及其相關結構與元件 |
WO2014020387A1 (en) | 2012-07-31 | 2014-02-06 | Soitec | Methods of forming semiconductor structures including mems devices and integrated circuits on opposing sides of substrates, and related structures and devices |
US10833175B2 (en) * | 2015-06-04 | 2020-11-10 | International Business Machines Corporation | Formation of dislocation-free SiGe finFET using porous silicon |
KR102578576B1 (ko) | 2017-12-01 | 2023-09-15 | 실리콘 제너시스 코포레이션 | 3차원 집적 회로 |
Family Cites Families (18)
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FR2461360A1 (fr) * | 1979-07-10 | 1981-01-30 | Thomson Csf | Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede |
JPS5955070A (ja) * | 1982-09-24 | 1984-03-29 | Toshiba Corp | 半導体装置の製造方法 |
FR2563377B1 (fr) * | 1984-04-19 | 1987-01-23 | Commissariat Energie Atomique | Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique |
FR2604022B1 (fr) * | 1986-09-16 | 1992-09-11 | Eurotechnique Sa | Memoire non volatile a grille flottante sans oxyde epais |
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
FR2664095B1 (fr) * | 1990-06-28 | 1993-12-17 | Commissariat A Energie Atomique | Procede de fabrication d'un contact electrique sur un element actif d'un circuit integre mis. |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
FR2714524B1 (fr) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
JPH08153804A (ja) * | 1994-09-28 | 1996-06-11 | Sony Corp | ゲート電極の形成方法 |
FR2750535B1 (fr) * | 1996-06-27 | 1998-08-07 | Commissariat Energie Atomique | Transistor mos et procede d'isolation laterale d'une region active d'un transistor mos |
FR2752644B1 (fr) * | 1996-08-21 | 1998-10-02 | Commissariat Energie Atomique | Procede de realisation d'un transistor a contacts auto-alignes |
US5714412A (en) * | 1996-12-02 | 1998-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-level, split-gate, flash memory cell and method of manufacture thereof |
US6013563A (en) * | 1997-05-12 | 2000-01-11 | Silicon Genesis Corporation | Controlled cleaning process |
US5888853A (en) * | 1997-08-01 | 1999-03-30 | Advanced Micro Devices, Inc. | Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof |
US6242298B1 (en) * | 1997-08-29 | 2001-06-05 | Kabushiki Kaisha Toshiba | Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same |
US6171982B1 (en) * | 1997-12-26 | 2001-01-09 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
US6083324A (en) * | 1998-02-19 | 2000-07-04 | Silicon Genesis Corporation | Gettering technique for silicon-on-insulator wafers |
US6093623A (en) * | 1998-08-04 | 2000-07-25 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
-
1997
- 1997-01-27 FR FR9700837A patent/FR2758907B1/fr not_active Expired - Fee Related
-
1998
- 1998-01-26 KR KR10-1999-7006667A patent/KR100452056B1/ko not_active IP Right Cessation
- 1998-01-26 US US09/341,555 patent/US6316333B1/en not_active Expired - Lifetime
- 1998-01-26 WO PCT/FR1998/000129 patent/WO1998033209A1/fr active IP Right Grant
- 1998-01-26 EP EP98904214A patent/EP0972304B1/de not_active Expired - Lifetime
- 1998-01-26 JP JP53168098A patent/JP4310503B2/ja not_active Expired - Lifetime
- 1998-01-26 DE DE69807054T patent/DE69807054T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2758907A1 (fr) | 1998-07-31 |
JP4310503B2 (ja) | 2009-08-12 |
EP0972304B1 (de) | 2002-08-07 |
KR20000070432A (ko) | 2000-11-25 |
WO1998033209A1 (fr) | 1998-07-30 |
DE69807054T2 (de) | 2003-04-17 |
KR100452056B1 (ko) | 2004-10-08 |
EP0972304A1 (de) | 2000-01-19 |
JP2001508943A (ja) | 2001-07-03 |
FR2758907B1 (fr) | 1999-05-07 |
US6316333B1 (en) | 2001-11-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |