DE69840399D1 - Verfahren zur Herstellung einer Gate-Elektrode - Google Patents

Verfahren zur Herstellung einer Gate-Elektrode

Info

Publication number
DE69840399D1
DE69840399D1 DE69840399T DE69840399T DE69840399D1 DE 69840399 D1 DE69840399 D1 DE 69840399D1 DE 69840399 T DE69840399 T DE 69840399T DE 69840399 T DE69840399 T DE 69840399T DE 69840399 D1 DE69840399 D1 DE 69840399D1
Authority
DE
Germany
Prior art keywords
producing
gate electrode
gate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840399T
Other languages
English (en)
Inventor
Jiong-Ping Lu
Ming Hwang
Dirk Noel Anderson
Jorge A Kittl
Hun-Lian Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69840399D1 publication Critical patent/DE69840399D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
DE69840399T 1997-10-07 1998-10-07 Verfahren zur Herstellung einer Gate-Elektrode Expired - Lifetime DE69840399D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6155797P 1997-10-07 1997-10-07

Publications (1)

Publication Number Publication Date
DE69840399D1 true DE69840399D1 (de) 2009-02-12

Family

ID=22036537

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840399T Expired - Lifetime DE69840399D1 (de) 1997-10-07 1998-10-07 Verfahren zur Herstellung einer Gate-Elektrode

Country Status (4)

Country Link
US (1) US6187656B1 (de)
EP (1) EP0908934B1 (de)
JP (1) JPH11233451A (de)
DE (1) DE69840399D1 (de)

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US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
US6432803B1 (en) * 1998-12-14 2002-08-13 Matsushita Electric Industrial Co., Inc. Semiconductor device and method of fabricating the same
JP2001102580A (ja) * 1999-09-30 2001-04-13 Nec Corp 半導体装置及びその製造方法
KR100500924B1 (ko) * 1999-12-30 2005-07-14 주식회사 하이닉스반도체 메모리소자의 텅스텐 전극 형성방법
US6376370B1 (en) * 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US7262130B1 (en) * 2000-01-18 2007-08-28 Micron Technology, Inc. Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
US6420262B1 (en) * 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US7211512B1 (en) * 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US6376349B1 (en) * 2000-01-19 2002-04-23 Motorola, Inc. Process for forming a semiconductor device and a conductive structure
JP4592864B2 (ja) * 2000-03-16 2010-12-08 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US6274484B1 (en) * 2000-03-17 2001-08-14 Taiwan Semiconductor Manufacturing Company Fabrication process for low resistivity tungsten layer with good adhesion to insulator layers
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
US6674167B1 (en) * 2000-05-31 2004-01-06 Micron Technology, Inc. Multilevel copper interconnect with double passivation
KR100632618B1 (ko) * 2000-06-30 2006-10-09 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성 방법
JP2002016248A (ja) 2000-06-30 2002-01-18 Mitsubishi Electric Corp 半導体装置の製造方法
US6774442B2 (en) 2000-07-21 2004-08-10 Renesas Technology Corp. Semiconductor device and CMOS transistor
US6511912B1 (en) * 2000-08-22 2003-01-28 Micron Technology, Inc. Method of forming a non-conformal layer over and exposing a trench
KR100631937B1 (ko) * 2000-08-25 2006-10-04 주식회사 하이닉스반도체 텅스텐 게이트 형성방법
EP1294015A1 (de) * 2001-09-12 2003-03-19 Infineon Technologies AG Verfahren zur Strukturierung einer leitenden Schicht aus polykristallinem Material
US6716734B2 (en) 2001-09-28 2004-04-06 Infineon Technologies Ag Low temperature sidewall oxidation of W/WN/poly-gatestack
US6509282B1 (en) 2001-11-26 2003-01-21 Advanced Micro Devices, Inc. Silicon-starved PECVD method for metal gate electrode dielectric spacer
JP3781666B2 (ja) 2001-11-29 2006-05-31 エルピーダメモリ株式会社 ゲート電極の形成方法及びゲート電極構造
JP3976577B2 (ja) 2002-02-01 2007-09-19 エルピーダメモリ株式会社 ゲート電極の製造方法
JP4559223B2 (ja) * 2002-07-15 2010-10-06 株式会社日立国際電気 半導体装置の製造方法及び基板処理装置
JP4275395B2 (ja) * 2002-12-11 2009-06-10 株式会社ルネサステクノロジ 半導体装置の製造方法
US20040135218A1 (en) * 2003-01-13 2004-07-15 Zhizhang Chen MOS transistor with high k gate dielectric
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
JP4191000B2 (ja) 2003-10-06 2008-12-03 エルピーダメモリ株式会社 半導体装置及びその製造方法
JP4690120B2 (ja) 2005-06-21 2011-06-01 エルピーダメモリ株式会社 半導体装置及びその製造方法
US7675119B2 (en) 2006-12-25 2010-03-09 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
KR100844940B1 (ko) 2006-12-27 2008-07-09 주식회사 하이닉스반도체 다중 확산방지막을 구비한 반도체소자 및 그의 제조 방법
DE102007045074B4 (de) * 2006-12-27 2009-06-18 Hynix Semiconductor Inc., Ichon Halbleiterbauelement mit Gatestapelstruktur
US7820555B2 (en) * 2007-10-11 2010-10-26 International Business Machines Corporation Method of patterning multilayer metal gate structures for CMOS devices
KR100939777B1 (ko) 2007-11-30 2010-01-29 주식회사 하이닉스반도체 텅스텐막 형성방법 및 이를 이용한 반도체 소자의 배선형성방법

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US4663825A (en) * 1984-09-27 1987-05-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2681887B2 (ja) * 1987-03-06 1997-11-26 シ−メンス、アクチエンゲゼルシヤフト ３次元１トランジスタメモリセル構造とその製法
JP2537413B2 (ja) * 1989-03-14 1996-09-25 三菱電機株式会社 半導体装置およびその製造方法
US5462895A (en) * 1991-09-04 1995-10-31 Oki Electric Industry Co., Ltd. Method of making semiconductor device comprising a titanium nitride film
KR940010564B1 (ko) * 1991-10-10 1994-10-24 금성일렉트론 주식회사 전계효과 트랜지스터 및 그 제조방법
KR0179677B1 (ko) * 1993-12-28 1999-04-15 사토 후미오 반도체장치 및 그 제조방법
JP3351635B2 (ja) * 1993-12-28 2002-12-03 株式会社東芝 半導体装置およびその製造方法
US5545592A (en) * 1995-02-24 1996-08-13 Advanced Micro Devices, Inc. Nitrogen treatment for metal-silicide contact
US5733816A (en) * 1995-12-13 1998-03-31 Micron Technology, Inc. Method for depositing a tungsten layer on silicon
US5926730A (en) * 1997-02-19 1999-07-20 Micron Technology, Inc. Conductor layer nitridation
TW322608B (en) * 1997-07-31 1997-12-11 United Microelectronics Corp Manufacturing method of self-aligned salicide
US5913145A (en) * 1997-08-28 1999-06-15 Texas Instruments Incorporated Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures

Also Published As

Publication number Publication date
US6187656B1 (en) 2001-02-13
JPH11233451A (ja) 1999-08-27
EP0908934B1 (de) 2008-12-31
EP0908934A2 (de) 1999-04-14
EP0908934A3 (de) 1999-08-04

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Legal Events

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