ATE520149T1 - Verfahren zur herstellung eines epitaktischen substrats - Google Patents

Verfahren zur herstellung eines epitaktischen substrats

Info

Publication number
ATE520149T1
ATE520149T1 AT04739271T AT04739271T ATE520149T1 AT E520149 T1 ATE520149 T1 AT E520149T1 AT 04739271 T AT04739271 T AT 04739271T AT 04739271 T AT04739271 T AT 04739271T AT E520149 T1 ATE520149 T1 AT E520149T1
Authority
AT
Austria
Prior art keywords
substrate
base substrate
epitactic
producing
preparation
Prior art date
Application number
AT04739271T
Other languages
English (en)
Inventor
Bruce Faure
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE520149T1 publication Critical patent/ATE520149T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/915—Separating from substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT04739271T 2003-06-06 2004-05-19 Verfahren zur herstellung eines epitaktischen substrats ATE520149T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03291371A EP1484794A1 (de) 2003-06-06 2003-06-06 Verfahren zur Herstellung eines Trägersubstrats
PCT/EP2004/005439 WO2004112126A1 (en) 2003-06-06 2004-05-19 A method of preparation of an epitaxial substrate

Publications (1)

Publication Number Publication Date
ATE520149T1 true ATE520149T1 (de) 2011-08-15

Family

ID=33155276

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04739271T ATE520149T1 (de) 2003-06-06 2004-05-19 Verfahren zur herstellung eines epitaktischen substrats

Country Status (8)

Country Link
US (1) US7226509B2 (de)
EP (2) EP1484794A1 (de)
JP (1) JP4733633B2 (de)
KR (1) KR100746179B1 (de)
CN (1) CN100576503C (de)
AT (1) ATE520149T1 (de)
TW (1) TWI269371B (de)
WO (1) WO2004112126A1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2855910B1 (fr) * 2003-06-06 2005-07-15 Commissariat Energie Atomique Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
WO2006101225A1 (ja) * 2005-03-22 2006-09-28 Sumitomo Chemical Company, Limited 自立基板、その製造方法及び半導体発光素子
CN101378008B (zh) * 2008-09-19 2010-06-02 苏州纳维科技有限公司 分离外延层与衬底的方法
FR2936903B1 (fr) * 2008-10-07 2011-01-14 Soitec Silicon On Insulator Relaxation d'une couche de materiau contraint avec application d'un raidisseur
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
US8541315B2 (en) * 2011-09-19 2013-09-24 International Business Machines Corporation High throughput epitaxial lift off for flexible electronics
CN102560676B (zh) * 2012-01-18 2014-08-06 山东大学 一种使用减薄键合结构进行GaN单晶生长的方法
JP2013247362A (ja) * 2012-05-29 2013-12-09 Samsung Corning Precision Materials Co Ltd 半導体素子用薄膜貼り合わせ基板の製造方法
JP2014192307A (ja) * 2013-03-27 2014-10-06 Disco Abrasive Syst Ltd サファイア基板の平坦加工方法
KR101485908B1 (ko) * 2013-05-16 2015-01-26 전북대학교산학협력단 고온 에피층을 이종 기판에 성장하는 구조 및 그 제조 방법
WO2015034118A1 (ko) * 2013-09-09 2015-03-12 Yoo Bong Young 실리콘 기판의 표면 박리 방법
JP6539959B2 (ja) * 2014-08-28 2019-07-10 株式会社Sumco エピタキシャルシリコンウェーハおよびその製造方法、ならびに、固体撮像素子の製造方法
CN108369894B (zh) 2015-12-04 2019-10-15 应用材料公司 用于清洁ingaas(或iii-v族)基板的方法和解决方案
CN105609408B (zh) * 2015-12-23 2018-11-16 上海华虹宏力半导体制造有限公司 半导体器件的形成方法
KR101852767B1 (ko) * 2016-05-25 2018-04-27 전북대학교산학협력단 템플레이트 에피 기판 및 이의 제조방법
CN107910402B (zh) * 2017-06-28 2020-07-17 超晶科技（北京）有限公司 一种铟镓砷红外探测器材料制备方法
RU2657674C1 (ru) * 2017-08-14 2018-06-14 Федеральное государственное бюджетное учреждение науки Институт общей и неорганической химии им. Н.С. Курнакова Российской академии наук (ИОНХ РАН) Способ получения гетероструктуры Mg(Fe1-xGax)2O4/Si со стабильной межфазной границей
KR102234101B1 (ko) 2018-09-21 2021-04-01 고려대학교 산학협력단 박막성장구조, 박막성장방법 및 박막열처리방법
FR3108774B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
CN112635323B (zh) * 2020-12-15 2021-12-28 中国科学院上海微系统与信息技术研究所 一种SiC基异质集成氮化镓薄膜与HEMT器件的制备方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948629A (en) 1989-02-10 1990-08-14 International Business Machines Corporation Deposition of diamond films
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5679152A (en) * 1994-01-27 1997-10-21 Advanced Technology Materials, Inc. Method of making a single crystals Ga*N article
US6958093B2 (en) * 1994-01-27 2005-10-25 Cree, Inc. Free-standing (Al, Ga, In)N and parting method for forming same
US6440823B1 (en) * 1994-01-27 2002-08-27 Advanced Technology Materials, Inc. Low defect density (Ga, Al, In)N and HVPE process for making same
FR2738671B1 (fr) 1995-09-13 1997-10-10 Commissariat Energie Atomique Procede de fabrication de films minces a materiau semiconducteur
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
JP2002510275A (ja) 1997-07-03 2002-04-02 シービーエル テクノロジーズ エピタキシャル層中の欠陥の除去
DE19803013B4 (de) * 1998-01-27 2005-02-03 Robert Bosch Gmbh Verfahren zum Ablösen einer Epitaxieschicht oder eines Schichtsystems und nachfolgendem Aufbringen auf einen alternativen Träger
FR2774511B1 (fr) 1998-01-30 2002-10-11 Commissariat Energie Atomique Substrat compliant en particulier pour un depot par hetero-epitaxie
US6120597A (en) * 1998-02-17 2000-09-19 The Trustees Of Columbia University In The City Of New York Crystal ion-slicing of single-crystal films
US6540827B1 (en) * 1998-02-17 2003-04-01 Trustees Of Columbia University In The City Of New York Slicing of single-crystal films using ion implantation
US6051849A (en) 1998-02-27 2000-04-18 North Carolina State University Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
US6086673A (en) * 1998-04-02 2000-07-11 Massachusetts Institute Of Technology Process for producing high-quality III-V nitride substrates
TW428331B (en) 1998-05-28 2001-04-01 Sumitomo Electric Industries Gallium nitride single crystal substrate and method of producing the same
US6113685A (en) 1998-09-14 2000-09-05 Hewlett-Packard Company Method for relieving stress in GaN devices
JP3525061B2 (ja) 1998-09-25 2004-05-10 株式会社東芝 半導体発光素子の製造方法
US6280523B1 (en) * 1999-02-05 2001-08-28 Lumileds Lighting, U.S., Llc Thickness tailoring of wafer bonded AlxGayInzN structures by laser melting
US6478871B1 (en) 1999-10-01 2002-11-12 Cornell Research Foundation, Inc. Single step process for epitaxial lateral overgrowth of nitride based materials
FR2810159B1 (fr) 2000-06-09 2005-04-08 Centre Nat Rech Scient Couche epaisse de nitrure de gallium ou de nitrure mixte de gallium et d'un autre metal, procede de preparation, et dispositif electronique ou optoelectronique comprenant une telle couche
JP4127463B2 (ja) * 2001-02-14 2008-07-30 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体の結晶成長方法及びｉｉｉ族窒化物系化合物半導体発光素子の製造方法
JP3598075B2 (ja) * 2001-05-11 2004-12-08 松下電器産業株式会社 窒化物半導体基板の製造方法
JP2003095798A (ja) * 2001-09-27 2003-04-03 Hoya Corp 単結晶基板の製造方法
GB0127263D0 (en) * 2001-11-13 2002-01-02 Diamanx Products Ltd Layered structures
KR20030052061A (ko) * 2001-12-20 2003-06-26 엘지전자 주식회사 질화갈륨 기판 제조 장치 및 방법

Also Published As

Publication number Publication date
WO2004112126A1 (en) 2004-12-23
EP1484794A1 (de) 2004-12-08
US20040255846A1 (en) 2004-12-23
KR100746179B1 (ko) 2007-08-03
TW200501239A (en) 2005-01-01
EP1631986B1 (de) 2011-08-10
JP2007524222A (ja) 2007-08-23
KR20060055462A (ko) 2006-05-23
EP1631986A1 (de) 2006-03-08
CN1802739A (zh) 2006-07-12
CN100576503C (zh) 2009-12-30
TWI269371B (en) 2006-12-21
JP4733633B2 (ja) 2011-07-27
US7226509B2 (en) 2007-06-05

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