ATE266258T1 - Verfahren zur herstellung eines halbleitergegenstands - Google Patents

Verfahren zur herstellung eines halbleitergegenstands

Info

Publication number
ATE266258T1
ATE266258T1 AT97309196T AT97309196T ATE266258T1 AT E266258 T1 ATE266258 T1 AT E266258T1 AT 97309196 T AT97309196 T AT 97309196T AT 97309196 T AT97309196 T AT 97309196T AT E266258 T1 ATE266258 T1 AT E266258T1
Authority
AT
Austria
Prior art keywords
substrate
porous silicon
silicon layer
image
multilayer structure
Prior art date
Application number
AT97309196T
Other languages
English (en)
Inventor
Kiyofumi Sakaguchi
Takao Yonehara
Tadashi Atoji
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE266258T1 publication Critical patent/ATE266258T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT97309196T 1996-11-15 1997-11-14 Verfahren zur herstellung eines halbleitergegenstands ATE266258T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30453996 1996-11-15

Publications (1)

Publication Number Publication Date
ATE266258T1 true ATE266258T1 (de) 2004-05-15

Family

ID=17934226

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97309196T ATE266258T1 (de) 1996-11-15 1997-11-14 Verfahren zur herstellung eines halbleitergegenstands

Country Status (10)

Country Link
EP (1) EP0843346B1 (de)
KR (1) KR100279756B1 (de)
CN (1) CN1104036C (de)
AT (1) ATE266258T1 (de)
AU (1) AU745315B2 (de)
CA (1) CA2220600C (de)
DE (1) DE69728950T2 (de)
MY (1) MY114469A (de)
SG (1) SG54593A1 (de)
TW (1) TW372366B (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW376585B (en) * 1997-03-26 1999-12-11 Canon Kk Semiconductor substrate and process for producing same
SG71094A1 (en) 1997-03-26 2000-03-21 Canon Kk Thin film formation using laser beam heating to separate layers
JP3492142B2 (ja) * 1997-03-27 2004-02-03 キヤノン株式会社 半導体基材の製造方法
TW522488B (en) 1998-07-27 2003-03-01 Canon Kk Sample processing apparatus and method
JP2000349264A (ja) 1998-12-04 2000-12-15 Canon Inc 半導体ウエハの製造方法、使用方法および利用方法
US6468923B1 (en) * 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
DE19940512A1 (de) * 1999-08-26 2001-03-22 Bosch Gmbh Robert Verfahren zur Verkappung eines Bauelementes mit einer Kavernenstruktur und Verfahren zur Herstellung der Kavernenstruktur
CN1119830C (zh) * 2000-04-27 2003-08-27 中国科学院上海冶金研究所 一种器件转移方法
US6420243B1 (en) * 2000-12-04 2002-07-16 Motorola, Inc. Method for producing SOI wafers by delamination
KR20040007852A (ko) * 2002-07-11 2004-01-28 (주)두진리사이클 백업보드의 금속막 박리방법 및 이를 수행하는 장치
EP1482548B1 (de) * 2003-05-26 2016-04-13 Soitec Verfahren zur Herstellung von Halbleiterscheiben
JP4348454B2 (ja) * 2007-11-08 2009-10-21 三菱重工業株式会社 デバイスおよびデバイス製造方法
TW201133945A (en) * 2010-01-12 2011-10-01 jian-min Song Diamond LED devices and associated methods
CN101789466B (zh) * 2010-02-10 2011-12-07 上海理工大学 太阳能电池制作方法
FR2984007B1 (fr) 2011-12-13 2015-05-08 Soitec Silicon On Insulator Procede de stabilisation d'une interface de collage situee au sein d'une structure comprenant une couche d'oxyde enterree et structure obtenue
FR2984597B1 (fr) * 2011-12-20 2016-07-29 Commissariat Energie Atomique Fabrication d’une structure souple par transfert de couches
WO2013126927A2 (en) * 2012-02-26 2013-08-29 Solexel, Inc. Systems and methods for laser splitting and device layer transfer
CN106992140A (zh) * 2016-01-20 2017-07-28 沈阳硅基科技有限公司 一种采用激光裂片技术制备soi硅片的方法
US20180068886A1 (en) * 2016-09-02 2018-03-08 Qualcomm Incorporated Porous semiconductor layer transfer for an integrated circuit structure
JP6834932B2 (ja) * 2017-12-19 2021-02-24 株式会社Sumco 貼り合わせウェーハ用の支持基板の製造方法および貼り合わせウェーハの製造方法
FR3079532B1 (fr) 2018-03-28 2022-03-25 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain
CN109904065B (zh) * 2019-02-21 2021-05-11 中国科学院上海微系统与信息技术研究所 异质结构的制备方法
GB202213149D0 (en) * 2022-09-08 2022-10-26 Poro Tech Ltd Method of separating a semiconductor device from a substrate
CN117690943B (zh) * 2024-01-31 2024-06-04 合肥晶合集成电路股份有限公司 一种图像传感器的制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH032889A (ja) * 1989-05-31 1991-01-09 Seikosha Co Ltd 表示装置
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法

Also Published As

Publication number Publication date
KR19980042472A (ko) 1998-08-17
AU4517497A (en) 1998-05-21
CN1191383A (zh) 1998-08-26
DE69728950T2 (de) 2005-03-31
CA2220600C (en) 2002-02-12
AU745315B2 (en) 2002-03-21
EP0843346A3 (de) 1998-07-08
CA2220600A1 (en) 1998-05-15
SG54593A1 (en) 1998-11-16
DE69728950D1 (de) 2004-06-09
EP0843346B1 (de) 2004-05-06
TW372366B (en) 1999-10-21
KR100279756B1 (ko) 2001-03-02
MY114469A (en) 2002-10-31
CN1104036C (zh) 2003-03-26
EP0843346A2 (de) 1998-05-20

Similar Documents

Publication Publication Date Title
ATE266258T1 (de) Verfahren zur herstellung eines halbleitergegenstands
ATE263429T1 (de) Verfahren zur herstellung eines halbleitergegenstands
ATE212476T1 (de) Verfahren zur übertragung einer halbleiterschicht mittels silizium-auf-isolator (soi) technologie
ATE259098T1 (de) Verfahren zur herstellung eines soi-substrats
DE69826053D1 (de) Halbleitersubstrat und Verfahren zu dessen Herstellung
DE69728022D1 (de) Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht
ATE166747T1 (de) Verfahren zur herstellung eines halbleitersubstrates
EP0793263A3 (de) Verfahren zur Herstellung von Halbleitersubstraten
DE69930583D1 (de) Verbundbauteil, Verfahren zu seiner Trennung, und Herstellungsverfahren eines Halbleitersubstrates unter Verwendung desselben
DE69231348D1 (de) Verfahren zur Herstellung eines Halbleiterkörpers
ATE242547T1 (de) Verfahren zur herstellung eines halbleitersubstrats
DE69001411D1 (de) Verfahren zur herstellung eines substrats fuer halbleiteranordnungen.
CA2233115A1 (en) Semiconductor substrate and method of manufacturing the same
DE502004003085D1 (de) Hochtemperatur-schichtsystem zur wärmeableitung und verfahren zu dessen herstellung
ATE265743T1 (de) Verfahren zur herstellung einer schichtstruktur mit einer silicid-schicht
DE69942582D1 (de) Zusammengesetzter zeolithfilm und verfahren zur herstellung desselben
DE69825928D1 (de) Verfahren und Herstellung einer dünnen Schicht
DE69124750D1 (de) Verfahren zur Herstellung eines Silizium Wafer mit einer Chip-Trennstruktur und Einkristallschichtabschnitten
ATE215737T1 (de) Verfahren zur herstellung von photovoltaischen modulen aus kristallinem silizium
EP0993029A3 (de) Verfahren zur Herstellung kristalliner Halbleiterschichten
EP0393551A3 (de) Verfahren zur Herstellung von gleichmässigen dünnen Schichten
ATE549744T1 (de) Verfahren zur herstellung einer halbleiterschicht auf ein substrat
TH29894A (th) วิธีการของการผลิตชิ้นวัตถุกึ่งตัวนำ
DE50015129D1 (de) Verfahren zur herstellung eines elements mit porosidiertem material

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties