ATE505816T1 - Verfahren zur herstellung eines indium-gallium- aluminium-nitrid-dünnfilms auf einem siliziumsubstrat - Google Patents

Verfahren zur herstellung eines indium-gallium- aluminium-nitrid-dünnfilms auf einem siliziumsubstrat

Info

Publication number
ATE505816T1
ATE505816T1 AT06791169T AT06791169T ATE505816T1 AT E505816 T1 ATE505816 T1 AT E505816T1 AT 06791169 T AT06791169 T AT 06791169T AT 06791169 T AT06791169 T AT 06791169T AT E505816 T1 ATE505816 T1 AT E505816T1
Authority
AT
Austria
Prior art keywords
layer
indium gallium
forming
aluminium nitride
silicon substrate
Prior art date
Application number
AT06791169T
Other languages
English (en)
Inventor
Fengyi Jiang
Li Wang
Wenqing Fang
Original Assignee
Lattice Power Jiangxi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Power Jiangxi Corp filed Critical Lattice Power Jiangxi Corp
Application granted granted Critical
Publication of ATE505816T1 publication Critical patent/ATE505816T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02642—Mask materials other than SiO2 or SiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
AT06791169T 2005-09-30 2006-09-29 Verfahren zur herstellung eines indium-gallium- aluminium-nitrid-dünnfilms auf einem siliziumsubstrat ATE505816T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNB200510030319XA CN100338790C (zh) 2005-09-30 2005-09-30 在硅衬底上制备铟镓铝氮薄膜的方法
PCT/CN2006/002583 WO2007036163A1 (fr) 2005-09-30 2006-09-29 Procede de fabrication d'un film mince en nitrure d'aluminium gallium indium sur un substrat de silicium

Publications (1)

Publication Number Publication Date
ATE505816T1 true ATE505816T1 (de) 2011-04-15

Family

ID=36751608

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06791169T ATE505816T1 (de) 2005-09-30 2006-09-29 Verfahren zur herstellung eines indium-gallium- aluminium-nitrid-dünnfilms auf einem siliziumsubstrat

Country Status (8)

Country Link
US (1) US7615420B2 (de)
EP (1) EP1930957B1 (de)
JP (1) JP2009510729A (de)
KR (1) KR101166954B1 (de)
CN (1) CN100338790C (de)
AT (1) ATE505816T1 (de)
DE (1) DE602006021326D1 (de)
WO (1) WO2007036163A1 (de)

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ATE555494T1 (de) 2009-02-19 2012-05-15 S O I Tec Silicon Relaxation und übertragung von verspannten materialschichten
CN101702418B (zh) * 2009-10-23 2011-02-16 山东华光光电子有限公司 降低位错缺陷的GaN基LED芯片外延生长方法
KR101762177B1 (ko) * 2010-12-17 2017-07-27 삼성전자 주식회사 반도체 소자 및 반도체 소자 제조 방법
US8853668B2 (en) 2011-09-29 2014-10-07 Kabushiki Kaisha Toshiba Light emitting regions for use with light emitting devices
US8664679B2 (en) 2011-09-29 2014-03-04 Toshiba Techno Center Inc. Light emitting devices having light coupling layers with recessed electrodes
US9012921B2 (en) 2011-09-29 2015-04-21 Kabushiki Kaisha Toshiba Light emitting devices having light coupling layers
US8698163B2 (en) 2011-09-29 2014-04-15 Toshiba Techno Center Inc. P-type doping layers for use with light emitting devices
US20130082274A1 (en) 2011-09-29 2013-04-04 Bridgelux, Inc. Light emitting devices having dislocation density maintaining buffer layers
US9178114B2 (en) 2011-09-29 2015-11-03 Manutius Ip, Inc. P-type doping layers for use with light emitting devices
TWI550921B (zh) * 2014-07-17 2016-09-21 嘉晶電子股份有限公司 氮化物半導體結構
JP6783990B2 (ja) * 2017-09-07 2020-11-11 豊田合成株式会社 Ｉｉｉ族窒化物半導体素子の製造方法および基板の製造方法
WO2020047825A1 (en) * 2018-09-07 2020-03-12 Enkris Semiconductor, Inc. Semiconductor structure and manufacturing method thereof
CN113192820B (zh) * 2021-03-12 2023-04-11 南昌大学 一种硅衬底氮化铝薄膜的制备方法
CN116364825A (zh) * 2023-06-01 2023-06-30 江西兆驰半导体有限公司 复合缓冲层及其制备方法、外延片及发光二极管
CN116978991B (zh) * 2023-09-22 2023-12-12 江西兆驰半导体有限公司 发光二极管外延片及其制备方法、led

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JPH01135397A (ja) * 1987-11-18 1989-05-29 Matsushita Electric Ind Co Ltd スチームアイロン
JPH01135396A (ja) * 1987-11-20 1989-05-29 Sanyo Electric Co Ltd 衣類用乾燥機
US5152805A (en) * 1989-12-29 1992-10-06 Gte Laboratories Incorporated M-I-M' device and fabrication method
JP3454037B2 (ja) * 1996-09-27 2003-10-06 日立電線株式会社 ＧａＮ系素子用基板及びその製造方法及びＧａＮ系素子
EP0874405A3 (de) * 1997-03-25 2004-09-15 Mitsubishi Cable Industries, Ltd. Element auf Basis von GaN mit niedriger Versetzungsdichte, seine Verwendung und Herstellungsverfahren
US20050018752A1 (en) * 1997-10-03 2005-01-27 Anglin Richard L. Chirping digital wireless system
JP3550070B2 (ja) * 1999-03-23 2004-08-04 三菱電線工業株式会社 ＧａＮ系化合物半導体結晶、その成長方法及び半導体基材
JP3760663B2 (ja) * 1999-03-31 2006-03-29 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体素子の製造方法
JP2001007449A (ja) * 1999-06-25 2001-01-12 Fuji Electric Co Ltd Ｉｉｉ族窒化物半導体薄膜とその製造方法
JP4665286B2 (ja) * 2000-03-24 2011-04-06 三菱化学株式会社 半導体基材及びその製造方法
JP2002284600A (ja) * 2001-03-26 2002-10-03 Hitachi Cable Ltd 窒化ガリウム結晶基板の製造方法及び窒化ガリウム結晶基板
US6955932B2 (en) * 2003-10-29 2005-10-18 International Business Machines Corporation Single and double-gate pseudo-FET devices for semiconductor materials evaluation
JP4332720B2 (ja) * 2003-11-28 2009-09-16 サンケン電気株式会社 半導体素子形成用板状基体の製造方法
CN100403562C (zh) * 2005-03-15 2008-07-16 金芃 垂直结构的半导体芯片或器件

Also Published As

Publication number Publication date
KR20080072631A (ko) 2008-08-06
KR101166954B1 (ko) 2012-07-19
US20080248633A1 (en) 2008-10-09
EP1930957A1 (de) 2008-06-11
DE602006021326D1 (de) 2011-05-26
CN1770484A (zh) 2006-05-10
JP2009510729A (ja) 2009-03-12
EP1930957B1 (de) 2011-04-13
CN100338790C (zh) 2007-09-19
WO2007036163A1 (fr) 2007-04-05
EP1930957A4 (de) 2009-08-19
US7615420B2 (en) 2009-11-10

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