CN1770484A - 在硅衬底上制备铟镓铝氮薄膜的方法 - Google Patents

在硅衬底上制备铟镓铝氮薄膜的方法 Download PDF

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CN1770484A
CN1770484A CNA200510030319XA CN200510030319A CN1770484A CN 1770484 A CN1770484 A CN 1770484A CN A200510030319X A CNA200510030319X A CN A200510030319XA CN 200510030319 A CN200510030319 A CN 200510030319A CN 1770484 A CN1770484 A CN 1770484A
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magnesium
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江风益
王立
方文卿
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Lattice Power Jiangxi Corp
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Nanchang University
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Abstract

本发明公开了一种在硅衬底上制备铟镓铝氮薄膜的方法，它通过引入金属镁进行在线区域掩膜，即先在硅衬底上形成一层镁掩模层或金属过渡层，然后再形成一层金属过渡层或镁掩模层，最后形成一层铟镓铝氮半导体层；先在硅衬底上形成一层金属过渡层，然后再分别依次向上形成一层第一铟镓铝氮半导体层、镁掩模层和第二铟镓铝氮半导体层。本发明可以减少硅衬底上生长的铟镓铝氮材料的位错密度，提高晶体质量。

Description

在硅衬底上制备铟镓铝氮薄膜的方法
技术领域
本发明涉及半导体材料，尤其是涉及一种在硅衬底上制备铟镓铝氮薄膜的方法。
背景技术：
铟镓铝氮(InxGayAl1-x-yN，0＜＝x＜＝1，0＜＝y＜＝1)是制备短波长发光器件的优选材料体系。近年来已经用铟镓铝氮材料制造出许多新颖的发光器件，如蓝色、绿色、白色发光二极管，紫色半导体激光器等等。同时铟镓铝氮材料也是制备许多高性能电子器件的良好材料。现有技术中，在蓝宝石衬底和碳化硅衬底上制备铟镓铝氮材料的方法已经较为成熟。根据这些公开的技术，已经可以制备出高质量的铟镓铝氮材料。但是，碳化硅衬底非常昂贵，用于生长铟镓铝氮材料将使成本很高。而蓝宝石衬底也比较贵，而且它是绝缘体且加工困难，不能制成具有上下电极的芯片结构，这样就导致器件制造工艺复杂，成本增加。硅是一种最成熟的半导体材料，它不仅价格便宜，而且容易控制其导电类型和电阻率，其加工工艺也很成熟，如果用于生长铟镓铝氮将可以大大节约成本。然而由于硅衬底与铟镓铝氮材料之间的晶格失配和热膨胀系数失配很大，在硅衬底上生长的铟镓铝氮材料一般含有很高的位错密度。铟镓铝氮材料中的位错可以起到非辐射复合中心的作用，因此使用高位错密度的铟镓铝氮材料制造的器件发光效率不高。
发明内容：
本发明的目的在于提供一种在硅衬底上制备铟镓铝氮薄膜的方法，该方法可以有效降低硅衬底上生长的铟镓铝氮材料的位错密度，提高晶体质量。
本发明的目的是这样实现的：
在硅衬底上制备铟镓铝氮薄膜(InxGayAl1-x-yN，0＜＝x＜＝1，0＜＝y＜＝1)的方法之一，包含以下步骤：
(1)、在硅衬底上形成一层镁掩模层；
(2)、在所述的镁掩模层上形成一层金属过渡层，该金属过渡层由铝层、钛层或铝钛合金层形成；
(3)、在所述金属过渡层上形成铟镓铝氮半导体层；
其中所述的镁掩模层只覆盖部分硅衬底表面，覆盖部分占总面积的10％-90％。
在硅衬底上制备铟镓铝氮薄膜(InxGayAl1-x-yN，0＜＝x＜＝1，0＜＝y＜＝1)的方法之二，包含以下步骤：
(1)、在硅衬底上形成一层金属过渡层，该金属过渡层由铝层、钛层或铝钛合金层形成；
(2)、在所述的金属过渡层上形成一层镁掩模层；
(3)、在所述的镁掩模层上形成铟镓铝氮半导体层；
其中所述的镁掩模层只覆盖部分金属过渡层表面，覆盖部分占总面积的10％-90％。
在硅衬底上制备铟镓铝氮薄膜(InxGayAl1-x-yN，0＜＝x＜＝1，0＜＝y＜＝1)的方法之三，包含以下步骤：
(1)、在硅衬底上形成一层金属过渡层，该金属过渡层由铝层、钛层或铝钛合金层形成；
(2)、在所述的金属过渡层上形成第一铟镓铝氮半导体层；
(3)、在所述的铟镓铝氮半导体层上形成一层镁掩模层；
(4)、在所述的镁掩模层上形成第二铟镓铝氮半导体层；
其中所述的镁掩模层只覆盖部分第一铟镓铝氮半导体层表面，覆盖部分占总面积的10％-90％。
所述的第一铟镓铝氮半导体层厚度介于1个单元子层到3微米之间。
本发明的目的是通过使用金属镁进行在线掩膜来实现的。由于在镁掩模层上难以进行铟镓铝氮材料生长，因此它可以用作铟镓铝氮生长的掩膜。在本发明的第一种方案中，在硅衬底上沉积一层镁掩膜层，该掩膜层只覆盖部分衬底表面，为了避免暴露的区域被氮化形成氮化硅，沉积镁层之后再在暴露的衬底表面上沉积一层金属铝，这样衬底表面部分被镁覆盖，其余部分则被铝覆盖。然后进行铟镓铝氮材料生长，此时在铝层上铟镓铝氮开始生长，而镁层上则难以生长。但铟镓铝氮材料生长到一定厚度，并超过掩膜层后，便开始进行横向生长。由于横向生长的铟镓铝氮材料位错密度很低，这样长成的薄膜的总位错密度就被降低。在本发明的第二种方案中，首先在硅衬底上覆盖一层铝过渡层，然后在铝层上用镁进行区域掩膜。这样在暴露的铝层上开始铟镓铝氮材料生长，到一定厚度并超过掩膜层后，开始进行横向生长，最终横向连接形成完整的薄膜向上生长。同样由于横向生长的铟镓铝氮材料位错密度很低，薄膜的总位错密度被降低。在本发明的第三种方案中，首先在硅衬底上覆盖一层铝过渡层，然后生长一层第一铟镓铝氮层，该层中含有大量位错。然后用镁进行在线区域掩膜。掩膜后进行第二铟镓铝氮层生长，这样镁掩膜的区域位错被阻挡而难以向上延伸。暴露的区域可以继续生长铟镓铝氮，到一定厚度并超过掩膜层后，开始进行横向生长，最终重新连接形成完整的薄膜后向上生长。同样，由于横向生长的铟镓铝氮材料位错密度很低，第二铟镓铝氮层的总位错密度被降低。在以上的方案中铝层还可以换成钛层或铝钛合金层。
因此本发明具有可以有效降低硅衬底上生长的铟镓铝氮材料的位错密度、提高晶体质量的优点。
附图说明：
图1是本发明实施例1在硅衬底上生长铟镓铝氮材料的叠层结构剖面示意图。
图2是本发明实施例2在硅衬底上生长铟镓铝氮材料的叠层结构剖面示意图。
图3是本发明实施例3在硅衬底上生长铟镓铝氮材料的叠层结构剖面示意图。
图中1为硅衬底，2为金属过渡层，3为镁掩膜层，4为铟镓铝氮半导体层，5为第一铟镓铝氮半导体层，6为第二铟镓铝氮半导体层。
具体实施方式：
下面用3个实施例对本发明的方法进行进一步的说明。
实施例1：
把一个硅(111)衬底1清洗干净，放入一金属有机化学气相沉积设备的反应室，首先在高温下用氢气对衬底1表面进行5分钟热处理，然后降低温度到720℃下，通入二茂镁沉积0.5个单原子层的金属镁掩膜层3。接着同样在720℃下依次沉积一金属铝薄层和一氮化铝缓冲层即金属过渡层2，最后升高温度到1050℃沉积3微米氮化镓层即铟镓铝氮半导体层4。
实施例2：
把一个硅(111)衬底1清洗干净，放入一金属有机化学气相沉积设备的反应室，首先在高温下用氢气对衬底1表面进行5分钟热处理，然后降低温度到900℃下沉积一金属钛薄层即金属过渡层2。接着在880℃下在钛层上沉积1个单原子层的金属镁掩膜层3。仍保持在880℃，沉积一氮化铝缓冲层，最后升高温度到1030℃沉积3微米氮化镓层即铟镓铝氮半导体层4。
实施例3：
把一个硅(111)衬底1清洗干净，放入一金属有机化学气相沉积设备的反应室，首先在高温下用氢气对衬底1表面进行5分钟热处理，然后降低温度到800℃下沉积一铝钛合金薄层即金属过渡层2。保持800℃在铝层上沉积一氮化铝缓冲层，然后升高温度到1030℃在氮化铝层上沉积0.5微米的第一氮化镓层即第一铟镓铝氮半导体层5。接着在同样温度下在第一氮化镓层上沉积2个单原子层的镁掩膜层3。然后依次再沉积2微米厚的掺硅氮化镓层、5个周期铟镓氮/氮化镓多量子阱和0.1微米厚的掺镁氮化镓层即第二铟镓铝氮半导体层4。

Claims (4)

1、一种在硅衬底上制备铟镓铝氮薄膜的方法，其特征在于：
(1)、在硅衬底上形成一层镁掩模层；
(2)、在所述的镁掩模层上形成一层金属过渡层，该金属过渡层由铝层、钛层或铝钛合金层形成；
(3)、在所述金属过渡层上形成铟镓铝氮半导体层；
其中所述的镁掩模层只覆盖部分硅衬底表面，覆盖部分占总面积的10％-90％。
2、在硅衬底上制备铟镓铝氮薄膜的方法，其特征在于：
(1)、在硅衬底上形成一层金属过渡层，该金属过渡层由铝层、钛层或铝钛合金层形成；
(2)、在所述的金属过渡层上形成一层镁掩模层；
(3)、在所述的镁掩模层上形成铟镓铝氮半导体层；
其中所述的镁掩模层只覆盖部分金属过渡层表面，覆盖部分占总面积的10％-90％。
3、在硅衬底上制备铟镓铝氮薄膜的方法，其特征在于：
(1)、在硅衬底上形成一层金属过渡层，该金属过渡层由铝层、钛层或铝钛合金层形成；
(2)、在所述的金属过渡层上形成第一铟镓铝氮半导体层；
(3)、在所述的铟镓铝氮半导体层上形成一层镁掩模层；
(4)、在所述的镁掩模层上形成第二铟镓铝氮半导体层；
其中所述的镁掩模层只覆盖部分第一铟镓铝氮半导体层表面，覆盖部分占总面积的10％-90％。
4、如权利要求3所述的在硅衬底上制备铟镓铝氮薄膜的方法，其特征在于：所述的第一铟镓铝氮半导体层厚度介于1个单元子层到3微米之间。
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PCT/CN2006/002583 WO2007036163A1 (fr) 2005-09-30 2006-09-29 Procede de fabrication d'un film mince en nitrure d'aluminium gallium indium sur un substrat de silicium
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101702418B (zh) * 2009-10-23 2011-02-16 山东华光光电子有限公司 降低位错缺陷的GaN基LED芯片外延生长方法
CN105280770A (zh) * 2014-07-17 2016-01-27 汉磊半导体晶圆股份有限公司 氮化物半导体结构
WO2020047825A1 (en) * 2018-09-07 2020-03-12 Enkris Semiconductor, Inc. Semiconductor structure and manufacturing method thereof
CN113192820A (zh) * 2021-03-12 2021-07-30 南昌大学 一种硅衬底氮化铝薄膜的制备方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2466626A3 (en) 2009-02-19 2012-07-04 Soitec Relaxation and transfer of strained material layers
KR101762177B1 (ko) * 2010-12-17 2017-07-27 삼성전자 주식회사 반도체 소자 및 반도체 소자 제조 방법
US8698163B2 (en) 2011-09-29 2014-04-15 Toshiba Techno Center Inc. P-type doping layers for use with light emitting devices
US9012921B2 (en) 2011-09-29 2015-04-21 Kabushiki Kaisha Toshiba Light emitting devices having light coupling layers
US8853668B2 (en) 2011-09-29 2014-10-07 Kabushiki Kaisha Toshiba Light emitting regions for use with light emitting devices
US8664679B2 (en) 2011-09-29 2014-03-04 Toshiba Techno Center Inc. Light emitting devices having light coupling layers with recessed electrodes
US20130082274A1 (en) 2011-09-29 2013-04-04 Bridgelux, Inc. Light emitting devices having dislocation density maintaining buffer layers
US9178114B2 (en) 2011-09-29 2015-11-03 Manutius Ip, Inc. P-type doping layers for use with light emitting devices
JP6783990B2 (ja) * 2017-09-07 2020-11-11 豊田合成株式会社 Ｉｉｉ族窒化物半導体素子の製造方法および基板の製造方法
CN116364825A (zh) * 2023-06-01 2023-06-30 江西兆驰半导体有限公司 复合缓冲层及其制备方法、外延片及发光二极管
CN116978991B (zh) * 2023-09-22 2023-12-12 江西兆驰半导体有限公司 发光二极管外延片及其制备方法、led

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135397A (ja) * 1987-11-18 1989-05-29 Matsushita Electric Ind Co Ltd スチームアイロン
JPH01135396A (ja) * 1987-11-20 1989-05-29 Sanyo Electric Co Ltd 衣類用乾燥機
US5152805A (en) * 1989-12-29 1992-10-06 Gte Laboratories Incorporated M-I-M' device and fabrication method
JP3454037B2 (ja) * 1996-09-27 2003-10-06 日立電線株式会社 ＧａＮ系素子用基板及びその製造方法及びＧａＮ系素子
EP0874405A3 (en) * 1997-03-25 2004-09-15 Mitsubishi Cable Industries, Ltd. GaN group crystal base member having low dislocation density, use thereof and manufacturing methods thereof
US20050018752A1 (en) * 1997-10-03 2005-01-27 Anglin Richard L. Chirping digital wireless system
JP3550070B2 (ja) * 1999-03-23 2004-08-04 三菱電線工業株式会社 ＧａＮ系化合物半導体結晶、その成長方法及び半導体基材
JP3760663B2 (ja) * 1999-03-31 2006-03-29 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体素子の製造方法
JP2001007449A (ja) * 1999-06-25 2001-01-12 Fuji Electric Co Ltd Ｉｉｉ族窒化物半導体薄膜とその製造方法
JP4665286B2 (ja) * 2000-03-24 2011-04-06 三菱化学株式会社 半導体基材及びその製造方法
JP2002284600A (ja) * 2001-03-26 2002-10-03 Hitachi Cable Ltd 窒化ガリウム結晶基板の製造方法及び窒化ガリウム結晶基板
US6955932B2 (en) * 2003-10-29 2005-10-18 International Business Machines Corporation Single and double-gate pseudo-FET devices for semiconductor materials evaluation
JP4332720B2 (ja) * 2003-11-28 2009-09-16 サンケン電気株式会社 半導体素子形成用板状基体の製造方法
CN100403562C (zh) * 2005-03-15 2008-07-16 金芃 垂直结构的半导体芯片或器件

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101702418B (zh) * 2009-10-23 2011-02-16 山东华光光电子有限公司 降低位错缺陷的GaN基LED芯片外延生长方法
CN105280770A (zh) * 2014-07-17 2016-01-27 汉磊半导体晶圆股份有限公司 氮化物半导体结构
CN105280770B (zh) * 2014-07-17 2018-06-05 嘉晶电子股份有限公司 氮化物半导体结构
WO2020047825A1 (en) * 2018-09-07 2020-03-12 Enkris Semiconductor, Inc. Semiconductor structure and manufacturing method thereof
CN113169227A (zh) * 2018-09-07 2021-07-23 苏州晶湛半导体有限公司 半导体结构及其制备方法
CN113192820A (zh) * 2021-03-12 2021-07-30 南昌大学 一种硅衬底氮化铝薄膜的制备方法

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