CN1801500A - 在硅衬底上制备高质量发光半导体薄膜的方法 - Google Patents

在硅衬底上制备高质量发光半导体薄膜的方法 Download PDF

Info

Publication number
CN1801500A
CN1801500A CNA2005101105660A CN200510110566A CN1801500A CN 1801500 A CN1801500 A CN 1801500A CN A2005101105660 A CNA2005101105660 A CN A2005101105660A CN 200510110566 A CN200510110566 A CN 200510110566A CN 1801500 A CN1801500 A CN 1801500A
Authority
CN
China
Prior art keywords
thin film
silicon substrate
transition zone
silicon
silver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2005101105660A
Other languages
English (en)
Other versions
CN100388519C (zh
Inventor
江风益
邵碧琳
王立
方文卿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Power Jiangxi Corp
Original Assignee
Nanchang University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanchang University filed Critical Nanchang University
Priority to CNB2005101105660A priority Critical patent/CN100388519C/zh
Publication of CN1801500A publication Critical patent/CN1801500A/zh
Priority to PCT/CN2006/003098 priority patent/WO2007056956A1/en
Priority to KR1020087011458A priority patent/KR20080070656A/ko
Priority to US12/067,690 priority patent/US7902556B2/en
Priority to EP06817841A priority patent/EP1949460A1/en
Priority to JP2008540435A priority patent/JP2009516377A/ja
Application granted granted Critical
Publication of CN100388519C publication Critical patent/CN100388519C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02469Group 12/16 materials
    • H01L21/02472Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02491Conductive materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0083Processes for devices with an active region comprising only II-VI compounds
    • H01L33/0087Processes for devices with an active region comprising only II-VI compounds with a substrate not being a II-VI compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Led Devices (AREA)
  • Semiconductor Lasers (AREA)

Abstract

本发明公开了一种在硅衬底上制备高质量发光半导体薄膜的方法,它首先在硅衬底表面形成一层银过渡层,然后在银过渡层上形成半导体薄膜。所述的半导体薄膜的成分为铟镓铝氮(InxGayAl1-x-yN,0<=x<=1,0<=y<=1)或锌镁镉氧(ZnxMgyCd1-x-yO,0<=x<=1,0<=y<=1)。本发明具有可以保护衬底表面不与生长气氛接触、从而防止在铟镓铝氮材料或锌镁镉氧材料生长前形成无定型氮化硅层、提高薄膜质量的优点。

Description

在硅衬底上制备高质量发光半导体薄膜的方法
技术领域
本发明涉及半导体材料,尤其涉及一种使用金属银过渡层在硅衬底上制备高质量发光半导体薄膜的方法。
背景技术:
经过几十年的发展,硅已经成为应用最广泛、最成熟的半导体材料。基于硅材料的各种半导体器件成为了现代社会发展、科技进步的强大动力。然而由于硅为间接带隙的半导体材料,迄今为止硅在发光器件方面的应用还非常有限。为了把硅和发光器件结合起来,在硅衬底上生长发光半导体薄膜被认为是一种可行的办法。另一方面,现有技术中半导体发光材料一般使用比较昂贵的衬底进行生长,如蓝宝石、砷化镓、磷化镓、碳化硅等。而近年来发展迅速的铟镓铝氮和锌镁镉氧等短波长发光材料则大多使用蓝宝石衬底进行。蓝宝石衬底的另一重大缺点是不导电,这为器件结构设计、加工,以及器件的可靠性带来很多问题。因此寻找便宜、导电、易加工的衬底是当前半导体发光材料,尤其是短波长发光材料研究的重要课题。基于这两方面的需要,在硅衬底上生长化合物发光半导体材料成为一个热点研究问题。然而,由于硅表面容易跟V族和VI族气体反应形成无定型的覆盖层,这样在发光半导体薄膜生长前就形成了一层不利于生长的表面层,而且这些表面覆盖层很难去除,所以严重影响后续材料生长。例如:在铟镓铝氮材料生长前容易形成无定型氮化硅层,锌镁镉氧材料生长前容易形成无定型氧化硅层。为了解决这一问题,现有技术中通过在铟镓铝氮材料或锌镁镉氧材料生长前在硅表面形成一层铝过渡层,可以基本解决这个问题。然而由于铝是一种非常活泼的金属,不太稳定,给制备工艺带来困难,而且可能带来器件可靠性问题。
发明内容:
本发明的目的在于提供一种在硅衬底上制备高质量发光半导体薄膜的方法,该方法可以保护衬底表面不与生长气氛接触,从而防止在铟镓铝氮材料或锌镁镉氧材料生长前形成无定型氮化层或氧化层,提高薄膜质量。
本发明的目的是这样实现的:
在硅衬底上制备高质量发光半导体薄膜的方法,特征是:首先在硅衬底表面形成一层银过渡层,然后在银过渡层上形成半导体薄膜。
所述的半导体薄膜的成份为铟镓铝氮(InxGayAl1-x-yN,0<=x<=1,0<=y<=1)或锌镁镉氧(ZnxMgyCd1-x-y0,0<=x<=1,0<=y<=1)。
所述的银过渡层的厚度大于2埃且小于50埃。
在所述的银过渡层和所述的半导体薄膜之间还可以具有一层或多层由金属铝、钛或铝钛合金形成的金属过渡层。
本发明是在硅(111)衬底上形成一层金属银过渡层,由于银在硅(111)表面具有良好的浸润性,银很容易把硅表面铺满,这样就保护衬底表面不与生长气氛接触而反应生成无定型的覆盖层。并且硅(111)表面形成的银膜一般具有(111)取向,因此该过渡层可以继承硅(111)表面的原子排列。铟镓铝氮和锌镁镉氧材料都具有六方对称的纤锌矿结构,其稳定生长面为(0001)面,要求衬底具有六方对称的晶格排列。因此银过渡层具有(111)表面有利于后续生长得到高的晶体质量。
银过渡层厚度不能太厚也不能太薄,太薄了不能有效的保护硅表面,太厚了不能继承硅表面的原子排列,不能维持长程有序,因此不利于后续发光半导体薄膜生长。银过渡层的厚度范围为2-50,优选为5-20。银过渡层的形成方法可以是气相沉积、真空蒸发、磁控溅射,以及其它常见的镀膜方法。该过渡层可以是预先形成然后放入发光半导体材料生长室中,也可以在发光半导体材料生长室中在线形成。
本发明所述的发光半导体材料是铟镓铝氮材料和锌镁镉氧材料。它们可以是单层材料也可以是叠层材料,还可以在这些材料中掺杂。所述的发光半导体材料可以具有如p-n结、双异质结、量子阱等微结构以制作发光器件。生长铟镓铝氮材料和锌镁镉氧材料的方法,可以采用任何已经公开的生长技术,如化学气相沉积,分子束外延,卤化物气相外延等等。为了获得高的晶体质量,一般还需要采用二步法生长,即先生长一层低温半导体缓冲层,然后再升高温度生长外延层和器件制造所需要的微结构。在发光半导体材料和银过渡层之间还可以插入别的金属过渡层,如铝、钛、镁等。
因此本发明具有可以保护衬底表面不与生长气氛接触、从而防止在铟镓铝氮材料或锌镁镉氧材料生长前形成无定型氮化硅层、提高薄膜质量的优点。
附图说明:
图1是根据本发明实施例1在硅(111)衬底上制备的铟镓铝氮外延材料的剖面结构示意图。图中1是硅衬底,2是银过渡层,3是氮化铝低温缓冲层,4是铟镓铝氮叠层。
图2是根据本发明实施例2在硅(111)衬底上制备的锌镁镉氧外延材料的剖面结构示意图。图中1是硅衬底,2是银过渡层,3是氧化锌低温缓冲层,4是氧化锌外延层,5是铝过渡层。
具体实施方式:
下面用2个实施例对本发明的方法进行进一步的说明。
实施例1:
参考图1。把一个硅(111)衬底1清洗干净,放入电子束蒸发台中蒸镀10的银金属膜即银过渡层2,然后把蒸有银过渡层2的衬底1放入一金属有机化学气相沉积设备的反应室,首先在1050℃用氢气对衬底1表面进行5分钟处理,接着在800℃下生长200的氮化铝低温缓冲层3,然后再升高温度生长铟镓铝氮半导体叠层4。该铟镓铝氮半导体叠层4中依次包含未掺杂氮化镓层、掺硅氮化镓层、铟镓氮/氮化镓多量子阱层、氮化镓掺镁层。
实施例2:
参考图2。把一个硅(111)衬底1清洗干净,放入一金属有机化学气相沉积设备的反应室中,首先在1000℃下用氢气处理衬底5分钟。然后降温到200℃沉积20的银金属膜即银过渡层2,接着在200℃下沉积10的铝过渡层5。同样在200℃下在铝过渡层5上生长300的氧化锌低温缓冲层3,然后再升高温度到700℃生长氧化锌外延层4。

Claims (4)

1、一种在硅衬底上制备高质量发光半导体薄膜的方法,其特征在于:首先在硅衬底表面形成一层银过渡层,然后在银过渡层上形成半导体薄膜。
2、如权利要求1所述的在硅衬底上制备铟镓铝氮薄膜的方法,其特征在于:所述的半导体薄膜的成份为铟镓铝氮(InxGayAl1-x-yN,0<=x<=1,0<=y<=1)或锌镁镉氧(ZnxMgyCd1-x-yO,0<=x<=1,0<=y<=1)。
3、如权利要求1所述的在硅衬底上制备铟镓铝氮薄膜的方法,其特征在于:所述的银过渡层的厚度大于2埃且小于50埃。
4、如权利要求1所述的在硅衬底上制备铟镓铝氮薄膜的方法,其特征在于:在所述的银过渡层和所述的半导体薄膜之间还可以具有一层或多层由金属铝、钛或铝钛合金形成的金属过渡层。
CNB2005101105660A 2005-11-17 2005-11-17 在硅衬底上制备高质量发光半导体薄膜的方法 Expired - Fee Related CN100388519C (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CNB2005101105660A CN100388519C (zh) 2005-11-17 2005-11-17 在硅衬底上制备高质量发光半导体薄膜的方法
PCT/CN2006/003098 WO2007056956A1 (en) 2005-11-17 2006-11-17 Method for fabricating high-quality semiconductor light-emitting devices on silicon substrates
KR1020087011458A KR20080070656A (ko) 2005-11-17 2006-11-17 실리콘 기판상에 고품질 반도체 발광 장치를 제조하는 방법
US12/067,690 US7902556B2 (en) 2005-11-17 2006-11-17 Method for fabricating high-quality semiconductor light-emitting devices on silicon substrates
EP06817841A EP1949460A1 (en) 2005-11-17 2006-11-17 Method for fabricating high-quality semiconductor light-emitting devices on silicon substrates
JP2008540435A JP2009516377A (ja) 2005-11-17 2006-11-17 シリコン基板上に高品質の半導体発光デバイスを製造するための方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005101105660A CN100388519C (zh) 2005-11-17 2005-11-17 在硅衬底上制备高质量发光半导体薄膜的方法

Publications (2)

Publication Number Publication Date
CN1801500A true CN1801500A (zh) 2006-07-12
CN100388519C CN100388519C (zh) 2008-05-14

Family

ID=36811354

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005101105660A Expired - Fee Related CN100388519C (zh) 2005-11-17 2005-11-17 在硅衬底上制备高质量发光半导体薄膜的方法

Country Status (6)

Country Link
US (1) US7902556B2 (zh)
EP (1) EP1949460A1 (zh)
JP (1) JP2009516377A (zh)
KR (1) KR20080070656A (zh)
CN (1) CN100388519C (zh)
WO (1) WO2007056956A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108736317A (zh) * 2018-05-15 2018-11-02 深圳市光脉电子有限公司 一种发光二极管外延结构及其矩阵式激光器器件

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8803189B2 (en) * 2008-08-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. III-V compound semiconductor epitaxy using lateral overgrowth
US8377796B2 (en) 2008-08-11 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. III-V compound semiconductor epitaxy from a non-III-V substrate
US20110079766A1 (en) * 2009-10-01 2011-04-07 Isaac Harshman Wildeson Process for fabricating iii-nitride based nanopyramid leds directly on a metalized silicon substrate
EP2942804B1 (en) * 2014-05-08 2017-07-12 Flosfia Inc. Crystalline multilayer structure and semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625202A (en) * 1995-06-08 1997-04-29 University Of Central Florida Modified wurtzite structure oxide compounds as substrates for III-V nitride compound semiconductor epitaxial thin film growth
US6649287B2 (en) * 2000-12-14 2003-11-18 Nitronex Corporation Gallium nitride materials and methods
US20040104395A1 (en) * 2002-11-28 2004-06-03 Shin-Etsu Handotai Co., Ltd. Light-emitting device, method of fabricating the same, and OHMIC electrode structure for semiconductor device
JP2004207508A (ja) * 2002-12-25 2004-07-22 Shin Etsu Handotai Co Ltd 発光素子及びその製造方法
JP4505794B2 (ja) * 2004-03-10 2010-07-21 信越半導体株式会社 発光素子の製造方法
CN100487927C (zh) * 2004-10-26 2009-05-13 金芃 导电和绝缘复合氮化镓基生长衬底及其生产技术和工艺
CN1688030A (zh) * 2005-03-28 2005-10-26 金芃 生长于硅衬底上的垂直结构的半导体芯片或器件
JP2007042682A (ja) * 2005-07-29 2007-02-15 Sanken Electric Co Ltd 半導体発光素子と保護素子との複合半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108736317A (zh) * 2018-05-15 2018-11-02 深圳市光脉电子有限公司 一种发光二极管外延结构及其矩阵式激光器器件

Also Published As

Publication number Publication date
US20080210951A1 (en) 2008-09-04
KR20080070656A (ko) 2008-07-30
US7902556B2 (en) 2011-03-08
EP1949460A1 (en) 2008-07-30
JP2009516377A (ja) 2009-04-16
CN100388519C (zh) 2008-05-14
WO2007056956A1 (en) 2007-05-24

Similar Documents

Publication Publication Date Title
CN100338790C (zh) 在硅衬底上制备铟镓铝氮薄膜的方法
Sands Stability and epitaxy of NiAl and related intermetallic films on III‐V compound semiconductors
EP2543507B1 (en) Laminate, method for producing same, and functional element using same
US7842539B2 (en) Zinc oxide semiconductor and method of manufacturing the same
CN106282917B (zh) 氮化镓基发光二极管及制备方法
CN100388519C (zh) 在硅衬底上制备高质量发光半导体薄膜的方法
WO2020215444A1 (zh) 氧化镓半导体及其制备方法
CN112687526B (zh) 氮化物半导体材料的制备方法及其退火处理方法
KR20050081207A (ko) 터널 정션 배리어층을 사용한 단결정 질화물계 반도체 성장및 이를 이용한 고품위 질화물계 발광소자 제작
CN105977135B (zh) 基于二硫化锡和磁控溅射氮化铝的氮化镓生长方法
KR100750932B1 (ko) 기판 분해 방지막을 사용한 단결정 질화물계 반도체 성장및 이를 이용한 고품위 질화물계 발광소자 제작
US20030019668A1 (en) Particle beam biaxial orientation of a substrate for epitaxial crystal growth
US20210359146A1 (en) Highly-textured thin films
CN100372138C (zh) 在硅衬底上制备铟镓铝氮材料的方法
EP4414170A1 (en) Laminate and method for manufacturing same
CN1512602A (zh) 制作高温超导器件的表面改性方法
CN102326228A (zh) 第ⅲ族氮化物半导体生长基板、第ⅲ族氮化物半导体外延基板、第ⅲ族氮化物半导体元件、第ⅲ族氮化物半导体自立基板及它们的制造方法
CN112820635B (zh) 半导体结构、自支撑氮化镓层及其制备方法
Fujimoto et al. Lattice-matched growth of high-Sn-content (x∼ 0.1) Si1− x Sn x layers on Si1− y Ge y buffers using molecular beam epitaxy
CN111584344A (zh) 一种GeSn和SiGeSn合金材料及其外延方法
CN1275336C (zh) 硅衬底上生长ii-vi族材料薄膜的方法
US20240203731A1 (en) Method of manufacturing an electronic device
Susanto et al. Characterization on Surface Morphology of GaN Layer Deposited on 2D MoS2 Developed by CVD System
JP3358072B2 (ja) 窒化ガリウム系半導体発光素子
Zhao et al. Development of preparation of the functional thin films by pulsed laser deposition

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20060818

Address after: No. 235, Nanjing East Road, Jiangxi, Nanchang

Applicant after: Lattice Power (JiangXi) Corp.

Address before: Institute of materials science and engineering, Nanchang University, 235 East Nanjing Road, Nanchang, Jiangxi

Applicant before: Nanchang University

C14 Grant of patent or utility model
GR01 Patent grant
PE01 Entry into force of the registration of the contract for pledge of patent right

Effective date of registration: 20080625

Pledge (preservation): Pledge

PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20091217

Pledge (preservation): Pledge registration

PE01 Entry into force of the registration of the contract for pledge of patent right

Effective date of registration: 20091217

Pledge (preservation): Pledge

PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20110316

Granted publication date: 20080514

Pledgee: Agricultural Bank of China, Limited by Share Ltd, Nanchang hi tech sub branch

Pledgor: Lattice Power (Jiangxi) Co., Ltd.

Registration number: 2009360000667

PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Method for preparing high quality light-emitting semiconductor thin film on silicon substrate

Effective date of registration: 20110316

Granted publication date: 20080514

Pledgee: Agricultural Bank of China, Limited by Share Ltd, Nanchang hi tech sub branch

Pledgor: Lattice Power (Jiangxi) Co., Ltd.

Registration number: 2011990000081

PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20131010

Granted publication date: 20080514

Pledgee: Agricultural Bank of China, Limited by Share Ltd, Nanchang hi tech sub branch

Pledgor: Lattice Power (Jiangxi) Co., Ltd.

Registration number: 2011990000081

PLDC Enforcement, change and cancellation of contracts on pledge of patent right or utility model
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Method for preparing high quality light-emitting semiconductor thin film on silicon substrate

Effective date of registration: 20150320

Granted publication date: 20080514

Pledgee: Export Import Bank of China

Pledgor: Lattice Power (Jiangxi) Co., Ltd.

Registration number: 2015990000219

PLDC Enforcement, change and cancellation of contracts on pledge of patent right or utility model
PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20160829

Granted publication date: 20080514

Pledgee: Export Import Bank of China

Pledgor: Lattice Power (Jiangxi) Co., Ltd.

Registration number: 2015990000219

PLDC Enforcement, change and cancellation of contracts on pledge of patent right or utility model
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080514

Termination date: 20181117