DE60333712D1 - Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer - Google Patents
Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-WaferInfo
- Publication number
- DE60333712D1 DE60333712D1 DE60333712T DE60333712T DE60333712D1 DE 60333712 D1 DE60333712 D1 DE 60333712D1 DE 60333712 T DE60333712 T DE 60333712T DE 60333712 T DE60333712 T DE 60333712T DE 60333712 D1 DE60333712 D1 DE 60333712D1
- Authority
- DE
- Germany
- Prior art keywords
- donor wafer
- image
- thin layer
- substrate
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title abstract 4
- 238000000034 method Methods 0.000 title abstract 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 abstract 2
- 238000003776 cleavage reaction Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 229910052742 iron Inorganic materials 0.000 abstract 1
- 230000003287 optical effect Effects 0.000 abstract 1
- 230000007017 scission Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2258—Diffusion into or out of AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0212405A FR2845523B1 (fr) | 2002-10-07 | 2002-10-07 | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60333712D1 true DE60333712D1 (de) | 2010-09-23 |
Family
ID=32011448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60333712T Expired - Lifetime DE60333712D1 (de) | 2002-10-07 | 2003-10-07 | Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer |
Country Status (6)
Country | Link |
---|---|
US (3) | US7008859B2 (de) |
EP (1) | EP1408545B1 (de) |
JP (1) | JP4854921B2 (de) |
AT (1) | ATE477589T1 (de) |
DE (1) | DE60333712D1 (de) |
FR (1) | FR2845523B1 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6912330B2 (en) * | 2001-05-17 | 2005-06-28 | Sioptical Inc. | Integrated optical/electronic circuits and associated methods of simultaneous generation thereof |
FR2845523B1 (fr) * | 2002-10-07 | 2005-10-28 | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee | |
FR2856192B1 (fr) * | 2003-06-11 | 2005-07-29 | Soitec Silicon On Insulator | Procede de realisation de structure heterogene et structure obtenue par un tel procede |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
EP1571705A3 (de) * | 2004-03-01 | 2006-01-04 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zur Herstellung einer Hableiterstruktur auf einem Substrat |
WO2006082467A1 (en) * | 2005-02-01 | 2006-08-10 | S.O.I.Tec Silicon On Insulator Technologies | Substrate for crystal growing a nitride semiconductor |
US7244630B2 (en) * | 2005-04-05 | 2007-07-17 | Philips Lumileds Lighting Company, Llc | A1InGaP LED having reduced temperature dependence |
FR2890489B1 (fr) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant |
CN1992173B (zh) * | 2005-11-30 | 2010-04-21 | 硅起源股份有限公司 | 用于注入键合衬底以便导电的方法和结构 |
JP5271279B2 (ja) * | 2007-02-08 | 2013-08-21 | ソイテック | 高熱消散基板を製造する方法 |
US20090092159A1 (en) * | 2007-05-28 | 2009-04-09 | Sumitomo Electric Industries, Ltd. | Semiconductor light-emitting device with tunable emission wavelength |
US20090174018A1 (en) * | 2008-01-09 | 2009-07-09 | Micron Technology, Inc. | Construction methods for backside illuminated image sensors |
FR2926674B1 (fr) | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable |
CN101904017A (zh) * | 2008-02-26 | 2010-12-01 | 硅绝缘体技术有限公司 | 制造半导体衬底的方法 |
US20100044827A1 (en) * | 2008-08-22 | 2010-02-25 | Kinik Company | Method for making a substrate structure comprising a film and substrate structure made by same method |
EP2202795A1 (de) * | 2008-12-24 | 2010-06-30 | S.O.I. TEC Silicon | Verfahren zur Herstellung eines Halbleitersubstrats und Halbleitersubstrat |
FR2953328B1 (fr) * | 2009-12-01 | 2012-03-30 | S O I Tec Silicon On Insulator Tech | Heterostructure pour composants electroniques de puissance, composants optoelectroniques ou photovoltaiques |
US8748288B2 (en) | 2010-02-05 | 2014-06-10 | International Business Machines Corporation | Bonded structure with enhanced adhesion strength |
EP2372755B1 (de) * | 2010-03-31 | 2013-03-20 | EV Group E. Thallner GmbH | Verfahren zum permanenten Verbinden zweier Metalloberflächen |
FR2961948B1 (fr) * | 2010-06-23 | 2012-08-03 | Soitec Silicon On Insulator | Procede de traitement d'une piece en materiau compose |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
RU2469433C1 (ru) * | 2011-07-13 | 2012-12-10 | Юрий Георгиевич Шретер | Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты) |
JP6011340B2 (ja) * | 2011-08-05 | 2016-10-19 | 住友電気工業株式会社 | 基板、半導体装置およびこれらの製造方法 |
FR2982071B1 (fr) * | 2011-10-27 | 2014-05-16 | Commissariat Energie Atomique | Procede de lissage d'une surface par traitement thermique |
FR2994766B1 (fr) * | 2012-08-23 | 2014-09-05 | Commissariat Energie Atomique | Procede de transfert d'un film d'inp |
FR3007892B1 (fr) * | 2013-06-27 | 2015-07-31 | Commissariat Energie Atomique | Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive |
CN105374664A (zh) * | 2015-10-23 | 2016-03-02 | 中国科学院上海微系统与信息技术研究所 | 一种InP薄膜复合衬底的制备方法 |
FR3045678B1 (fr) | 2015-12-22 | 2017-12-22 | Soitec Silicon On Insulator | Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche |
EP3417476A1 (de) * | 2016-02-16 | 2018-12-26 | G-Ray Switzerland SA | Strukturen, systeme und verfahren zum transport elektrischer ladungen über gebundene schnittstellen |
CN113223928B (zh) * | 2021-04-16 | 2024-01-12 | 西安电子科技大学 | 一种基于转移键合的氧化镓外延生长方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2596777B1 (fr) * | 1986-04-08 | 1994-01-21 | Etat Francais Cnet | Procede de preparation de semi-isolants 3-5 mono-cristallins par dopage et application des semi-isolants ainsi obtenus |
US4738934A (en) * | 1986-05-16 | 1988-04-19 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making indium phosphide devices |
IL100979A0 (en) | 1991-03-18 | 1992-11-15 | Hughes Aircraft Co | Method for establishing an electrical field at a surface of a semiconductor device |
JP2932787B2 (ja) * | 1991-10-03 | 1999-08-09 | 日立電線株式会社 | 化合物半導体ウェハの製造方法 |
US5227313A (en) * | 1992-07-24 | 1993-07-13 | Eastman Kodak Company | Process for making backside illuminated image sensors |
US5244817A (en) * | 1992-08-03 | 1993-09-14 | Eastman Kodak Company | Method of making backside illuminated image sensors |
US5270221A (en) * | 1992-11-05 | 1993-12-14 | Hughes Aircraft Company | Method of fabricating high quantum efficiency solid state sensors |
JPH08139297A (ja) * | 1994-09-14 | 1996-05-31 | Nippon Telegr & Teleph Corp <Ntt> | Soi基板の製造方法 |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JPH11163363A (ja) * | 1997-11-22 | 1999-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
FR2816445B1 (fr) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
JP4304884B2 (ja) * | 2001-06-06 | 2009-07-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
FR2845523B1 (fr) * | 2002-10-07 | 2005-10-28 | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee | |
US7169226B2 (en) * | 2003-07-01 | 2007-01-30 | International Business Machines Corporation | Defect reduction by oxidation of silicon |
-
2002
- 2002-10-07 FR FR0212405A patent/FR2845523B1/fr not_active Expired - Fee Related
-
2003
- 2003-10-06 US US10/678,127 patent/US7008859B2/en not_active Expired - Lifetime
- 2003-10-07 JP JP2003348741A patent/JP4854921B2/ja not_active Expired - Lifetime
- 2003-10-07 EP EP03292465A patent/EP1408545B1/de not_active Expired - Lifetime
- 2003-10-07 DE DE60333712T patent/DE60333712D1/de not_active Expired - Lifetime
- 2003-10-07 AT AT03292465T patent/ATE477589T1/de not_active IP Right Cessation
-
2005
- 2005-11-16 US US11/274,264 patent/US7535115B2/en active Active
-
2008
- 2008-06-16 US US12/139,609 patent/US7645684B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20040121558A1 (en) | 2004-06-24 |
FR2845523A1 (fr) | 2004-04-09 |
FR2845523B1 (fr) | 2005-10-28 |
JP2004179630A (ja) | 2004-06-24 |
US20080248631A1 (en) | 2008-10-09 |
US7535115B2 (en) | 2009-05-19 |
ATE477589T1 (de) | 2010-08-15 |
JP4854921B2 (ja) | 2012-01-18 |
EP1408545A2 (de) | 2004-04-14 |
EP1408545A3 (de) | 2004-08-04 |
EP1408545B1 (de) | 2010-08-11 |
US7645684B2 (en) | 2010-01-12 |
US20060060922A1 (en) | 2006-03-23 |
US7008859B2 (en) | 2006-03-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R082 | Change of representative |
Ref document number: 1408545 Country of ref document: EP Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, DE |
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R081 | Change of applicant/patentee |
Ref document number: 1408545 Country of ref document: EP Owner name: SOITEC, FR Free format text: FORMER OWNER: COMMISSARIAT A L'ENERGIE ATOMIQ, S.O.I.TEC SILICON ON INSULATOR, , FR Effective date: 20120905 Ref document number: 1408545 Country of ref document: EP Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA), FR Free format text: FORMER OWNER: COMMISSARIAT A L'ENERGIE ATOMIQ, S.O.I.TEC SILICON ON INSULATOR, , FR Effective date: 20120905 |
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R082 | Change of representative |
Ref document number: 1408545 Country of ref document: EP Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, DE Effective date: 20120905 |