ATE524827T1 - Verfahren zum transfer einer schicht gespannten halbleitermaterials - Google Patents
Verfahren zum transfer einer schicht gespannten halbleitermaterialsInfo
- Publication number
- ATE524827T1 ATE524827T1 AT03762846T AT03762846T ATE524827T1 AT E524827 T1 ATE524827 T1 AT E524827T1 AT 03762846 T AT03762846 T AT 03762846T AT 03762846 T AT03762846 T AT 03762846T AT E524827 T1 ATE524827 T1 AT E524827T1
- Authority
- AT
- Austria
- Prior art keywords
- semiconductor material
- layer
- lattice parameter
- transferring
- strained semiconductor
- Prior art date
Links
- 239000000463 material Substances 0.000 title abstract 4
- 238000000034 method Methods 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Drying Of Semiconductors (AREA)
- Led Devices (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0208602A FR2842350B1 (fr) | 2002-07-09 | 2002-07-09 | Procede de transfert d'une couche de materiau semiconducteur contraint |
PCT/IB2003/003341 WO2004006326A1 (en) | 2002-07-09 | 2003-07-09 | Method of transferring of a layer of strained semiconductor material |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE524827T1 true ATE524827T1 (de) | 2011-09-15 |
Family
ID=29763665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03762846T ATE524827T1 (de) | 2002-07-09 | 2003-07-09 | Verfahren zum transfer einer schicht gespannten halbleitermaterials |
Country Status (9)
Country | Link |
---|---|
EP (1) | EP1547146B1 (de) |
JP (3) | JP4545586B2 (de) |
KR (1) | KR100829644B1 (de) |
CN (1) | CN100511636C (de) |
AT (1) | ATE524827T1 (de) |
AU (1) | AU2003247130A1 (de) |
FR (1) | FR2842350B1 (de) |
TW (1) | TWI296836B (de) |
WO (1) | WO2004006326A1 (de) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
FR2867310B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
FR2867307B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
US7282449B2 (en) | 2004-03-05 | 2007-10-16 | S.O.I.Tec Silicon On Insulator Technologies | Thermal treatment of a semiconductor layer |
US7217949B2 (en) * | 2004-07-01 | 2007-05-15 | International Business Machines Corporation | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
FR2881877B1 (fr) * | 2005-02-04 | 2007-08-31 | Soitec Silicon On Insulator | Transistor a effet de champ multi-grille a canal multi-couche |
JP4654710B2 (ja) * | 2005-02-24 | 2011-03-23 | 信越半導体株式会社 | 半導体ウェーハの製造方法 |
KR100714822B1 (ko) * | 2005-07-29 | 2007-05-04 | 한양대학교 산학협력단 | 에스오아이 웨이퍼의 제조 방법 |
FR2892733B1 (fr) | 2005-10-28 | 2008-02-01 | Soitec Silicon On Insulator | Relaxation de couches |
FR2883661B1 (fr) * | 2006-05-04 | 2008-04-25 | Soitec Silicon On Insulator | Transistor a effet de champ multi-grille a canal multi-couche |
KR101495153B1 (ko) * | 2007-06-01 | 2015-02-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 제작 방법 및 반도체장치 |
US8178419B2 (en) | 2008-02-05 | 2012-05-15 | Twin Creeks Technologies, Inc. | Method to texture a lamina surface within a photovoltaic cell |
CN103165512A (zh) * | 2011-12-14 | 2013-06-19 | 中国科学院上海微系统与信息技术研究所 | 一种超薄绝缘体上半导体材料及其制备方法 |
US8841161B2 (en) | 2012-02-05 | 2014-09-23 | GTAT.Corporation | Method for forming flexible solar cells |
US8916954B2 (en) | 2012-02-05 | 2014-12-23 | Gtat Corporation | Multi-layer metal support |
US8785294B2 (en) | 2012-07-26 | 2014-07-22 | Gtat Corporation | Silicon carbide lamina |
WO2014022722A2 (en) * | 2012-08-02 | 2014-02-06 | Gtat Corporation | Epitaxial growth on thin lamina |
US8946054B2 (en) | 2013-04-19 | 2015-02-03 | International Business Machines Corporation | Crack control for substrate separation |
CN108780734A (zh) * | 2016-01-20 | 2018-11-09 | 麻省理工学院 | 载体基板上器件的制造 |
FR3051596B1 (fr) * | 2016-05-17 | 2022-11-18 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
FR3051595B1 (fr) * | 2016-05-17 | 2022-11-18 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
EP3709943A1 (de) * | 2017-11-15 | 2020-09-23 | Smith & Nephew PLC | Integrierte sensorgestützte wundüberwachungs- und/oder therapieverbände und -systeme |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3942672B2 (ja) * | 1996-04-12 | 2007-07-11 | キヤノンアネルバ株式会社 | 基板処理方法および基板処理装置 |
US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
JP4476390B2 (ja) * | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
JP4226175B2 (ja) * | 1999-12-10 | 2009-02-18 | 富士通株式会社 | 半導体装置およびその製造方法 |
KR100429869B1 (ko) * | 2000-01-07 | 2004-05-03 | 삼성전자주식회사 | 매몰 실리콘 저머늄층을 갖는 cmos 집적회로 소자 및기판과 그의 제조방법 |
WO2001054202A1 (en) * | 2000-01-20 | 2001-07-26 | Amberwave Systems Corporation | Strained-silicon metal oxide semiconductor field effect transistors |
AU2001268577A1 (en) * | 2000-06-22 | 2002-01-02 | Massachusetts Institute Of Technology | Etch stop layer system |
WO2002015244A2 (en) * | 2000-08-16 | 2002-02-21 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded expitaxial growth |
US6524935B1 (en) * | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
WO2002071493A2 (en) * | 2001-03-02 | 2002-09-12 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed cmos electronics and high speed analog |
US6603156B2 (en) * | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
-
2002
- 2002-07-09 FR FR0208602A patent/FR2842350B1/fr not_active Expired - Lifetime
-
2003
- 2003-07-09 CN CNB038162113A patent/CN100511636C/zh not_active Expired - Lifetime
- 2003-07-09 AU AU2003247130A patent/AU2003247130A1/en not_active Abandoned
- 2003-07-09 TW TW092118766A patent/TWI296836B/zh not_active IP Right Cessation
- 2003-07-09 EP EP03762846A patent/EP1547146B1/de not_active Expired - Lifetime
- 2003-07-09 KR KR1020057000467A patent/KR100829644B1/ko active IP Right Grant
- 2003-07-09 JP JP2004519124A patent/JP4545586B2/ja not_active Expired - Lifetime
- 2003-07-09 WO PCT/IB2003/003341 patent/WO2004006326A1/en active Application Filing
- 2003-07-09 AT AT03762846T patent/ATE524827T1/de not_active IP Right Cessation
-
2010
- 2010-05-14 JP JP2010112240A patent/JP4602474B2/ja not_active Expired - Lifetime
- 2010-05-14 JP JP2010112251A patent/JP4602475B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2010219546A (ja) | 2010-09-30 |
JP4602474B2 (ja) | 2010-12-22 |
CN100511636C (zh) | 2009-07-08 |
EP1547146A1 (de) | 2005-06-29 |
WO2004006326A1 (en) | 2004-01-15 |
CN1666331A (zh) | 2005-09-07 |
KR100829644B1 (ko) | 2008-05-16 |
AU2003247130A1 (en) | 2004-01-23 |
TWI296836B (en) | 2008-05-11 |
JP2010199617A (ja) | 2010-09-09 |
JP2005532686A (ja) | 2005-10-27 |
EP1547146B1 (de) | 2011-09-14 |
TW200409281A (en) | 2004-06-01 |
KR20050018979A (ko) | 2005-02-28 |
JP4545586B2 (ja) | 2010-09-15 |
FR2842350A1 (fr) | 2004-01-16 |
FR2842350B1 (fr) | 2005-05-13 |
JP4602475B2 (ja) | 2010-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE524827T1 (de) | Verfahren zum transfer einer schicht gespannten halbleitermaterials | |
WO2004006311A3 (en) | Transfer of a thin layer from a wafer comprising a buffer layer | |
TW200608455A (en) | Semiconductor film manufacturing method and substrate manufacturing method | |
SG125932A1 (en) | Method of forming strained silicon on insulator substrate | |
TW200746262A (en) | Method of manufacturing nitride semiconductor substrate and composite material substrate | |
ATE521085T1 (de) | Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur | |
TW200715380A (en) | Process for lateral disjonting of a semiconductor wafer and opto-electronic element | |
WO2002001608A3 (en) | METHOD FOR ACHIEVING IMPROVED EPITAXY QUALITY (SURFACE TEXTURE AND DEFECT DENSITY) ON FREE-STANDING (ALUMINUM, INDIUM, GALLIUM) NITRIDE ((Al,In,Ga)N) SUBSTRATES FOR OPTO-ELECTRONIC AND ELECTRONIC DEVICES | |
DE69820662D1 (de) | Planarisierungsverfahren für halbleitende substrate | |
DE60329576D1 (de) | Nitrid-halbleiterbauelement mit einem trägersubstrat und verfahren zu seiner herstellung | |
TW200624360A (en) | Substrate treatment method, substrate treatment system, and substrate treatment program | |
TW200512801A (en) | Fabrication of semiconductor devices | |
WO2003015143A1 (fr) | Film semi-conducteur en nitrure du groupe iii et son procede de production | |
TW200616014A (en) | Method for manufacturing compound material wafers | |
DE60142035D1 (de) | Verfahren zur herstellung von vias in silizium carbid und dessen bauelementen und schaltkreise | |
TW200721373A (en) | Method for recycling an epitaxied donor wafer | |
WO2006033822A3 (en) | Fabrication of electronic and photonic systems on flexible substrates by layer transfer method | |
WO2008120467A1 (ja) | 半導体装置の製造方法 | |
ATE301332T1 (de) | Verfahren zum selektiven transferieren von halbleiter-chips von einem träger zu einem empfangssubstrat | |
TW200503076A (en) | III-V compound semiconductor crystal and method for production thereof | |
TW200705696A (en) | Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same | |
TW200723365A (en) | Method for producing III-N layers, and III-N layers or III-N substrates, and devices based thereon | |
JP2013080897A (ja) | 複合基板の製造方法 | |
WO2009028314A1 (ja) | 半導体装置の製造方法 | |
TW200746456A (en) | Nitride-based semiconductor device and production method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |