US6603156B2 - Strained silicon on insulator structures - Google Patents

Strained silicon on insulator structures Download PDF

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US6603156B2
US6603156B2 US09/823,855 US82385501A US6603156B2 US 6603156 B2 US6603156 B2 US 6603156B2 US 82385501 A US82385501 A US 82385501A US 6603156 B2 US6603156 B2 US 6603156B2
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silicon
insulating layer
strained
insulator
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Kern Rim
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Soitec Silicon on Insulator Technologies SA
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International Business Machines Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Abstract

A SOI structure and a method for its fabrication, in which a strained silicon layer lies directly on an insulator layer, contrary to the prior requirement for strained-Si layers to lie directly on a strain-inducing (e.g., SiGe) layer. The method generally entails the forming a silicon layer on a strain-inducing layer so as to form a multilayer structure, in which the strain-inducing layer has a different lattice constant than silicon so that the silicon layer is strained as a result of the lattice mismatch with the strain-inducing layer. The multilayer structure is then bonded to a substrate so that an insulating layer is between the strained silicon layer and the substrate, and so that the strained silicon layer directly contacts the insulating layer. The strain-inducing layer is then removed to expose a surface of the strained silicon layer and yield a strained silicon-on-insulator structure that comprises the substrate, the insulating layer on the substrate, and the strained silicon layer on the insulating layer. As a result, the method yields a strained silicon-on-insulator (SSOI) structure in which the strain in the silicon layer is maintained by the SOI structure.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

Not applicable.

BACKGROUND OF THE INVENTION

The present invention generally relates to integrated circuit (IC) structures and processes that include a strained semiconductor layer. More particularly, this invention relates to a strained silicon layer that is directly on an insulator, yielding a strained silicon-on-insulator (SSOI) structure that is useful for IC device fabrication, such as complementary metal-oxide-semiconductor (CMOS) transistors and other metal-oxide-semiconductor field effect transistor (MOSFET) applications.

Strained silicon CMOS essentially refers to CMOS devices fabricated on substrates having a thin strained silicon (strained-Si) layer on a relaxed SiGe layer. Electron and hole mobility in strained-Si layers has been shown to be significantly higher than in bulk silicon layers, and MOSFET's with strained-Si channels have been experimentally demonstrated to have enhanced device performance compared to devices fabricated in conventional (unstrained) silicon substrates. Potential performance improvements include increased device drive current and transconductance, as well as the added ability to scale the operation voltage without sacrificing circuit speed in order to reduce the power consumption.

Strained-Si layers are the result of biaxial tensile stress induced in silicon grown on a substrate formed of a material whose lattice constant is greater than that of silicon. The lattice constant of germanium is about 4.2 percent greater than that of silicon, and the lattice constant of a silicon-germanium alloy is linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy containing fifty atomic percent germanium is about 1.02 times greater than the lattice constant of silicon. Epitaxial growth of silicon on such a SiGe substrate will yield a silicon layer under tensile strain, with the underlying SiGe substrate being essentially unstrained, or “relaxed.” A structure and process that realize the advantages of a strained-Si channel structure for MOSFET applications are taught in commonly-assigned U.S. Pat. No. 6,059,895 to Chu et al., which discloses a technique for forming a CMOS device having a strained-Si channel on a SiGe layer, all on an insulating substrate.

A difficulty in fully realizing the advantages of strained-Si CMOS technology is the presence of the relaxed SiGe layer under the strained-Si layer. The SiGe layer can interact with various processing steps, such as thermal oxidation, salicide formation and annealing, such that it is difficult to maintain material integrity during the CMOS fabrication, and may ultimately limit the device performance enhancements and device yield that can be achieved. Another disadvantage is that the SiGe layer adds to the total thickness of the body region of the MOSFET. This additional thickness is particularly undesirable for silicon-on-insulator (SOI) FET structures, because it frustrates the ability to form a very thin SOI device, whose merits as a MOSFET structure for very short channel lengths are well documented. Therefore, distinct advantages could be realized with a strained-Si structure that does not include the strain-inducing layer, but instead has a strained-Si layer that is directly on another layer, such as an insulator layer to yield a strained SOI structure. However, conventional wisdom has been that the SiGe layer must be present at all times to maintain the strain in the silicon layer, in that exposure to elevated temperatures during subsequent processing would have the effect of removing the strain in an unsupported strained-Si layer.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a SOI structure and a method for its fabrication, in which a strained silicon layer lies directly on an insulator layer. As such, the invention overcomes the disadvantages of the prior art requirement for strained-Si structures on an insulating substrate to include a strain-inducing (e.g., SiGe) layer between the strained-Si layer and the insulator. The method of this invention generally entails forming a silicon layer on a strain-inducing layer so as to form a multilayer structure, in which the strain-inducing layer has a different lattice constant than silicon so that the strain-inducing layer induces strain in the silicon layer as a result of the lattice mismatch. The multilayer structure is then bonded to a substrate so that an insulating layer is between the strained silicon layer and the substrate, and so that the strained silicon layer directly contacts the insulating layer. For this purpose, the insulating layer may be provided on the substrate or on the surface of the strained silicon layer opposite the strain-inducing layer. The strain-inducing layer is then removed to yield a strained silicon-on-insulator (SSOI) structure that comprises the strained silicon layer on the insulating layer, with the insulating layer being between the substrate and strained silicon layer. As a result, the resulting SSOI structure does not include an additional strain-inducing layer. Instead, the present invention is based on the determination that strain already induced in a silicon layer can be substantially maintained by a substrate that does not have a strain-inducing lattice mismatch with silicon. In the SSOI structure, the insulating layer (alone or in combination with the substrate) is in some manner able to physically inhibit relaxation of the strained silicon layer.

According to the invention, the resulting SSOI structure is particularly well suited as a semiconductor substrate for IC devices. For this purpose, source and drain regions are formed in the surface of the strained silicon layer, and the silicon layer defines a channel between the source region and the drain region. As a result of the method by which the SSOI structure is fabricated, the strained-Si channel directly contacts the insulating layer. By eliminating the strain-inducing layer under the strained-Si channel, the present invention enables the advantages of strained-Si CMOS technology to be more fully realized. For example, eliminating the strain-inducing layer (e.g., SiGe) reduces the total thickness of the MOSFET device, and avoids interactions with various processing steps such that material integrity can be maintained during CMOS fabrication.

Other objects and advantages of this invention will be better appreciated from the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 represents alternative techniques for forming a strained-silicon-on-insulator (SSOI) structure in accordance with the present invention.

FIGS. 2 and 3 show two MOSFET applications that utilize the SSOI structure of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 represents processes within the scope of this invention by which a multilayer structure 16 can be formed in which a strained silicon (strained-Si) layer 12 lies directly on an insulator layer 14, such that the structure 16 can be further processed to yield a strained silicon-on-insulator (SSOI) structure 10 suitable for fabrication of MOSFET's and other IC devices such as those represented in FIG. 2. FIG. 1 illustrates four alternative techniques (“Alternatives” (A), (B), (C) and (D)) for the first step of the process represented in FIG. 1. With each of the alternatives shown in FIG. 1, a multilayer structure is bonded to a substrate so that the insulator 14 is between the strained-Si layer 12 and the substrate, and such that the strained-Si layer 12 directly contacts the insulator 14. While four techniques are shown and will be discussed below, it is foreseeable that other techniques could be devised and employed to yield the intermediate multilayer structure 16 of FIG. 1, and such modifications are within the scope of this invention. In addition, while FIGS. 1 and 2 show multilayered structures comprising a limited number of layers, those skilled in the art will appreciate that additional layers of various materials could be added to the structures without substantively altering the invention. Of importance is that each technique shown in FIG. 1 produces a strained-Si layer 12 that is supported by a layer (e.g., 14/24) other than that which originally induced strain in the silicon layer 12. Therefore, additional layers can be included in the structure 16 as long as this fundamental aspect of the invention is met. The four alternatives differ primarily in the materials being bonded, e.g., silicon-to-insulator (Alternative (A)), insulator-to-insulator (Alternative (B)), insulator-to-semiconductor (Alternative (C)), or semiconductor-to-semiconductor (Alternative (D)).

Alternative (A) of FIG. 1 represents the multilayer structure 16 as being fabricated by bonding a pair of structures 18 and 20. The first structure 18 comprises the strained-Si layer 12 on a relaxed SiGe substrate 22. The function of the substrate 22 is to induce the biaxial tensile stresses that create a desired level of strain in the silicon layer 12, and therefore could be formed of another material having a lattice constant that differs from silicon. Because the relationship between the germanium concentration and lattice constant is linear for SiGe alloys, the amount of strain induced in the strained-Si layer 12 can be tailored by the amount of germanium in the SiGe alloy. Germanium has a lattice constant of about 4 percent greater than silicon, which is therefore the upper limit for the lattice mismatch between the strained-Si layer 12 and the SiGe substrate 22. A preferred lattice mismatch is believed to be about 0.2 to about 2 percent, achieved with a SiGe alloy containing about 5 to about 50 atomic percent germanium, though it is foreseeable that lower and higher mismatches could be used. Furthermore, lattice mismatches greater than 4 percent are possible of the substrate 22 is formed of a material other than a SiGe alloy.

The substrate 22 is preferably a single-crystal material, and the strained-Si layer 12 is epitaxially grown on the SiGe substrate 22 in accordance with known techniques in the art. The SiGe substrate 22 can be formed by such known methods as epitaxial growth and Czhochralski growth, though other methods are foreseeable. Because the SiGe substrate 22 has a greater lattice constant than silicon, the strained-Si layer 12 is under biaxial tension, while the underlying SiGe substrate 22 remains substantially unstrained, or “relaxed.” A suitable thickness for the strained-Si layer 12 is up to about 500 angstroms, while a suitable thickness for the SiGe substrate is about 1000 to about 50,000 angstroms.

The second structure 20 of Alternative (A) of FIG. 1 comprises the insulator 14 on a substrate 24 that at least initially serves as a handle wafer for the insulator 14. As will become apparent from the following, it is foreseeable that one or more layers of various materials could be included between the insulator 14 and substrate 24 or on the backside of the substrate 24 (opposite the insulator 14). Suitable materials for the insulator 14 include silicon oxide (silica, SiO2), silicon nitride (SiN), and aluminum oxide (alumina; Al2O3), though other electrical insulating (“high-k”) materials could foreseeably be used, including silicon oxynitride, hafnium oxide (hafnia, HfO2), zirconium oxide (zirconia, ZrO2), and doped aluminum oxide. Thicknesses of up to about one micrometer are believed suitable for the insulator 14. Suitable materials for the substrate 24 are dependent on the role, if any, that the substrate 24 serves in the final SSOI structure 10. As will be discussed in greater detail below, the substrate 24 may subsequently serve as a gate electrode for a MOSFET device, such that preferred materials for the substrate 24 include single-crystal silicon, polysilicon, metals such as tungsten, etc. Other suitable materials for the substrate 24 generally include SOI, SiGe, GaAs and other III-V semiconductors. While the individual thicknesses of the insulator 14 and substrate 24 are not generally critical to the invention, the total thickness of the structure that remains to support the strained-Si layer 12 (which includes both the insulator 14 and substrate 24 in FIG. 1) must be sufficient to maintain a desired level of strain in the strained-Si layer 12.

In Alternative (A) of FIG. 1, the structures 18 and 20 are bonded together by placing the strained-Si layer 12 and insulator 14 in contact with each other, and then performing any suitable wafer bonding technique known in the art. The result of the wafer bonding technique is the multilayer structure 16 shown in FIG. 1, in which the strained-Si layer 12 is between the insulator 14 and the SiGe substrate 22, such that the insulator 14 is effectively a buried layer within the structure 16. The SiGe substrate 22 is then completely removed, preferably by a method such as chemical-mechanical polishing (CMP), wafer cleaving (such as a SmartCut process available from LETI), a chemical etching process that is selective to silicon, or a combination of these techniques. The preferred method for completely removing the SiGe substrate 22 is by a selective chemical etching process such as HHA (hydrogen peroxide, hydrofluoric acid, acetic acid) etching, which preferentially etches the SiGe substrate 22. If the SmartCut process is used, a hydrogen implant step required by this process can be performed at various points during the three process steps represented in FIG. 1. The result of removing the substrate 22 is the SSOI structure 10 shown in FIG. 1, which is shown as including only the strained-Si layer 12, the insulator 14 and the substrate 24 though, as noted above, one or more additional layers could be present between the insulator 14 and substrate 24 or on the backside of the substrate 24 (opposite the insulator 14).

Alternatives (B), (C) and (D) of FIG. 1 can make use of the same materials as used in Alternative (A). Alternative (B) differs from (A) in that the insulator 14 is formed by two individual layers 14 a and 14 b formed on the strained-Si layer 12 as well as the substrate 24. The layer 14 a formed on the strained-Si layer 12 can be thermally grown or deposited by known methods. In Alternative (B), the bonding step is insulator-to-insulator (14 a to 14 b). Again, one or more additional layers could be present between the insulator layer 14 b and substrate 24, or on the backside of the substrate 24 (opposite the insulator layer 14 b).

Alternative (C) of FIG. 1 differs in that the insulator 14 is entirely grown or deposited directly on the strained-Si layer 12, instead of the substrate 24. As such, the substrate 24 (which may comprise multiple layers of various materials) may be the sole component of the structure 20. Alternative (C) generally represents the multilayer structure 16 as being formed by an insulator-to-semiconductor (14 to 24) bonding operation.

Similar to Alternative (C), Alternative (D) provides that the insulator 14 is grown or deposited directly on the strained-Si layer 12 instead of the substrate 24. Alternative (D) further differs by the use of two individual layers 24 a and 24 b to form the substrate 24, with the layer 24 a being deposited on the insulator 14. The wafer bonding operation involves mating the layers 24 a and 24 b (the latter being shown as the sole component of the structure 20), such that after wafer bonding these layers 24 a and 24 b form the substrate 24. The layers 24 a and 24 b may be formed of the same material, e.g., one of those discussed above for the substrate 24, though applications exist where the layers 24 a and 24 b are preferably formed of different materials, e.g., two or more of those discussed above for the substrate 24. If the layers 24 a and 24 b are formed of silicon, the structures 18 and 20 can be bonded together by known silicon direct bonding methods. The layer 24 a can be deposited on the insulator 14 by such known methods as chemical vapor deposition (CVD).

With each of the alternatives shown in FIG. 1, the resulting multilayer structure 16 is further processed to remove the SiGe substrate 22, leaving the SSOI structure 10. Most notably, the invention eliminates the substrate 22 that originally induced the desired tensile stress in the silicon layer 12. According to the invention, the tensile stress in the strained-Si layer 12 is maintained by the SOI structure 10, more particularly, the insulator 14 and possibly the substrate 24. The extent to which the substrate 24 contributes to maintaining the strained-Si layer 12 will depend on the particulars of the insulator 14. For example, the substrate 24 is more likely to have an affect if the insulator 14 is very thin. It is important to note that the ability for strain already induced in a silicon layer to be substantially maintained by a substrate that does not have a strain-inducing lattice mismatch with silicon was unknown until determined in an investigation leading up to this invention.

FIGS. 2 and 3 represent two SSOI MOSFET structures made possible with the present invention. In FIG. 2, a SSOI MOSFET 40 is formed by appropriately doping the strained-Si layer 12 to define source and drain regions 26 and 28 separated by a channel 30 defined by that portion of the strained-Si layer 12 between the regions 26 and 28. The source and drain regions 26 and 28 can be formed by conventional doping methods to be n+ or p+ doped. A gate structure for the channel 30 is then formed by depositing or growing a gate oxide 32, followed by a gate electrode 34, which may be metal, polysilicon, silicon, or another suitable conducting or semiconducting material. Suitable processes for forming the gate oxide 32 and electrode 34 are well known in the art, and therefore will not be discussed in any detail here. In the device of FIG. 2, the substrate 24 serves primarily as a handle wafer. In contrast, the device of FIG. 3 is a double-gate MOSFET 50, in which the substrate 24 is patterned to form a second gate electrode 36 that is insulated from the channel 30 by the insulator 14. In this role, the substrate 24 must be formed of a suitable conducting material such as tungsten or another metal, or a semiconducting material such as silicon, polysilicon, etc. As with the MOSFET 40 of FIG. 2, the double-gate MOSFET 50 of FIG. 3 can be fabricated using known MOSFET processes. Because of the greater mobility of electrons and holes in the channels 30 due to the strained-Si layers 12, each of the devices 40 and 50 of FIGS. 2 and 3 are capable of exhibiting enhanced performance as compared to conventional MOSFET devices of similar construction. Anticipated performance improvements include increased device drive current and transconductance, as well as the added ability to scale the operation voltage without sacrificing circuit speed in order to reduce power consumption.

While the invention has been described in terms of a preferred embodiment, it is apparent that other forms could be adopted by one skilled in the art. For example, different processes and process parameters could be used, the multilayer initial, intermediate and final structures could contain semiconducting and/or insulating layers in addition to those shown, and appropriate materials could be substituted for those noted. Accordingly, the scope of the invention is to be limited only by the following claims.

Claims (12)

What is claimed is:
1. A silicon-on-insulator structure comprising a strained silicon layer directly on an insulating layer, wherein the strained silicon layer does not contact a strain-inducing layer yet is under tensile strain that was not originally induced but is maintained by the insulating layer.
2. A silicon-on-insulator structure according to claim 1, wherein the insulating layer is formed of a material chosen from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide and doped aluminum oxide.
3. A silicon-on-insulator structure according to claim 1, wherein the insulating layer is a buried oxide layer between the strained silicon layer and a third layer.
4. A silicon-on-insulator structure according to claim 1, further comprising source and drain regions in the strained silicon layer, the strained silicon layer defining a channel between the source region and the drain region so as to define a field effect transistor device, the channel being in direct contact with the insulating layer.
5. A silicon-on-insulator structure according to claim 4, further comprising a gate separated from the channel by the insulating layer so that the insulating layer is a gate insulator of the field effect transistor device.
6. A silicon-on-insulator structure according to claim 4, further comprising a pair of gates separated by the channel.
7. A silicon-on-insulator structure according to claim 6, wherein a first of the gates is separated from the channel by the insulating layer so that the insulating layer is a gate insulator of the field effect transistor device.
8. A silicon-on-insulator structure according to claim 7, wherein a second of the gates is separated from the channel by a second insulating layer so that the second insulating layer is a gate insulator of a second field effect transistor device.
9. A silicon-on-insulator structure according to claim 1, further comprising a semiconductor layer contacting the insulating layer and separated from the strained silicon layer by the insulating layer.
10. A silicon-on-insulator structure comprising:
an insulating layer;
a strained silicon layer directly contacting the insulating layer, wherein the strained silicon layer does not contact a strain-inducing layer yet is under biaxial tension strain that was not originally induced but is maintained by the insulating layer;
source and drain regions in the strained silicon layer, the strained silicon layer defining a channel between the source region and the drain region, the channel being in direct contact with the insulating layer;
a gate oxide overlying the channel;
a first gate electrode contacting the gate oxide; and
a second gate electrode separated from the channel by the insulating layer such that the insulating layer defines a gate insulator for the second gate electrode;
wherein the strained silicon layer does not contact a strain-inducing layer having a lattice constant different from silicon.
11. A silicon-on-insulator structure according to claim 10, wherein the insulating layer is formed of a material chosen from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide and doped aluminum oxide.
12. A silicon-on-insulator structure according to claim 10, wherein the first and second gate electrodes are formed of a material chosen from the group consisting of metals, silicon and polysilicon.
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KR20037012889A KR100650418B1 (en) 2001-03-31 2002-03-21 Method of forming strained silicon on insulatorssoi and structures formed thereby
CA 2501580 CA2501580C (en) 2001-03-31 2002-03-21 Method of forming strained silicon on insulator (ssoi) and structures formed thereby
PCT/US2002/008795 WO2002080241A1 (en) 2001-03-31 2002-03-21 Method of forming strained silicon on insulator (ssoi) and structures formed thereby
CN 02807649 CN1254849C (en) 2001-03-31 2002-03-21 Method of forming strained silicon on insulator (SSDI) and structures formed thereby
JP2002578555A JP4318093B2 (en) 2001-03-31 2002-03-21 Method for manufacturing strained silicon-on-insulator structure
EP20020723555 EP1410428A1 (en) 2001-03-31 2002-03-21 Method of forming strained silicon on insulator (ssoi) and structures formed thereby
TW91106010A TWI222098B (en) 2001-03-31 2002-03-27 Method of forming strained silicon on insulator and structures formed thereby

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Cited By (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030052334A1 (en) * 2001-06-18 2003-03-20 Lee Minjoo L. Structure and method for a high-speed semiconductor device
US20030077867A1 (en) * 2001-03-02 2003-04-24 Fitzergald Eugene A. Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US20030203600A1 (en) * 2002-02-11 2003-10-30 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US6703144B2 (en) 2000-01-20 2004-03-09 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US20040045499A1 (en) * 2002-06-10 2004-03-11 Amberwave Systems Corporation Source and drain elements
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US20040087117A1 (en) * 2002-08-23 2004-05-06 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US20040157409A1 (en) * 2002-07-09 2004-08-12 Bruno Ghyselen Transfer of a thin layer from a wafer comprising a buffer layer
US20040164318A1 (en) * 2001-08-06 2004-08-26 Massachusetts Institute Of Technology Structures with planar strained layers
US20040173790A1 (en) * 2003-03-05 2004-09-09 Yee-Chia Yeo Method of forming strained silicon on insulator substrate
US20040217430A1 (en) * 2003-05-01 2004-11-04 Chu Jack Oon High performance FET devices and methods therefor
US20050023610A1 (en) * 2003-07-30 2005-02-03 Bruno Ghyselen Semiconductor-on-insulator structure having high-temperature elastic constraints
US20050037599A1 (en) * 2003-07-01 2005-02-17 Stmicroelectronics S.A. Process for fabricating strained layers of silicon or of a silicon/germanium alloy
US20050045995A1 (en) * 2003-08-25 2005-03-03 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US20050070070A1 (en) * 2003-09-29 2005-03-31 International Business Machines Method of forming strained silicon on insulator
US6893936B1 (en) 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
US20050108101A1 (en) * 2003-11-13 2005-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system to link orders with quotations
US20050106792A1 (en) * 2003-11-14 2005-05-19 Cea Stephen M. Transistor with strain-inducing structure in channel
US20050153524A1 (en) * 2004-01-12 2005-07-14 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
US20050151164A1 (en) * 2001-06-21 2005-07-14 Amberwave Systems Corporation Enhancement of p-type metal-oxide-semiconductor field effect transistors
US20050156255A1 (en) * 2004-01-21 2005-07-21 Taiwan Semiconductor Manufacturing Co. Noble high-k device
US20050191795A1 (en) * 2004-03-01 2005-09-01 Dureseti Chidambarrao Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US20050196936A1 (en) * 2004-03-05 2005-09-08 Nicolas Daval Methods for thermally treating a semiconductor layer
US20050196937A1 (en) * 2004-03-05 2005-09-08 Nicolas Daval Methods for forming a semiconductor structure
US6949451B2 (en) 2003-03-10 2005-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. SOI chip with recess-resistant buried insulator and method of manufacturing the same
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US20050230675A1 (en) * 2003-12-05 2005-10-20 Kabushiki Kaisha Toshiba Field-effect transistor, semiconductor device, and photo relay
US20050285187A1 (en) * 2004-06-24 2005-12-29 International Business Machines Corporation Strained-silicon CMOS device and method
US20060001088A1 (en) * 2004-07-01 2006-01-05 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer
WO2006027332A1 (en) * 2004-09-09 2006-03-16 Sez Ag Method for selective etching
US20060084244A1 (en) * 2003-04-04 2006-04-20 Yee-Chia Yeo Silicon-on-insulator chip with multiple crystal orientations
US20060134893A1 (en) * 2004-12-16 2006-06-22 Savage Donald E Fabrication of strained heterojunction structures
US20060141748A1 (en) * 2004-03-05 2006-06-29 Nicolas Daval Thermal treament of a semiconductor layer
US20060157788A1 (en) * 2005-01-19 2006-07-20 International Business Machines Corporation SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and methods for making same
US20060163557A1 (en) * 2005-01-27 2006-07-27 Fujitsu Limited Semiconductor device and fabrication process thereof
US20060266997A1 (en) * 2001-08-09 2006-11-30 Amberwave Systems Corporation Methods for forming semiconductor structures with differential surface layer thicknesses
US20070020886A1 (en) * 2005-02-03 2007-01-25 Francois Brunier Method for reducing the trap density in a semiconductor wafer
US20070032009A1 (en) * 2002-06-07 2007-02-08 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US20070096206A1 (en) * 2005-11-03 2007-05-03 International Business Machines Corporation Gate electrode stress control for finfet performance enhancement
US20070111417A1 (en) * 2004-08-31 2007-05-17 International Business Machines Corporation Strained-silicon cmos device and method
US20070122965A1 (en) * 2005-09-29 2007-05-31 International Business Machines Corporation Stress engineering using dual pad nitride with selective soi device architecture
US20070120154A1 (en) * 2005-11-30 2007-05-31 International Business Machines Corporation Finfet structure with multiply stressed gate electrode
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
US20070173037A1 (en) * 2005-10-03 2007-07-26 Nastasi Michael A Method of transferring strained semiconductor structures
US20070284688A1 (en) * 2006-06-13 2007-12-13 Wisconsin Alumni Research Foundation Pin diodes for photodetection and high-speed, high-resolution image sensing
US20080029832A1 (en) * 2006-08-03 2008-02-07 Micron Technology, Inc. Bonded strained semiconductor with a desired surface orientation and conductance direction
US20080102602A1 (en) * 2004-12-08 2008-05-01 Samsung Electronics Co., Ltd. Structure of strained silicon on insulator and method of manufacturing the same
US20080233725A1 (en) * 2007-03-23 2008-09-25 Micron Technology, Inc. Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures
US20080277734A1 (en) * 2007-05-08 2008-11-13 Micron Technology, Inc. Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US20090193379A1 (en) * 2002-07-29 2009-07-30 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20100078722A1 (en) * 2006-09-08 2010-04-01 Zhenqiang Ma Method for fabricating high-speed thin-film transistors
US7838392B2 (en) 2002-06-07 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming III-V semiconductor device structures
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US8129821B2 (en) 2002-06-25 2012-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Reacted conductive gate electrodes
US8227309B2 (en) 2006-02-16 2012-07-24 Micron Technology, Inc. Localized compressive strained semiconductor
DE102011011157A1 (en) * 2011-02-14 2012-08-16 Texas Instruments Deutschland Gmbh Method for producing an electronic device
US8617968B1 (en) 2012-06-18 2013-12-31 International Business Machines Corporation Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs)
US8765577B2 (en) 2012-09-12 2014-07-01 International Business Machines Corporation Defect free strained silicon on insulator (SSOI) substrates
US8822282B2 (en) 2001-03-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating contact regions for FET incorporating SiGe
CN104022152A (en) * 2014-06-04 2014-09-03 重庆大学 Double-gate p-channel MOSFET with compression strain thin film strain source and preparation method thereof
US9484423B2 (en) 2013-11-01 2016-11-01 Samsung Electronics Co., Ltd. Crystalline multiple-nanosheet III-V channel FETs
US9548236B2 (en) 2002-06-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US9570609B2 (en) 2013-11-01 2017-02-14 Samsung Electronics Co., Ltd. Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
US9647098B2 (en) 2014-07-21 2017-05-09 Samsung Electronics Co., Ltd. Thermionically-overdriven tunnel FETs and methods of fabricating the same

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6321101A (en) 2000-05-26 2001-12-11 Amberwave Systems Corp Buried channel strained silicon fet using an ion implanted doped layer
EP1307917A2 (en) * 2000-08-07 2003-05-07 Amberwave Systems Corporation Gate technology for strained surface channel and strained buried channel mosfet devices
JP2004507084A (en) 2000-08-16 2004-03-04 マサチューセッツ インスティテュート オブ テクノロジーMassachusetts Institute of Technology Manufacturing process of semiconductor products using graded epitaxial growth
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6646322B2 (en) 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6677192B1 (en) 2001-03-02 2004-01-13 Amberwave Systems Corporation Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002101833A1 (en) * 2001-06-07 2002-12-19 Amberwave Systems Corporation Multiple gate insulators with strained semiconductor heterostructures
WO2002103760A2 (en) * 2001-06-14 2002-12-27 Amberware Systems Corporation Method of selective removal of sige alloys
WO2003025984A2 (en) 2001-09-21 2003-03-27 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
AU2002341803A1 (en) 2001-09-24 2003-04-07 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
WO2003105189A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
FR2842350B1 (en) * 2002-07-09 2005-05-13 Method for transferring a layer of concealed semiconductor material
AU2003270040A1 (en) * 2002-08-29 2004-03-19 Massachusetts Institute Of Technology Fabrication method for a monocrystalline semiconductor layer on a substrate
US6707106B1 (en) * 2002-10-18 2004-03-16 Advanced Micro Devices, Inc. Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer
US7157774B2 (en) * 2003-01-31 2007-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Strained silicon-on-insulator transistors with mesa isolation
US20040245571A1 (en) * 2003-02-13 2004-12-09 Zhiyuan Cheng Semiconductor-on-insulator article and method of making same
DE10310740A1 (en) * 2003-03-10 2004-09-30 Forschungszentrum Jülich GmbH Method for producing a stress-relaxed layer structure on a non-lattice-matched substrate, and use of such a layer system in electronic and / or optoelectronic components
JP2004281764A (en) * 2003-03-17 2004-10-07 Seiko Epson Corp Semiconductor device and method for manufacturing it
US6864149B2 (en) * 2003-05-09 2005-03-08 Taiwan Semiconductor Manufacturing Company SOI chip with mesa isolation and recess resistant regions
US6982433B2 (en) * 2003-06-12 2006-01-03 Intel Corporation Gate-induced strain for MOS performance improvement
US6974733B2 (en) * 2003-06-16 2005-12-13 Intel Corporation Double-gate transistor with enhanced carrier mobility
US6964880B2 (en) * 2003-06-27 2005-11-15 Intel Corporation Methods for the control of flatness and electron mobility of diamond coated silicon and structures formed thereby
FR2860341B1 (en) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator Method for manufacturing lowered lower multilayer structure
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
KR20060123334A (en) * 2003-12-16 2006-12-01 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Method for forming a strained si-channel in a mosfet structure
US7205210B2 (en) 2004-02-17 2007-04-17 Freescale Semiconductor, Inc. Semiconductor structure having strained semiconductor and method therefor
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
FR2868204B1 (en) * 2004-03-25 2006-06-16 Commissariat Energie Atomique Semiconductor-type substrate on insulation comprising a carbon diamond buried layer
US7005302B2 (en) * 2004-04-07 2006-02-28 Advanced Micro Devices, Inc. Semiconductor on insulator substrate and devices formed therefrom
FR2870043B1 (en) * 2004-05-07 2006-11-24 Commissariat Energie Atomique Manufacturing of active zones of different nature directly on insulation and application to mos transistor with single or double grid
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
KR100674914B1 (en) 2004-09-25 2007-01-26 삼성전자주식회사 MOS transistor having strained channel layer and methods of manufacturing thereof
GB2420222A (en) * 2004-11-13 2006-05-17 Iqe Silicon Compounds Ltd Enhanced carrier mobility in strained semiconductor layers through smoothing surface treatment
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7355221B2 (en) * 2005-05-12 2008-04-08 International Business Machines Corporation Field effect transistor having an asymmetrically stressed channel region
KR100741923B1 (en) 2005-10-12 2007-07-23 동부일렉트로닉스 주식회사 semiconductor device and method for manufacturing the same
FR2893446B1 (en) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn Segment segment segment layer treatment
WO2007067589A2 (en) * 2005-12-05 2007-06-14 Massachusetts Institute Of Technology Insulated gate devices and method of making same
CN100431132C (en) 2006-03-30 2008-11-05 上海理工大学 Making method of adopting phase-change to realizing strain silicon on insulator
US8063397B2 (en) * 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
JP5019852B2 (en) * 2006-11-10 2012-09-05 信越化学工業株式会社 Method for manufacturing strained silicon substrate
CN101201330B (en) 2006-12-15 2010-11-10 北京有色金属研究总院 Nondestructive detecting method for strain silicon heterojunction in insulator
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
FR2912841B1 (en) * 2007-02-15 2009-05-22 Soitec Silicon On Insulator Method of polishing heterostructures
KR100937818B1 (en) * 2007-08-20 2010-01-20 주식회사 하이닉스반도체 Flash memory device and manufacturing method thereof
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
FR2929447B1 (en) * 2008-03-28 2010-05-28 Commissariat Energie Atomique Method for making a constrained layer
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US8536022B2 (en) * 2010-05-19 2013-09-17 Koninklijke Philips N.V. Method of growing composite substrate using a relaxed strained layer
CN102903739B (en) * 2012-10-19 2016-01-20 清华大学 There is the semiconductor structure of rare earth oxide
US9391198B2 (en) 2014-09-11 2016-07-12 Globalfoundries Inc. Strained semiconductor trampoline

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5081062A (en) * 1987-08-27 1992-01-14 Prahalad Vasudev Monolithic integration of silicon on insulator and gallium arsenide semiconductor technologies
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5659187A (en) * 1991-05-31 1997-08-19 International Business Machines Corporation Low defect density/arbitrary lattice constant heteroepitaxial layers
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6023082A (en) * 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
US6080235A (en) * 1997-06-03 2000-06-27 Ut-Battelle, Llc Geometric shape control of thin film ferroelectrics and resulting structures
US6251738B1 (en) * 2000-01-10 2001-06-26 International Business Machines Corporation Process for forming a silicon-germanium base of heterojunction bipolar transistor
US6310367B1 (en) * 1999-02-22 2001-10-30 Kabushiki Kaisha Toshiba MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081062A (en) * 1987-08-27 1992-01-14 Prahalad Vasudev Monolithic integration of silicon on insulator and gallium arsenide semiconductor technologies
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US5659187A (en) * 1991-05-31 1997-08-19 International Business Machines Corporation Low defect density/arbitrary lattice constant heteroepitaxial layers
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US6023082A (en) * 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US6059895A (en) 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator
US6080235A (en) * 1997-06-03 2000-06-27 Ut-Battelle, Llc Geometric shape control of thin film ferroelectrics and resulting structures
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6310367B1 (en) * 1999-02-22 2001-10-30 Kabushiki Kaisha Toshiba MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6251738B1 (en) * 2000-01-10 2001-06-26 International Business Machines Corporation Process for forming a silicon-germanium base of heterojunction bipolar transistor
US6417059B2 (en) * 2000-01-10 2002-07-09 International Business Machines Corporation Process for forming a silicon-germanium base of a heterojunction bipolar transistor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"High Performance Strained-Si p-MOSFET on SIGe-on-Insulator Substrates Fabricated by SIMOX Technology" by T.Mizuno, S. Takagi et al. Advanced LSI Tech Lab, Toshiba Corp. 1999 IEEE 22.8.1.* *
T. Mizuno, et al, High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology, IEDM 934-936-99.

Cited By (154)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6703144B2 (en) 2000-01-20 2004-03-09 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6723661B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US20030077867A1 (en) * 2001-03-02 2003-04-24 Fitzergald Eugene A. Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US8822282B2 (en) 2001-03-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating contact regions for FET incorporating SiGe
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US8436336B2 (en) 2001-06-18 2013-05-07 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US20030052334A1 (en) * 2001-06-18 2003-03-20 Lee Minjoo L. Structure and method for a high-speed semiconductor device
US20050151164A1 (en) * 2001-06-21 2005-07-14 Amberwave Systems Corporation Enhancement of p-type metal-oxide-semiconductor field effect transistors
US20040164318A1 (en) * 2001-08-06 2004-08-26 Massachusetts Institute Of Technology Structures with planar strained layers
US20070072354A1 (en) * 2001-08-06 2007-03-29 Massachusetts Institute Of Technology Structures with planar strained layers
US20060266997A1 (en) * 2001-08-09 2006-11-30 Amberwave Systems Corporation Methods for forming semiconductor structures with differential surface layer thicknesses
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US20030203600A1 (en) * 2002-02-11 2003-10-30 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US10050145B2 (en) 2002-06-07 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor device structures
US20150243788A1 (en) * 2002-06-07 2015-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for Forming Semiconductor Device Structures
US9064930B2 (en) * 2002-06-07 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor device structures
US20110318893A1 (en) * 2002-06-07 2011-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor device structures
US8586452B2 (en) * 2002-06-07 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor device structures
US9601623B2 (en) * 2002-06-07 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor device structures
US9548236B2 (en) 2002-06-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US7838392B2 (en) 2002-06-07 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming III-V semiconductor device structures
US7566606B2 (en) 2002-06-07 2009-07-28 Amberwave Systems Corporation Methods of fabricating semiconductor devices having strained dual channel layers
US20070032009A1 (en) * 2002-06-07 2007-02-08 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US10510581B2 (en) 2002-06-07 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US20040045499A1 (en) * 2002-06-10 2004-03-11 Amberwave Systems Corporation Source and drain elements
US8129821B2 (en) 2002-06-25 2012-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Reacted conductive gate electrodes
US20080265261A1 (en) * 2002-07-09 2008-10-30 S.O.I.Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US8049224B2 (en) 2002-07-09 2011-11-01 S.O.I.Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US20100314628A1 (en) * 2002-07-09 2010-12-16 S.O.I.Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US7338883B2 (en) 2002-07-09 2008-03-04 S.O.I.Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US20040157409A1 (en) * 2002-07-09 2004-08-12 Bruno Ghyselen Transfer of a thin layer from a wafer comprising a buffer layer
US20050255682A1 (en) * 2002-07-09 2005-11-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US7803694B2 (en) 2002-07-09 2010-09-28 S.O.I.Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US7534701B2 (en) 2002-07-09 2009-05-19 S.O.I. Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US20090193379A1 (en) * 2002-07-29 2009-07-30 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US7829442B2 (en) 2002-08-23 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US20040087117A1 (en) * 2002-08-23 2004-05-06 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US20040173790A1 (en) * 2003-03-05 2004-09-09 Yee-Chia Yeo Method of forming strained silicon on insulator substrate
US20050275024A1 (en) * 2003-03-10 2005-12-15 Yee-Chia Yeo SOI chip with recess-resistant buried insulator and method of manufacturing the same
US6949451B2 (en) 2003-03-10 2005-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. SOI chip with recess-resistant buried insulator and method of manufacturing the same
US7372107B2 (en) 2003-03-10 2008-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. SOI chip with recess-resistant buried insulator and method of manufacturing the same
US20080160727A1 (en) * 2003-04-04 2008-07-03 Yee-Chia Yeo Silicon-on-Insulator Chip with Multiple Crystal Orientations
US20060084244A1 (en) * 2003-04-04 2006-04-20 Yee-Chia Yeo Silicon-on-insulator chip with multiple crystal orientations
US7368334B2 (en) 2003-04-04 2008-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US7704809B2 (en) 2003-04-04 2010-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US20080132021A1 (en) * 2003-05-01 2008-06-05 International Business Machines Corporation High Performance FET Devices and Methods Thereof
US7563657B2 (en) 2003-05-01 2009-07-21 International Business Machines Corporation High performance FET devices and methods thereof
US7411214B2 (en) 2003-05-01 2008-08-12 International Business Machines Corporation High performance FET devices and methods thereof
US20080108196A1 (en) * 2003-05-01 2008-05-08 International Business Machines Corporation High Performance FET Devices and Methods Thereof
US20050161711A1 (en) * 2003-05-01 2005-07-28 International Business Machines Corporation High performance FET devices and methods thereof
US20050156169A1 (en) * 2003-05-01 2005-07-21 International Business Machines Corporation High performance FET devices and methods thereof
US7547930B2 (en) 2003-05-01 2009-06-16 International Business Machines Corporation High performance FET devices and methods thereof
US7358122B2 (en) 2003-05-01 2008-04-15 International Business Machines Corporation High performance FET devices and methods thereof
US20040217430A1 (en) * 2003-05-01 2004-11-04 Chu Jack Oon High performance FET devices and methods therefor
US7510916B2 (en) 2003-05-01 2009-03-31 International Business Machines Corporation High performance FET devices and methods thereof
US6909186B2 (en) 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US7279404B2 (en) * 2003-07-01 2007-10-09 Stmicroelectronics S.A. Process for fabricating strained layers of silicon or of a silicon/germanium alloy
US20050037599A1 (en) * 2003-07-01 2005-02-17 Stmicroelectronics S.A. Process for fabricating strained layers of silicon or of a silicon/germanium alloy
US20050023610A1 (en) * 2003-07-30 2005-02-03 Bruno Ghyselen Semiconductor-on-insulator structure having high-temperature elastic constraints
CN100505276C (en) 2003-08-25 2009-06-24 国际商业机器公司 Strained insulated silicon
US20050045995A1 (en) * 2003-08-25 2005-03-03 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US7098508B2 (en) * 2003-08-25 2006-08-29 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US20050070070A1 (en) * 2003-09-29 2005-03-31 International Business Machines Method of forming strained silicon on insulator
US20050108101A1 (en) * 2003-11-13 2005-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system to link orders with quotations
US7019326B2 (en) * 2003-11-14 2006-03-28 Intel Corporation Transistor with strain-inducing structure in channel
US20060084216A1 (en) * 2003-11-14 2006-04-20 Cea Stephen M Transistor with strain-inducing structure in channel
US7473591B2 (en) 2003-11-14 2009-01-06 Intel Corporation Transistor with strain-inducing structure in channel
US20050106792A1 (en) * 2003-11-14 2005-05-19 Cea Stephen M. Transistor with strain-inducing structure in channel
US20050230675A1 (en) * 2003-12-05 2005-10-20 Kabushiki Kaisha Toshiba Field-effect transistor, semiconductor device, and photo relay
US7145169B2 (en) * 2003-12-05 2006-12-05 Kabushiki Kaisha Toshiba Field-effect transistor, semiconductor device, and photo relay
US6992025B2 (en) 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
US20050153524A1 (en) * 2004-01-12 2005-07-14 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
US7351994B2 (en) * 2004-01-21 2008-04-01 Taiwan Semiconductor Manufacturing Company Noble high-k device
US20050156255A1 (en) * 2004-01-21 2005-07-21 Taiwan Semiconductor Manufacturing Co. Noble high-k device
US7060539B2 (en) 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US20050191795A1 (en) * 2004-03-01 2005-09-01 Dureseti Chidambarrao Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer
US7285495B2 (en) 2004-03-05 2007-10-23 S.O.I.Tec Silicon On Insulator Technologies Methods for thermally treating a semiconductor layer
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
US7276428B2 (en) 2004-03-05 2007-10-02 S.O.I.Tec Silicon On Insulator Technologies Methods for forming a semiconductor structure
US20050245049A1 (en) * 2004-03-05 2005-11-03 Takeshi Akatsu Atomic implantation and thermal treatment of a semiconductor layer
US20050196937A1 (en) * 2004-03-05 2005-09-08 Nicolas Daval Methods for forming a semiconductor structure
US7449394B2 (en) 2004-03-05 2008-11-11 S.O.I.Tec Silicon On Insulator Technologies Atomic implantation and thermal treatment of a semiconductor layer
US20060141748A1 (en) * 2004-03-05 2006-06-29 Nicolas Daval Thermal treament of a semiconductor layer
US20050196936A1 (en) * 2004-03-05 2005-09-08 Nicolas Daval Methods for thermally treating a semiconductor layer
US20050285187A1 (en) * 2004-06-24 2005-12-29 International Business Machines Corporation Strained-silicon CMOS device and method
US7227205B2 (en) 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US6893936B1 (en) 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
US20060001088A1 (en) * 2004-07-01 2006-01-05 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US8017499B2 (en) 2004-07-01 2011-09-13 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20070155130A1 (en) * 2004-07-01 2007-07-05 International Business Machines Corporation STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
US7507989B2 (en) 2004-07-01 2009-03-24 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US7485518B2 (en) 2004-07-01 2009-02-03 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20080042166A1 (en) * 2004-07-01 2008-02-21 International Business Machines Corporation STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
US20080220588A1 (en) * 2004-07-01 2008-09-11 International Business Machines Corporation STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US20070111417A1 (en) * 2004-08-31 2007-05-17 International Business Machines Corporation Strained-silicon cmos device and method
US7808081B2 (en) 2004-08-31 2010-10-05 International Business Machines Corporation Strained-silicon CMOS device and method
US8796157B2 (en) 2004-09-09 2014-08-05 Lam Research Ag Method for selective etching
WO2006027332A1 (en) * 2004-09-09 2006-03-16 Sez Ag Method for selective etching
US20080038932A1 (en) * 2004-09-09 2008-02-14 Sez Ag Method for Selective Etching
US20080102602A1 (en) * 2004-12-08 2008-05-01 Samsung Electronics Co., Ltd. Structure of strained silicon on insulator and method of manufacturing the same
US7544585B2 (en) * 2004-12-08 2009-06-09 Samsung Electronics Co., Ltd. Structure of strained silicon on insulator and method of manufacturing the same
US20060134893A1 (en) * 2004-12-16 2006-06-22 Savage Donald E Fabrication of strained heterojunction structures
US20080296615A1 (en) * 2004-12-16 2008-12-04 Savage Donald E Fabrication of strained heterojunction structures
US7973336B2 (en) 2004-12-16 2011-07-05 Wisconsin Alumni Research Foundation Released freestanding strained heterojunction structures
US7229901B2 (en) 2004-12-16 2007-06-12 Wisconsin Alumni Research Foundation Fabrication of strained heterojunction structures
US20060157788A1 (en) * 2005-01-19 2006-07-20 International Business Machines Corporation SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and methods for making same
US7217978B2 (en) 2005-01-19 2007-05-15 International Business Machines Corporation SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same
US20060163557A1 (en) * 2005-01-27 2006-07-27 Fujitsu Limited Semiconductor device and fabrication process thereof
US7262465B2 (en) * 2005-01-27 2007-08-28 Fujitsu Limited P-channel MOS transistor and fabrication process thereof
US7601606B2 (en) * 2005-02-03 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Method for reducing the trap density in a semiconductor wafer
US20070020886A1 (en) * 2005-02-03 2007-01-25 Francois Brunier Method for reducing the trap density in a semiconductor wafer
US20070122965A1 (en) * 2005-09-29 2007-05-31 International Business Machines Corporation Stress engineering using dual pad nitride with selective soi device architecture
US7550364B2 (en) 2005-09-29 2009-06-23 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US20070173037A1 (en) * 2005-10-03 2007-07-26 Nastasi Michael A Method of transferring strained semiconductor structures
US7638410B2 (en) 2005-10-03 2009-12-29 Los Alamos National Security, Llc Method of transferring strained semiconductor structure
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US20070096206A1 (en) * 2005-11-03 2007-05-03 International Business Machines Corporation Gate electrode stress control for finfet performance enhancement
US20070120154A1 (en) * 2005-11-30 2007-05-31 International Business Machines Corporation Finfet structure with multiply stressed gate electrode
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
US8435850B2 (en) 2006-02-16 2013-05-07 Micron Technology, Inc. Localized compressive strained semiconductor
US8227309B2 (en) 2006-02-16 2012-07-24 Micron Technology, Inc. Localized compressive strained semiconductor
US7777290B2 (en) 2006-06-13 2010-08-17 Wisconsin Alumni Research Foundation PIN diodes for photodetection and high-speed, high-resolution image sensing
US20070284688A1 (en) * 2006-06-13 2007-12-13 Wisconsin Alumni Research Foundation Pin diodes for photodetection and high-speed, high-resolution image sensing
US20080029832A1 (en) * 2006-08-03 2008-02-07 Micron Technology, Inc. Bonded strained semiconductor with a desired surface orientation and conductance direction
US8962447B2 (en) 2006-08-03 2015-02-24 Micron Technology, Inc. Bonded strained semiconductor with a desired surface orientation and conductance direction
US20100078722A1 (en) * 2006-09-08 2010-04-01 Zhenqiang Ma Method for fabricating high-speed thin-film transistors
US7960218B2 (en) 2006-09-08 2011-06-14 Wisconsin Alumni Research Foundation Method for fabricating high-speed thin-film transistors
US20080233725A1 (en) * 2007-03-23 2008-09-25 Micron Technology, Inc. Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures
US7871911B2 (en) 2007-03-23 2011-01-18 Micron Technology, Inc. Methods for fabricating semiconductor device structures
US7759233B2 (en) 2007-03-23 2010-07-20 Micron Technology, Inc. Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures
US20100216297A1 (en) * 2007-03-23 2010-08-26 Micron Technology, Inc. Methods for fabricating semiconductor device structures
US9076867B2 (en) 2007-05-08 2015-07-07 Micron Technology, Inc. Semiconductor device structures including strained transistor channels
US8293611B2 (en) 2007-05-08 2012-10-23 Micron Technology, Inc. Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels
US20080277734A1 (en) * 2007-05-08 2008-11-13 Micron Technology, Inc. Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels
US8679928B2 (en) 2007-05-08 2014-03-25 Micron Technology, Inc. Methods for stressing transistor channels of a semiconductor device structure
DE102011011157B4 (en) * 2011-02-14 2017-11-09 Texas Instruments Deutschland Gmbh Electronic semiconductor device and method for its manufacture
DE102011011157A1 (en) * 2011-02-14 2012-08-16 Texas Instruments Deutschland Gmbh Method for producing an electronic device
US8617968B1 (en) 2012-06-18 2013-12-31 International Business Machines Corporation Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs)
US8765577B2 (en) 2012-09-12 2014-07-01 International Business Machines Corporation Defect free strained silicon on insulator (SSOI) substrates
US8921209B2 (en) 2012-09-12 2014-12-30 International Business Machines Corporation Defect free strained silicon on insulator (SSOI) substrates
US9570609B2 (en) 2013-11-01 2017-02-14 Samsung Electronics Co., Ltd. Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
US9484423B2 (en) 2013-11-01 2016-11-01 Samsung Electronics Co., Ltd. Crystalline multiple-nanosheet III-V channel FETs
CN104022152A (en) * 2014-06-04 2014-09-03 重庆大学 Double-gate p-channel MOSFET with compression strain thin film strain source and preparation method thereof
US9647098B2 (en) 2014-07-21 2017-05-09 Samsung Electronics Co., Ltd. Thermionically-overdriven tunnel FETs and methods of fabricating the same

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