GB2420222A - Enhanced carrier mobility in strained semiconductor layers through smoothing surface treatment - Google Patents

Enhanced carrier mobility in strained semiconductor layers through smoothing surface treatment Download PDF

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Publication number
GB2420222A
GB2420222A GB0425110A GB0425110A GB2420222A GB 2420222 A GB2420222 A GB 2420222A GB 0425110 A GB0425110 A GB 0425110A GB 0425110 A GB0425110 A GB 0425110A GB 2420222 A GB2420222 A GB 2420222A
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Prior art keywords
layer
wafer
strained
semiconductor material
substrate
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GB0425110A
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GB0425110D0 (en
Inventor
Robert Cameron Harper
Maurice Howard Fisher
Aled Owen Morgan
Benoit Alfred Lou Roumiguieres
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IQE Silicon Compounds Ltd
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IQE Silicon Compounds Ltd
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Publication of GB2420222A publication Critical patent/GB2420222A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate

Abstract

The carrier mobility of a semiconductor device comprising a strained layer of Si 12 deposited on a graded SiGe strain-inducing layer 11 is improved by annealing the wafer prior to deposition of the strained layer 12, to reduce any surface roughness on the layer 12 having a wavelength of below 1 micron. The annealing can advantageously be performed at temperatures above 750 degrees centigrade in a treatment medium containing an etchant in gas form such as Hbr, CF3CL, Bcl3, CF4 or HCl..

Description

Enhancing Carrier Mobility in Strained Semiconductor Layers This invention
relates to enhancing carrier mobility in strained semiconductor layers.
Silicon (Si) is widely used in the manufacture of semiconductor devices, since it is readily commercially available and exhibits a number of desirable characteristics.
However, with increasing demands on the speed of semiconductors, it has become desirable to form semiconductor devices from materials such as Germanium (Ge) , which has higher carrier mobilities and which therefore can operate at higher speeds.
Unfortunately, materials such as Ge are not readily available commercially and do not possess the desirable characteristics of Si.
In order to overcome this problem, it is well known that the electron mobility of Si can be increased by depositing a graded strain-inducing layer of a SiGe compound onto a Si substrate. A capping layer of Si is then deposited on the compound layer. The lattice of this capping layer of Si adopts the lattice constant of the underlying compound layer.
Accordingly, the Si lattice of the capping layer is strained and has a constant which is greater than of pure Si, owing to the Ge content of the compound.
In order to prevent a lattice mismatch between the Si substrate and the SiGe compound layer, the strain-inducing layer is graded from Si1Ge0 to say Si 83Ge0. The capping layer of Si grown on the final Si0 83Ge017 compound has an electron mobility of almost doible that of the pure Si substrate.
However, the increase in hole mobility in the capping layer of Si is minimal compared with that of pure Si, thereby reducing the benefits of the strained material in devices such as MOSFET devices, which utilise hole and electrons as charge carriers.
In order to overcome this problem, it has been proposed to increase the final percentage of Ge in the strain-inducing layer to approximately Si0 65Ge0 At this level, both the electron and hole conductivities in the Si capping layer are approximately double their respective values in pure Si.
The lattice mismatch between Si and Ge in the strain- inducing layer causes strain, leading to dislocations and a disadvantage of increasing the Ge content of the strain- inducing layer in the aforementioned way is that it substantially increases the dislocations in the graded layer.
These dislocations spread through to the capping layer and for this reason, the final Ge content of the compound layer and hence the hole conductivity of heterogenous devices has hitherto been minimised.
Strained silicon-on-insulator (SSOI) structures are useful for IC device fabrication, such as complementary metal- oxide-semiconductor (CMOS) transistors and other metal-oxide- semiconductor field effect transistor (MOSFET) applications.
Such structures are produced by forming a silicon layer on a straininducing layer, such as the graded heterogenous layer hereinbefore described, so as to form a multilayer structure, in which the straininducing layer has a different lattice constant than silicon so that the strain-inducing layer induces strain in the silicon layer as a result of the lattice mismatch. The surface of the multilayer structure is then bonded to an insulator and the strain-inducing layer is then removed eq by cleaving, to yield a strained silicon-on- insulator (SSOI) structure that comprises the strained silicon layer on the insulating layer, with the insulating layer being between the substrate and strained silicon layer. As a result, the resulting Ssoi structure does not include an additional strain-inducing layer.
In any heterogenous strain-inducing layer, the lattice mismatch between the materials causes strain, leading to dislocations and cross-hatch which roughen the upper surface of the wafer on which semiconductor devices are formed. This so-called long scale roughness can have a wavelength from a few microns to tens of microns and is undesirable, since it makes further processing of the wafer difficult.
Surface characterisation of the wafer surface (using atomic force microscopy) indicates that several distinct lengths of micro-roughness are present. In addition to long scale roughness, short scale roughness having wavelengths of below one micron can be seen to be super-imposed on the long scale roughness. The wavelength of this roughness is short and as such the presence of such roughness does not have an appreciable effect on the further processing of the wafer.
We have now devised a method of enhancing the carrier mobility of in a strained layer of a semiconductor device, such as a heterogenous or SSO1 semiconductor device, which alleviates the above-mentioned problem.
In accordance with this invention, there is provided a the method of enhancing the carrier mobility in a strained layer of a semiconductor device by treating the wafer on which the device is produced to reduce surface roughness having a wavelength of below 1 micron.
The carriers in the channels of deeply-scaled MOSFET devices are closer to the device surface due to increased electric fields in the channels. Thus, high levels of short scale roughness on the surface such a device degrades the carrier mobility of the device due to surface scattering.
Accordingly, the reduction of this short scale roughness substantially improves the mobility of electrons and holes within the strained layer and in particular increases the hole mobility to a level comparable with the increase in electron.
The wafer may be treated by chemical mechanical polishing to reduce the short scale roughness. However, this is another process step and therefore adds to the expense of the wafer production. Furthermore, chemical mechanical polishing causes undesirable surface interfaces, introduces contaminants into the wafer and residual polish damage. Whilst such polishing reduces the overall surface roughness, it is better at reducing long scale than short scale roughness and merely has the effect of reducing the magnitude of short scale roughness.
Preferably, the wafer is treated by annealing to reduce the short scale roughness. Annealing can be carried out in the reactor chamber in which the wafer is processed and the ability to smooth the wafer during processing is a far more cost effective than having to provide the additional step of chemical mechanical polishing.
We have found that annealing the wafer produces a significant improvement in the occurrence of short scale surface roughness on the wafer surface, whilst only marginally improving the longer scale surface roughness.
Preferably the wafer is annealed by raising it to temperature above 750 degrees centigrade.
The wafer is preferably annealed in a treatment medium.
The treatment medium preferably comprises an etchant, preferably comprising one or more of the following chemical compounds such as HBr, CF3C1, BC13, CF4 or Rd. Preferably the etchant flows in a diluent carrier gas, such as Hydrogen or Nitrogen. A plurality of treatments may be successively performed during annealing.
For any given wafer reactor chamber, the optimum annealing conditions will vary. However by varying the length, gas flow and temperature of the anneals, along with the length, temperature and gas flows of the etches; an optimum set of conditions will be arrived at for reducing short scale surface roughness.
Preferably, the strained layer is produced by growing a layer of heterogeneous semiconductor material on a substrate.
Preferably, the wafer is treated to reduce the short scale roughness following growth of said layer of heterogeneous semiconductor material, a further layer of semiconductor material preferably then being grown.
Preferably the or each layer is grown by epitaxy.
Preferably said substrate comprises a first semiconductor material, said heterogeneous semiconductor material comprising a compound or alloy of said first semiconductor material and a second semiconductor material.
Preferably, the ratio of the second material to the first material is increased away from the substrate.
Preferably, the rate of increase of said ratio varies.
We have found that varying the rate of increase of the ratio of the second material to the first material significantly reduces the long scale surface roughness and defectivity levels at the surface of the compound layer.
Preferably, the rate of increase of said ratio increases away from the substrate towards the surface of the compound layer.
Preferably a capping layer comprising said first material is deposited on the surface of said heterogeneous semiconductor material, the wafer being treated prior to deposition of said capping layer.
Preferably the first material is Si and preferably, the second material is Ge.
Preferably the final composition of said heterogeneous semiconductor material comprises 10-35% of said second material.
Also in accordance with this invention, there is provided the treatment of a wafer of strained semiconductor material by reduction of surface roughness of the wafer having a wavelength of below 1 micron to enhance the carrier mobility of semiconductor devices formed on the wafer.
An embodiment of this invention will now be described by way of an example only and with reference to the accompanying drawings, in which: Figure 1 is a schematic sectional view through a semiconductor wafer treated in accordance with the present invention; Figure 2 is flow chart of the productions steps of the wafer of Figure 1; Figure 3 is a graph of the number of occurrences of particular roughness wavelengths of the final layer of the wafer of Figure 1; and Figure 4 is a graph of the of f current against on current for a NMOS semiconductor device formed on the final layer of the wafer of Figure 1.
Figure 5 is a similar graph of the off current against on current for a PMOS semiconductor device formed on the final layer of the wafer of Figure 1.
Referring to Figures 1 and 2 of the drawings, a semiconductor wafer is formed by epitaxially depositing a graded compound layer 11 of Si 1Ge on a Si substrate 10.
disposed the substrate 10 and a capping layer 12 of Si.
The graded layer 11 is formed by increasing X in Si1Ge from 0 at the surface of the substrate 10 to about 0.2 at the surface of the graded layer 11. This gradual change in X reduces crystalline dislocations of the type which would occur if Si0 8Ge02 were deposited directly onto the Si substrate 10.
The ratio of Ge to Si in the graded layer 11 may vary linearly. However, the ratio is preferably gradually increased in a linear manner: We have found that this variation in the rate of change X through the layer 11 significantly improves the defectivity levels and the long scale surface roughness at the surface of layer 11.
Following the growth of the graded layer 11, the wafer is annealed in accordance with the invention by raising it to a temperature in excess of 750 degrees centigrade in an etchant such as HBr, CF3C1, BC13, CF4 or HC1, which is introduced into the epitaxial growth chamber in a carrier gas such as hydrogen or nitrogen.
A thin capping layer 12 of Si is then epitaxially grown on the graded layer 11. The Si of the capping layer 12 adopts the larger lattice constant of the underlying Si0 8Ge02 and accordingly, the Si layer 12 has a greater electron mobility than that of a conventional Si layer.
Referring to Figure 3 of the drawings, the step of annealing the wafer following deposition of the graded layer 11 and prior to deposition of the capping layer 12 has the effect of significantly reducing the number of occurrences of short scale roughness wavelengths from 1/im down to the resolution limit of the measuring tool, compared with the number of occurrences in a conventional untreated wafer.
We have found that this reduction of the number of occurrences of short scale roughness wavelengths is important to device operation of deeply scaled MOSFETS. The reason for this is because the carriers in the channels are closer to the surface due to increased electric fields in the channels. The carrier mobility can become degraded due to surface scattering in materials exhibiting a high level of short scale roughness.
Referring to Figures 4 and 5 of the drawings, from tests it can be seen that N-channel (NM0s) and P-channel (PMOS) transistors fabricated on a wafer treated in accordance with this invention exhibit a substantial improvement in on current (ION) and a low off current (10FF) . This can only be due to improved mobility of both electrons and holes because all other parameters that affect the off current (10FF), such as threshold voltage, physical structure size etc. of the device, are the same as those used in a similarly tested conventional devices.
It will be appreciated that the level of on current (ION) achievable in a transistor is key to its performance: the more current that a transistor can pass, the quicker it has the ability to charge/discharge capacitors, turn on and off, and switch other devices etc. The level of the off current (I OFF) also needs to be minimised, since this so-called leakage current degrades power efficiency, especially for low standby power portable applications.
The present invention thus enables a transistor to be provided which has a substantially increased on current (I) compared with a conventional transistor and yet a low off current (10FF)

Claims (22)

  1. Claims 1. A method of enhancing the carrier mobility in a strained layer
    of a semiconductor device by treating the wafer on which the device is produced to reduce surface roughness S having a wavelength of below 1 micron.
  2. 2. A method as claimed in claim 1, in which the wafer is treated by annealing to reduce said short scale roughness.
  3. 3. A method as claimed in claim 2, in which the annealing is carried out in a reactor chamber in which layers of the wafer are deposited.
  4. 4. A method as claimed in claims 2 or 3, in which the wafer is annealed by raising it to temperature above 750 degrees centigrade.
  5. 5. A method as claimed in any of claims 2 to 4, in which wafer is annealed in a treatment medium.
  6. 6. A method as claimed in a claim 5, in which the wafer is annealed in a treatment medium containing an etchant.
  7. 7. A method as claimed in claim 6, in which the etchant comprises one or more of HBr, CF3C1, BC13, CF4 or HC1.
  8. 8. A method as claimed in claims 6 or 7, in which the etchant flows in a diluent carrier gas, such as Hydrogen or Nitrogen.
  9. 9. A method as claimed in any preceding claim, in which the strained layer is formed on a strain-inducing layer.
  10. 10. A method as claimed in claim 9, in which the strain- inducing layer is formed by growing a layer of heterogeneous semiconductor material on a substrate.
  11. 11. A method as claimed in claims 9 or 10, in which the wafer is treated to reduce the short scale roughness following growth of said straininducing layer.
  12. 12. A method as claimed in any of claims 9 to 11, in which the or each layer is grown by epitaxy.
  13. 13. A method as claimed in any of claims 9 to 12, in which said substrate comprises a first semiconductor material, said strain-inducing layer comprising a compound of said first semiconductor material and a second semiconductor material.
  14. 14. A method as claimed in claims 13, in which the ratio of the second material to the first material is increased away from the substrate.
  15. 15. A method as claimed in claims 14, in which the rate of increase of said ratio varies.
  16. 16. A method as claimed in claims 15, in which the rate of increase of said ratio increases away from the substrate towards the surface of the compound layer.
  17. 17. A method as claimed in any of claims 13 to 16, in which the strained layer comprises a capping layer comprising of said first material deposited on the surface of said heterogeneous semiconductor material, the wafer being treated prior to deposition of said capping layer.
  18. 18. A method as claimed in any of claims 13 to 17, in which the first material is Si and the second material is Ge.
  19. 19. A method as claimed in any of claims 13 to 18, in which the final composition of said heterogeneous semiconductor material comprises 10-35% of said second material.
  20. 20. A method as claimed in any preceding claim, in which the upper surface of the strained layer is bonded to an insulating layer, the strained layer then being separated from the layer(s) on which the strained layer was produced.
  21. 21. A method substantially as herein described with reference to the accompanying drawings.
  22. 22. The treatment of a wafer of a strained semiconductor material by reduction of surface roughness of the wafer having a wavelength of below 1 micron to enhance the carrier mobility of semiconductor devices formed on the wafer.
GB0425110A 2004-11-13 2004-11-13 Enhanced carrier mobility in strained semiconductor layers through smoothing surface treatment Withdrawn GB2420222A (en)

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GB0425110D0 GB0425110D0 (en) 2004-12-15
GB2420222A true GB2420222A (en) 2006-05-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882374A (en) * 2014-02-27 2015-09-02 旺宏电子股份有限公司 Etching method and etching composition

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Publication number Priority date Publication date Assignee Title
US20020140031A1 (en) * 2001-03-31 2002-10-03 Kern Rim Strained silicon on insulator structures
US20020185686A1 (en) * 2001-06-12 2002-12-12 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030003679A1 (en) * 2001-06-29 2003-01-02 Doyle Brian S. Creation of high mobility channels in thin-body SOI devices
US20030132433A1 (en) * 2002-01-15 2003-07-17 Piner Edwin L. Semiconductor structures including a gallium nitride material component and a silicon germanium component
US20030143783A1 (en) * 2002-01-31 2003-07-31 Maa Jer-Shen Method to form relaxed SiGe layer with high Ge content
US20040067644A1 (en) * 2002-10-04 2004-04-08 Malik Igor J. Non-contact etch annealing of strained layers
WO2004034453A1 (en) * 2002-10-04 2004-04-22 Silicon Genesis Corporation Method for treating semiconductor material
US20040075105A1 (en) * 2002-08-23 2004-04-22 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
EP1437765A1 (en) * 2001-08-23 2004-07-14 Sumitomo Mitsubishi Silicon Corporation Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
WO2004068556A2 (en) * 2003-01-27 2004-08-12 Amberwave Systems Corporation Semiconductor structures with structural homogeneity

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Publication number Priority date Publication date Assignee Title
US20020140031A1 (en) * 2001-03-31 2002-10-03 Kern Rim Strained silicon on insulator structures
US20020185686A1 (en) * 2001-06-12 2002-12-12 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030003679A1 (en) * 2001-06-29 2003-01-02 Doyle Brian S. Creation of high mobility channels in thin-body SOI devices
EP1437765A1 (en) * 2001-08-23 2004-07-14 Sumitomo Mitsubishi Silicon Corporation Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
US20030132433A1 (en) * 2002-01-15 2003-07-17 Piner Edwin L. Semiconductor structures including a gallium nitride material component and a silicon germanium component
US20030143783A1 (en) * 2002-01-31 2003-07-31 Maa Jer-Shen Method to form relaxed SiGe layer with high Ge content
US20040075105A1 (en) * 2002-08-23 2004-04-22 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US20040067644A1 (en) * 2002-10-04 2004-04-08 Malik Igor J. Non-contact etch annealing of strained layers
WO2004034453A1 (en) * 2002-10-04 2004-04-22 Silicon Genesis Corporation Method for treating semiconductor material
WO2004068556A2 (en) * 2003-01-27 2004-08-12 Amberwave Systems Corporation Semiconductor structures with structural homogeneity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882374A (en) * 2014-02-27 2015-09-02 旺宏电子股份有限公司 Etching method and etching composition
CN104882374B (en) * 2014-02-27 2018-03-06 旺宏电子股份有限公司 Lithographic method and etching constituent

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