ATE521085T1 - Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur - Google Patents

Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur

Info

Publication number
ATE521085T1
ATE521085T1 AT06793255T AT06793255T ATE521085T1 AT E521085 T1 ATE521085 T1 AT E521085T1 AT 06793255 T AT06793255 T AT 06793255T AT 06793255 T AT06793255 T AT 06793255T AT E521085 T1 ATE521085 T1 AT E521085T1
Authority
AT
Austria
Prior art keywords
heterostructure
semiconductor
insulating layer
active layer
bonding
Prior art date
Application number
AT06793255T
Other languages
English (en)
Inventor
Xavier Hebras
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE521085T1 publication Critical patent/ATE521085T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Light Receiving Elements (AREA)
  • Semiconductor Lasers (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
AT06793255T 2005-09-08 2006-09-06 Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur ATE521085T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0509168A FR2890489B1 (fr) 2005-09-08 2005-09-08 Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
PCT/EP2006/066046 WO2007028800A1 (fr) 2005-09-08 2006-09-06 Procédé de fabrication d'une hétérostructure de type semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
ATE521085T1 true ATE521085T1 (de) 2011-09-15

Family

ID=36593036

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06793255T ATE521085T1 (de) 2005-09-08 2006-09-06 Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur

Country Status (8)

Country Link
US (1) US7485551B2 (de)
EP (1) EP1922751B1 (de)
JP (1) JP2009508329A (de)
KR (1) KR100979930B1 (de)
CN (1) CN101258591B (de)
AT (1) ATE521085T1 (de)
FR (1) FR2890489B1 (de)
WO (1) WO2007028800A1 (de)

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WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
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Also Published As

Publication number Publication date
FR2890489A1 (fr) 2007-03-09
US20070054466A1 (en) 2007-03-08
CN101258591B (zh) 2011-04-20
US7485551B2 (en) 2009-02-03
JP2009508329A (ja) 2009-02-26
KR100979930B1 (ko) 2010-09-03
WO2007028800A1 (fr) 2007-03-15
EP1922751A1 (de) 2008-05-21
FR2890489B1 (fr) 2008-03-07
KR20080040759A (ko) 2008-05-08
EP1922751B1 (de) 2011-08-17
CN101258591A (zh) 2008-09-03

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