SG10201913059PA - High resistivity silicon-on-insulator structure and method of manufacture thereof - Google Patents

High resistivity silicon-on-insulator structure and method of manufacture thereof

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Publication number
SG10201913059PA
SG10201913059PA SG10201913059PA SG10201913059PA SG10201913059PA SG 10201913059P A SG10201913059P A SG 10201913059PA SG 10201913059P A SG10201913059P A SG 10201913059PA SG 10201913059P A SG10201913059P A SG 10201913059PA SG 10201913059P A SG10201913059P A SG 10201913059PA
Authority
SG
Singapore
Prior art keywords
manufacture
high resistivity
insulator structure
resistivity silicon
silicon
Prior art date
Application number
SG10201913059PA
Inventor
Jeffrey L Libbert
Qingmin Liu
Gang Wang
Andrew M Jones
Original Assignee
Globalwafers Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalwafers Co Ltd filed Critical Globalwafers Co Ltd
Publication of SG10201913059PA publication Critical patent/SG10201913059PA/en

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
SG10201913059PA 2016-12-05 2017-12-01 High resistivity silicon-on-insulator structure and method of manufacture thereof SG10201913059PA (en)

Applications Claiming Priority (1)

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US201662429922P 2016-12-05 2016-12-05

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SG10201913059PA true SG10201913059PA (en) 2020-02-27

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Country Link
US (2) US10468295B2 (en)
EP (2) EP4009361A1 (en)
JP (2) JP6801105B2 (en)
KR (2) KR102587815B1 (en)
CN (2) CN115714130A (en)
SG (1) SG10201913059PA (en)
TW (2) TWI727123B (en)
WO (1) WO2018106535A1 (en)

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US10943813B2 (en) * 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
FR3098642B1 (en) * 2019-07-12 2021-06-11 Soitec Silicon On Insulator method of manufacturing a structure comprising a thin layer transferred to a support provided with a charge trapping layer
US11171015B2 (en) * 2019-09-11 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer
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FR3116151A1 (en) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE
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FR3137493A1 (en) * 2022-06-29 2024-01-05 Soitec METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A BARRIER LAYER TO THE DIFFUSION OF ATOMIC SPECIES
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