FR2934925B1 - Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage. - Google Patents

Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage.

Info

Publication number
FR2934925B1
FR2934925B1 FR0855447A FR0855447A FR2934925B1 FR 2934925 B1 FR2934925 B1 FR 2934925B1 FR 0855447 A FR0855447 A FR 0855447A FR 0855447 A FR0855447 A FR 0855447A FR 2934925 B1 FR2934925 B1 FR 2934925B1
Authority
FR
France
Prior art keywords
stabilize
manufacturing
bonding interface
ion implantations
implantations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0855447A
Other languages
English (en)
Other versions
FR2934925A1 (fr
Inventor
Konstantin Bourdelle
Didier Landru
Karine Landry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0855447A priority Critical patent/FR2934925B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to CN200980126223XA priority patent/CN102084478A/zh
Priority to JP2011521500A priority patent/JP2011530182A/ja
Priority to US12/997,835 priority patent/US20110165758A1/en
Priority to KR1020117000073A priority patent/KR20110055508A/ko
Priority to PCT/EP2009/058434 priority patent/WO2010015467A1/fr
Priority to EP09804531A priority patent/EP2311082A1/fr
Publication of FR2934925A1 publication Critical patent/FR2934925A1/fr
Application granted granted Critical
Publication of FR2934925B1 publication Critical patent/FR2934925B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
FR0855447A 2008-08-06 2008-08-06 Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage. Expired - Fee Related FR2934925B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0855447A FR2934925B1 (fr) 2008-08-06 2008-08-06 Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage.
JP2011521500A JP2011530182A (ja) 2008-08-06 2009-07-03 接着接合界面を安定するためにイオンを注入する工程を備える構造物製造方法
US12/997,835 US20110165758A1 (en) 2008-08-06 2009-07-03 Method for making a structure comprising a step for implanting ions in order to stabilize the adhesive bonding interface
KR1020117000073A KR20110055508A (ko) 2008-08-06 2009-07-03 접착 접합 계면을 안정화시키기 위한 이온 주입 단계를 포함하는 구조의 제조 방법
CN200980126223XA CN102084478A (zh) 2008-08-06 2009-07-03 制造包括注入离子步骤以稳定粘接键合界面的结构的方法
PCT/EP2009/058434 WO2010015467A1 (fr) 2008-08-06 2009-07-03 Procédé de fabrication de structure comportant une étape d'implantation d'ions afin de stabiliser l'interface de liaison par collage
EP09804531A EP2311082A1 (fr) 2008-08-06 2009-07-03 Procede de fabrication de structure comportant une etape d'implantation d'ions afin de stabiliser l'interface de liaison par collage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0855447A FR2934925B1 (fr) 2008-08-06 2008-08-06 Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage.

Publications (2)

Publication Number Publication Date
FR2934925A1 FR2934925A1 (fr) 2010-02-12
FR2934925B1 true FR2934925B1 (fr) 2011-02-25

Family

ID=40344907

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0855447A Expired - Fee Related FR2934925B1 (fr) 2008-08-06 2008-08-06 Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage.

Country Status (7)

Country Link
US (1) US20110165758A1 (fr)
EP (1) EP2311082A1 (fr)
JP (1) JP2011530182A (fr)
KR (1) KR20110055508A (fr)
CN (1) CN102084478A (fr)
FR (1) FR2934925B1 (fr)
WO (1) WO2010015467A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2142182B1 (fr) * 2007-02-06 2017-09-27 Neuroquest Inc. Composition comprenant des composés terpéniques et procédés d'inhibition de la transmission nerveuse
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR2978603B1 (fr) * 2011-07-28 2013-08-23 Soitec Silicon On Insulator Procede de transfert d'une couche semi-conductrice monocristalline sur un substrat support
FR2995445B1 (fr) 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
FR2995447B1 (fr) 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
US9490201B2 (en) * 2013-03-13 2016-11-08 Intel Corporation Methods of forming under device interconnect structures

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1596184A (en) * 1976-11-27 1981-08-19 Fujitsu Ltd Method of manufacturing semiconductor devices
FR2506344B2 (fr) * 1980-02-01 1986-07-11 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
KR910009318B1 (ko) * 1987-09-08 1991-11-09 미쓰비시 뎅끼 가부시기가이샤 반도체 장치의 제조 및 고내압 파묻음 절연막 형성방법
JP3139904B2 (ja) * 1993-12-28 2001-03-05 新日本製鐵株式会社 半導体基板の製造方法および製造装置
US6720627B1 (en) * 1995-10-04 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device having junction depths for reducing short channel effect
AU5760199A (en) * 1998-09-25 2000-04-17 Asahi Kasei Kabushiki Kaisha Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
WO2001082346A1 (fr) * 2000-04-24 2001-11-01 Beijing Normal University Procede de fabrication d'un materiau en silicium sur isolant (soi)
KR100367740B1 (ko) * 2000-08-16 2003-01-10 주식회사 하이닉스반도체 반도체 소자의 게이트 산화막 제조방법
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6551898B1 (en) * 2001-11-01 2003-04-22 The United States Of America As Represented By The Secretary Of The Navy Creation of a polarizable layer in the buried oxide of silicon-on-insulator substrates for the fabrication of non-volatile memory
US6982229B2 (en) * 2003-04-18 2006-01-03 Lsi Logic Corporation Ion recoil implantation and enhanced carrier mobility in CMOS device
US7662701B2 (en) * 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7052978B2 (en) * 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
CN1992173B (zh) * 2005-11-30 2010-04-21 硅起源股份有限公司 用于注入键合衬底以便导电的方法和结构
US7778501B2 (en) * 2007-04-03 2010-08-17 Hewlett-Packard Development Company, L.P. Integrated circuits having photonic interconnect layers and methods for fabricating same
US20100216295A1 (en) * 2009-02-24 2010-08-26 Alex Usenko Semiconductor on insulator made using improved defect healing process

Also Published As

Publication number Publication date
FR2934925A1 (fr) 2010-02-12
CN102084478A (zh) 2011-06-01
JP2011530182A (ja) 2011-12-15
KR20110055508A (ko) 2011-05-25
WO2010015467A1 (fr) 2010-02-11
EP2311082A1 (fr) 2011-04-20
US20110165758A1 (en) 2011-07-07

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20130430