FR2865574B1 - Procede de fabrication d'un substrat demontable - Google Patents

Procede de fabrication d'un substrat demontable

Info

Publication number
FR2865574B1
FR2865574B1 FR0400694A FR0400694A FR2865574B1 FR 2865574 B1 FR2865574 B1 FR 2865574B1 FR 0400694 A FR0400694 A FR 0400694A FR 0400694 A FR0400694 A FR 0400694A FR 2865574 B1 FR2865574 B1 FR 2865574B1
Authority
FR
France
Prior art keywords
manufacturing
demountable
substrate
demountable substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0400694A
Other languages
English (en)
Other versions
FR2865574A1 (fr
Inventor
Olivier Rayssac
Takeshi Akatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0400694A priority Critical patent/FR2865574B1/fr
Priority to PCT/IB2005/000347 priority patent/WO2005074022A1/fr
Priority to EP05702483A priority patent/EP1709676A1/fr
Priority to JP2006550359A priority patent/JP4905784B2/ja
Publication of FR2865574A1 publication Critical patent/FR2865574A1/fr
Application granted granted Critical
Publication of FR2865574B1 publication Critical patent/FR2865574B1/fr
Priority to US11/481,696 priority patent/US7544265B2/en
Priority to US12/392,888 priority patent/US8012289B2/en
Priority to US13/151,358 priority patent/US20110233733A1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/915—Separating from substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Thin Film Transistor (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Silicon Compounds (AREA)
FR0400694A 2004-01-26 2004-01-26 Procede de fabrication d'un substrat demontable Expired - Lifetime FR2865574B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0400694A FR2865574B1 (fr) 2004-01-26 2004-01-26 Procede de fabrication d'un substrat demontable
EP05702483A EP1709676A1 (fr) 2004-01-26 2005-01-24 Procede de fabrication d'un substrat separable
JP2006550359A JP4905784B2 (ja) 2004-01-26 2005-01-24 剥離基板の製造方法
PCT/IB2005/000347 WO2005074022A1 (fr) 2004-01-26 2005-01-24 Procede de fabrication d'un substrat separable
US11/481,696 US7544265B2 (en) 2004-01-26 2006-07-05 Method of fabricating a release substrate
US12/392,888 US8012289B2 (en) 2004-01-26 2009-02-25 Method of fabricating a release substrate
US13/151,358 US20110233733A1 (en) 2004-01-26 2011-06-02 Method of fabricating a release substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0400694A FR2865574B1 (fr) 2004-01-26 2004-01-26 Procede de fabrication d'un substrat demontable

Publications (2)

Publication Number Publication Date
FR2865574A1 FR2865574A1 (fr) 2005-07-29
FR2865574B1 true FR2865574B1 (fr) 2006-04-07

Family

ID=34717408

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0400694A Expired - Lifetime FR2865574B1 (fr) 2004-01-26 2004-01-26 Procede de fabrication d'un substrat demontable

Country Status (5)

Country Link
US (3) US7544265B2 (fr)
EP (1) EP1709676A1 (fr)
JP (1) JP4905784B2 (fr)
FR (1) FR2865574B1 (fr)
WO (1) WO2005074022A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3753047B1 (fr) * 2018-02-13 2022-10-05 Soitec Structure démontable et procédé de démontage utilisant ladite structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
FR2926672B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331475B1 (en) * 1995-01-12 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Method and manufacturing semiconductor device
SG55413A1 (en) * 1996-11-15 1998-12-21 Method Of Manufacturing Semico Method of manufacturing semiconductor article
JP3116085B2 (ja) * 1997-09-16 2000-12-11 東京農工大学長 半導体素子形成法
JPH11307747A (ja) * 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
US6534381B2 (en) * 1999-01-08 2003-03-18 Silicon Genesis Corporation Method for fabricating multi-layered substrates
US6255195B1 (en) * 1999-02-22 2001-07-03 Intersil Corporation Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
WO2000074932A1 (fr) * 1999-06-03 2000-12-14 The Penn State Research Foundation Matieres a reseau de colonnes de porosite de surface deposees en film mince
US6352909B1 (en) * 2000-01-06 2002-03-05 Silicon Wafer Technologies, Inc. Process for lift-off of a layer from a substrate
FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
US7309620B2 (en) * 2002-01-11 2007-12-18 The Penn State Research Foundation Use of sacrificial layers in the manufacture of high performance systems on tailored substrates
FR2860249B1 (fr) * 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
FR2866983B1 (fr) * 2004-03-01 2006-05-26 Soitec Silicon On Insulator Realisation d'une entite en materiau semiconducteur sur substrat
CN101027769B (zh) * 2004-09-21 2017-06-23 Soitec公司 具有对要键合表面的处理的转移方法
US7575988B2 (en) * 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3753047B1 (fr) * 2018-02-13 2022-10-05 Soitec Structure démontable et procédé de démontage utilisant ladite structure

Also Published As

Publication number Publication date
JP4905784B2 (ja) 2012-03-28
US20070077729A1 (en) 2007-04-05
WO2005074022A1 (fr) 2005-08-11
US8012289B2 (en) 2011-09-06
JP2007524237A (ja) 2007-08-23
US20090179299A1 (en) 2009-07-16
US20110233733A1 (en) 2011-09-29
EP1709676A1 (fr) 2006-10-11
FR2865574A1 (fr) 2005-07-29
US7544265B2 (en) 2009-06-09

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