ATE426918T1 - Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dunnen schicht - Google Patents

Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dunnen schicht

Info

Publication number
ATE426918T1
ATE426918T1 AT04700491T AT04700491T ATE426918T1 AT E426918 T1 ATE426918 T1 AT E426918T1 AT 04700491 T AT04700491 T AT 04700491T AT 04700491 T AT04700491 T AT 04700491T AT E426918 T1 ATE426918 T1 AT E426918T1
Authority
AT
Austria
Prior art keywords
layers
wafer
recycling
layer structure
layer
Prior art date
Application number
AT04700491T
Other languages
English (en)
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Takeshi Akatsu
Yves Levaillant
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0300099A external-priority patent/FR2849715B1/fr
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE426918T1 publication Critical patent/ATE426918T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02032Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00Single-crystal growth by condensing evaporated or sublimed materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Water Treatment By Sorption (AREA)
  • Solid-Sorbent Or Filter-Aiding Compositions (AREA)
AT04700491T 2003-01-07 2004-01-07 Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dunnen schicht ATE426918T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0300099A FR2849715B1 (fr) 2003-01-07 2003-01-07 Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince
US47243503P 2003-05-22 2003-05-22

Publications (1)

Publication Number Publication Date
ATE426918T1 true ATE426918T1 (de) 2009-04-15

Family

ID=32715106

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04700491T ATE426918T1 (de) 2003-01-07 2004-01-07 Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dunnen schicht

Country Status (8)

Country Link
US (2) US20050167002A1 (de)
EP (1) EP1588416B1 (de)
JP (1) JP4949014B2 (de)
KR (1) KR100889886B1 (de)
CN (1) CN100483666C (de)
AT (1) ATE426918T1 (de)
DE (1) DE602004020181D1 (de)
WO (1) WO2004061944A1 (de)

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US20090325362A1 (en) * 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
JP5047609B2 (ja) * 2003-01-07 2012-10-10 ソワテク 除去構造を含んでなるウェハーの、その薄層を除去した後の、機械的手段による循環使用
FR2892228B1 (fr) * 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7825006B2 (en) * 2004-05-06 2010-11-02 Cree, Inc. Lift-off process for GaN films formed on SiC substrates and devices fabricated using the method
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
US7932111B2 (en) * 2005-02-23 2011-04-26 Cree, Inc. Substrate removal process for high light extraction LEDs
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
KR100672731B1 (ko) * 2005-10-04 2007-01-24 동부일렉트로닉스 주식회사 반도체 소자의 금속배선 형성방법
EP1933384B1 (de) * 2006-12-15 2013-02-13 Soitec Halbleiter-Heterostruktur
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
US20080173895A1 (en) * 2007-01-24 2008-07-24 Sharp Laboratories Of America, Inc. Gallium nitride on silicon with a thermal expansion transition buffer layer
KR20080113479A (ko) * 2007-06-25 2008-12-31 엘지이노텍 주식회사 웨이퍼 재활용 방법
US20090042353A1 (en) * 2007-08-09 2009-02-12 Yi Ma Integrated circuit fabrication process for a high melting temperature silicide with minimal post-laser annealing dopant deactivation
US7737036B2 (en) * 2007-08-09 2010-06-15 Applied Materials, Inc. Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation
US7863193B2 (en) * 2007-08-09 2011-01-04 Applied Materials, Inc. Integrated circuit fabrication process using a compression cap layer in forming a silicide with minimal post-laser annealing dopant deactivation
FR2922681A1 (fr) 2007-10-23 2009-04-24 Soitec Silicon On Insulator Procede de detachement d'un substrat.
US7998835B2 (en) * 2008-01-15 2011-08-16 Globalfoundries Singapore Pte. Ltd. Strain-direct-on-insulator (SDOI) substrate and method of forming
US8299485B2 (en) * 2008-03-19 2012-10-30 Soitec Substrates for monolithic optical circuits and electronic circuits
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
US7745853B2 (en) * 2008-06-18 2010-06-29 Chang Gung University Multi-layer structure with a transparent gate
DE102008063402B4 (de) * 2008-12-31 2013-10-17 Advanced Micro Devices, Inc. Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
EP2333824B1 (de) 2009-12-11 2014-04-16 Soitec Herstellung von dünnen SOI-Vorrichtungen
FR2955205B1 (fr) * 2009-12-16 2012-09-21 St Microelectronics Sa Dispositif microelectronique, en particulier capteur d'image a illumination par la face arriere et procede de fabrication
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure
TWI562195B (en) * 2010-04-27 2016-12-11 Pilegrowth Tech S R L Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication
US8536022B2 (en) 2010-05-19 2013-09-17 Koninklijke Philips N.V. Method of growing composite substrate using a relaxed strained layer
US8692261B2 (en) * 2010-05-19 2014-04-08 Koninklijke Philips N.V. Light emitting device grown on a relaxed layer
US9564320B2 (en) * 2010-06-18 2017-02-07 Soraa, Inc. Large area nitride crystal and method for making it
WO2012099701A1 (en) * 2010-12-31 2012-07-26 Solexel, Inc. Method for reconstructing a semiconductor template
FR2972567B1 (fr) 2011-03-09 2013-03-22 Soitec Silicon On Insulator Méthode de formation d'une structure de ge sur iii/v sur isolant
MY167902A (en) * 2011-05-26 2018-09-26 Solexel Inc Method and apparatus for reconditioning a carrier wafer for reuse
CN102820251A (zh) * 2011-06-08 2012-12-12 中国科学院上海微系统与信息技术研究所 一种基于键合工艺的高k介质埋层的soi材料制备方法
FR2977069B1 (fr) * 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
CA2840517A1 (en) * 2011-06-29 2013-06-27 Stephen R. Forrest Sacrificial etch protection layers for reuse of wafers after epitaxial lift off
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
JP5810907B2 (ja) * 2011-12-28 2015-11-11 日亜化学工業株式会社 基板の再生方法及び該再生方法を用いた窒化物半導体素子の製造方法
JP6091805B2 (ja) * 2012-08-27 2017-03-08 シャープ株式会社 再生基板の製造方法
KR101984934B1 (ko) * 2012-11-21 2019-09-03 서울바이오시스 주식회사 기판 재생 방법 및 재생 기판
KR102071034B1 (ko) 2013-02-28 2020-01-29 서울바이오시스 주식회사 질화물 기판 제조 방법
US20140264456A1 (en) * 2013-03-15 2014-09-18 Semiconductor Components Industries, Llc Method of forming a high electron mobility semiconductor device
KR102116828B1 (ko) * 2013-04-29 2020-06-01 서울바이오시스 주식회사 기판 재생 방법
WO2015019539A1 (ja) * 2013-08-06 2015-02-12 シャープ株式会社 再生基板の製造方法
CN105993063A (zh) * 2013-12-02 2016-10-05 应用材料公司 用于基板处理的方法
WO2015112308A1 (en) 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof
EP3221885B1 (de) 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. Hochresistiver halbleiter-auf-isolator-wafer und verfahren zur herstellung
EP3221884B1 (de) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. Hochbeständiger soi-wafer mit ladungsabfangenden schichten und, verfahren zu deren herstellung
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
CN104377301A (zh) * 2014-11-24 2015-02-25 苏州矩阵光电有限公司 一种ⅲ-ⅴ族化合物半导体霍尔元件及其制备方法
CN104393168A (zh) * 2014-11-25 2015-03-04 苏州矩阵光电有限公司 一种霍尔元件及其制备方法
JP6517360B2 (ja) 2015-03-03 2019-05-22 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited 膜応力を制御可能なシリコン基板の上に電荷トラップ用多結晶シリコン膜を成長させる方法
JP6637515B2 (ja) 2015-03-17 2020-01-29 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 半導体オン・インシュレータ構造の製造において使用するための熱的に安定した電荷トラップ層
JP6533309B2 (ja) 2015-06-01 2019-06-19 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited 多層構造体の製造方法
JP6592534B2 (ja) * 2015-06-01 2019-10-16 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited 多層構造体及びその製造方法
CN104932194A (zh) * 2015-07-22 2015-09-23 京东方科技集团股份有限公司 一种掩膜板及其制备方法、掩膜板的回收方法
US9496128B1 (en) 2015-10-15 2016-11-15 International Business Machines Corporation Controlled spalling utilizing vaporizable release layers
CN105374664A (zh) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 一种InP薄膜复合衬底的制备方法
SG10201913407TA (en) 2015-11-20 2020-03-30 Globalwafers Co Ltd Manufacturing method of smoothing a semiconductor surface
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
WO2017142849A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a buried high resistivity layer
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
WO2017155808A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
EP3758050A1 (de) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Halbleiter-auf-isolator-struktur mit niedrigtemperatur-fliessfähiger oxidschicht und verfahren zur herstellung davon
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
EP3469120B1 (de) 2016-06-08 2022-02-02 GlobalWafers Co., Ltd. Hochohmige monokristalline siliciumbarren und wafer mit verbesserter mechanischer festigkeit
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
CN110178211B (zh) 2016-10-26 2022-12-13 环球晶圆股份有限公司 具有增强电荷俘获效率的高电阻率绝缘体上硅衬底
US10700012B2 (en) * 2017-04-14 2020-06-30 Qualcomm Incorporated Porous silicon dicing
KR101905770B1 (ko) 2017-04-17 2018-12-05 한국과학기술원 기공층이 형성된 Ge 기판을 이용한 화합물 반도체 제조 방법
EP3989272A1 (de) 2017-07-14 2022-04-27 Sunedison Semiconductor Limited Verfahren zur herstellung einer halbleiter-auf-isolator-struktur
CN109786306A (zh) * 2018-03-22 2019-05-21 苏州捷芯威半导体有限公司 半导体器件制造方法和衬底支撑结构
FR3079345B1 (fr) * 2018-03-26 2020-02-21 Soitec Procede de fabrication d'un substrat pour dispositif radiofrequence
FR3079346B1 (fr) * 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
US10818540B2 (en) 2018-06-08 2020-10-27 Globalwafers Co., Ltd. Method for transfer of a thin layer of silicon
US11466384B2 (en) 2019-01-08 2022-10-11 Slt Technologies, Inc. Method of forming a high quality group-III metal nitride boule or wafer using a patterned substrate
JP2023513570A (ja) 2020-02-11 2023-03-31 エスエルティー テクノロジーズ インコーポレイテッド 改善されたiii族窒化物基板、その製造方法、並びにその使用方法
US11721549B2 (en) 2020-02-11 2023-08-08 Slt Technologies, Inc. Large area group III nitride crystals and substrates, methods of making, and methods of use
CN111653649B (zh) * 2020-06-05 2023-09-05 中国科学院上海微系统与信息技术研究所 一种Si基InGaAs光电探测器的制备方法及光电探测器
CN111933518A (zh) * 2020-08-18 2020-11-13 西安电子科技大学 基于SiC衬底和LiCoO2缓冲层的AlN单晶材料制备方法
CN112967930B (zh) * 2021-02-07 2023-05-12 西安微电子技术研究所 一种SiC晶圆的金属化层剥离方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6159824A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
FR2775121B1 (fr) 1998-02-13 2000-05-05 Picogiga Sa Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
FR2783254B1 (fr) * 1998-09-10 2000-11-10 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin,et produits obtenus
US6555443B1 (en) * 1998-11-11 2003-04-29 Robert Bosch Gmbh Method for production of a thin film and a thin-film solar cell, in particular, on a carrier substrate
JP2000223682A (ja) * 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
FR2794893B1 (fr) * 1999-06-14 2001-09-14 France Telecom Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie
US6500732B1 (en) * 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US6690043B1 (en) * 1999-11-26 2004-02-10 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
US6750130B1 (en) * 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
JP2001284558A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 積層半導体基板及びその製造方法並びに半導体装置
JP4269541B2 (ja) * 2000-08-01 2009-05-27 株式会社Sumco 半導体基板と電界効果型トランジスタ並びにSiGe層の形成方法及びこれを用いた歪みSi層の形成方法と電界効果型トランジスタの製造方法
EP1309989B1 (de) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
JP2002329664A (ja) * 2001-04-26 2002-11-15 Mitsubishi Materials Silicon Corp SiGe層の形成方法及びこれを用いた歪みSi層の形成方法と電界効果型トランジスタの製造方法、並びに半導体ウェーハ及びこれを用いた歪みSiウェーハと電界効果型トランジスタ
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US6841001B2 (en) * 2002-07-19 2005-01-11 Cree, Inc. Strain compensated semiconductor structures and methods of fabricating strain compensated semiconductor structures

Also Published As

Publication number Publication date
KR20050092394A (ko) 2005-09-21
JP4949014B2 (ja) 2012-06-06
EP1588416A1 (de) 2005-10-26
US7256075B2 (en) 2007-08-14
JP2006518544A (ja) 2006-08-10
US20050170611A1 (en) 2005-08-04
CN1757106A (zh) 2006-04-05
KR100889886B1 (ko) 2009-03-20
DE602004020181D1 (de) 2009-05-07
EP1588416B1 (de) 2009-03-25
CN100483666C (zh) 2009-04-29
WO2004061944A1 (en) 2004-07-22
US20050167002A1 (en) 2005-08-04

Similar Documents

Publication Publication Date Title
ATE426918T1 (de) Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dunnen schicht
TWI367544B (en) Gan donor substrate with a n surface and a ga surface
WO2006017070A3 (en) Protective cotaing on a substrate and method of making thereof
WO2009019147A3 (en) Deposition from ionic liquids
WO2007066277A3 (en) A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device
WO2005109473A3 (en) Adhesion improvement for dielectric layers to conductive materials
WO2005091370A8 (en) Method for manufacturing integrated circuit
TW200636009A (en) Multilayer sheet, production method thereof and pressure-sensitive adhesive sheet using the multilayer sheet
WO2003088340A3 (de) Verfahren zur herstellung strukturierter schichten auf substraten
ATE524827T1 (de) Verfahren zum transfer einer schicht gespannten halbleitermaterials
WO2010120805A3 (en) Modification of magnetic properties of films using ion and neutral beam implantation
WO2007048563A3 (de) Verfahren zum transfer eines mehrschichtkörpers sowie transferfolie
WO2010098993A3 (en) Hdd pattern implant system
WO2010042927A3 (en) Continuous feed chemical vapor deposition
TW200628619A (en) Vacuum coating system
WO2008157345A3 (en) Wafer reclamation compositions and methods
WO2007149991A3 (en) Dielectric deposition and etch back processes for bottom up gapfill
EP1975987A3 (de) Verfahren zum Abstreifen von Material zur Wafer-Wiedergewinnung
WO2008141158A3 (en) Substrate surface structures and processes for forming the same
WO2006079979A3 (en) A method of manufacturing a semiconductor device
WO2009031270A1 (ja) ウエハ再生方法およびウエハ再生装置
WO2008148882A3 (en) Method for producing hybrid components
WO2005103824A3 (en) Method of forming a metal pattern on a substrate
WO2010102089A3 (en) Methods for depositing layers having reduced interfacial contamination
JP2006041453A5 (de)

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties