FR2849715B1 - Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince - Google Patents

Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince

Info

Publication number
FR2849715B1
FR2849715B1 FR0300099A FR0300099A FR2849715B1 FR 2849715 B1 FR2849715 B1 FR 2849715B1 FR 0300099 A FR0300099 A FR 0300099A FR 0300099 A FR0300099 A FR 0300099A FR 2849715 B1 FR2849715 B1 FR 2849715B1
Authority
FR
France
Prior art keywords
recycling
plate
thin layer
multilayer structure
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0300099A
Other languages
English (en)
Other versions
FR2849715A1 (fr
Inventor
Bruno Ghysclen
Cecile Aulnette
Benedite Osternaud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0300099A priority Critical patent/FR2849715B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to JP2006500316A priority patent/JP4949014B2/ja
Priority to TW93100388A priority patent/TWI309064B/zh
Priority to KR1020057012742A priority patent/KR100889886B1/ko
Priority to EP04700491A priority patent/EP1588416B1/fr
Priority to DE602004020181T priority patent/DE602004020181D1/de
Priority to AT04700491T priority patent/ATE426918T1/de
Priority to PCT/IB2004/000311 priority patent/WO2004061944A1/fr
Priority to CNB2004800061438A priority patent/CN100483666C/zh
Publication of FR2849715A1 publication Critical patent/FR2849715A1/fr
Priority to US11/075,273 priority patent/US7256075B2/en
Priority to US11/075,324 priority patent/US20050167002A1/en
Application granted granted Critical
Publication of FR2849715B1 publication Critical patent/FR2849715B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Laminated Bodies (AREA)
FR0300099A 2003-01-07 2003-01-07 Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince Expired - Lifetime FR2849715B1 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
FR0300099A FR2849715B1 (fr) 2003-01-07 2003-01-07 Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince
CNB2004800061438A CN100483666C (zh) 2003-01-07 2004-01-07 施主晶片以及重复利用晶片的方法和剥离有用层的方法
KR1020057012742A KR100889886B1 (ko) 2003-01-07 2004-01-07 박층을 박리한 후 다층 구조를 포함하는 웨이퍼의 재활용방법
EP04700491A EP1588416B1 (fr) 2003-01-07 2004-01-07 Recyclage d'une tranche comprenant une structure multicouches apres l'enlevement d'une couche mince
DE602004020181T DE602004020181D1 (de) 2003-01-07 2004-01-07 Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dünnen schicht
AT04700491T ATE426918T1 (de) 2003-01-07 2004-01-07 Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dunnen schicht
JP2006500316A JP4949014B2 (ja) 2003-01-07 2004-01-07 薄層を除去した後の多層構造を備えるウェハのリサイクル
TW93100388A TWI309064B (en) 2003-01-07 2004-01-07 Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
PCT/IB2004/000311 WO2004061944A1 (fr) 2003-01-07 2004-01-07 Recyclage d'une tranche comprenant une structure multicouches apres l'enlevement d'une couche mince
US11/075,273 US7256075B2 (en) 2003-01-07 2005-03-07 Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
US11/075,324 US20050167002A1 (en) 2003-01-07 2005-03-07 Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0300099A FR2849715B1 (fr) 2003-01-07 2003-01-07 Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince

Publications (2)

Publication Number Publication Date
FR2849715A1 FR2849715A1 (fr) 2004-07-09
FR2849715B1 true FR2849715B1 (fr) 2007-03-09

Family

ID=32524717

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0300099A Expired - Lifetime FR2849715B1 (fr) 2003-01-07 2003-01-07 Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince

Country Status (2)

Country Link
FR (1) FR2849715B1 (fr)
TW (1) TWI309064B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8951887B2 (en) 2011-06-23 2015-02-10 Soitec Process for fabricating a semiconductor structure employing a temporary bond

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
US10373818B1 (en) * 2018-01-31 2019-08-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer recycling

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6162705A (en) * 1997-05-12 2000-12-19 Silicon Genesis Corporation Controlled cleavage process and resulting device using beta annealing
FR2775121B1 (fr) * 1998-02-13 2000-05-05 Picogiga Sa Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP2000223682A (ja) * 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
FR2794893B1 (fr) * 1999-06-14 2001-09-14 France Telecom Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie
US6500732B1 (en) * 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8951887B2 (en) 2011-06-23 2015-02-10 Soitec Process for fabricating a semiconductor structure employing a temporary bond

Also Published As

Publication number Publication date
TWI309064B (en) 2009-04-21
TW200504863A (en) 2005-02-01
FR2849715A1 (fr) 2004-07-09

Similar Documents

Publication Publication Date Title
FR2889887B1 (fr) Procede de report d'une couche mince sur un support
FR2867310B1 (fr) Technique d'amelioration de la qualite d'une couche mince prelevee
NO20055717D0 (no) Flerbelagt eller flerlags innkapslingsmatriks for proteinbiosensorer
DE602004029009D1 (de) Laminatfolie
DE602004019940D1 (de) Polyesterfolie
ATE339189T1 (de) Materialien mit multiplen vesikelschichten
DE60309594D1 (de) Mehrschichtiger Laminatschlauch
DE60323524D1 (de) Metallisierte mehrschichtfolie
EP1656793A4 (fr) Couche de tranche dans une video codec
DE602005025156D1 (de) Laminatfolie
SG114747A1 (en) Etching composition for laminated film including reflective electrode and method for forming laminated wiring structure
FR2889202B1 (fr) Procede de depot d'une couche anti-rayure
DE60029248D1 (de) Biaxial gestreckter bioabbaubarer film
DE602004026664D1 (de) Hochverschleissbeständige Hartstoffschicht
FI20045495A0 (fi) Monikerrosrakenne ja menetelmä sen valmistamiseksi
BR0307590B1 (pt) Laminado
FR2895562B1 (fr) Procede de relaxation d'une couche mince contrainte
HK1075230A1 (en) Multilayered polymer based thin film structure for medical grade products
FR2847076B1 (fr) Procede de detachement d'une couche mince a temperature moderee apres co-implantation
DE60221013D1 (de) Mehrschichtiger polymerfilm
EP1759834A4 (fr) Film stratifié pour plaque de réflexion
DE602004021619D1 (de) Mehrschichtige folie mit witterungsbeständiger oberflächenschicht
FR2855910B1 (fr) Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque
DE502004008860D1 (de) Thermoplastischer Mehrschichtverbund
FR2870988B1 (fr) Procede de realisation d'une structure multi-couches comportant, en profondeur, une couche de separation

Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

PLFP Fee payment

Year of fee payment: 14

PLFP Fee payment

Year of fee payment: 15

PLFP Fee payment

Year of fee payment: 16

PLFP Fee payment

Year of fee payment: 18

PLFP Fee payment

Year of fee payment: 19

PLFP Fee payment

Year of fee payment: 20