CN114256345A - 一种fdsoi器件结构及其制备方法 - Google Patents
一种fdsoi器件结构及其制备方法 Download PDFInfo
- Publication number
- CN114256345A CN114256345A CN202010992679.2A CN202010992679A CN114256345A CN 114256345 A CN114256345 A CN 114256345A CN 202010992679 A CN202010992679 A CN 202010992679A CN 114256345 A CN114256345 A CN 114256345A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon
- germanium
- channel
- fdsoi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 116
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 92
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 58
- 238000002161 passivation Methods 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 16
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 41
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 22
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 229910010038 TiAl Inorganic materials 0.000 claims description 9
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 15
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- -1 SiCoNi Chemical compound 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/263—Amorphous materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
技术领域
本发明涉及半导体技术领域,特别是涉及一种FDSOI器件结构及其制备方法。
背景技术
现有技术中,制作22nm FDSOI(Fully Depleted Silicon-on-Insulator)的PMOS普遍采用硅沟道和金属栅极工艺,其中沟道为硅沟道,栅极为高K金属栅极。此工艺中的沟道为硅沟道,沟道中的应力有待提高,因而为了提高沟道中的应力,将硅沟道替换成锗硅沟道,采用锗硅沟道和金属栅极工艺,这会大大增加沟道的压应力,从而提高空穴迁移率。
但是现有技术中的锗硅沟道中的锗会向栅介质进行扩散,降低了器件的可靠性和性能。
因此,需要提出一种新的器件结构和制备方法来解决上述问题。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种FDSOI器件结构及其制备方法,用于解决现有技术中FDSOI器件的锗硅沟道中的锗会向栅介质进行扩散,降低了器件的可靠性和性能的问题。
为实现上述目的及其他相关目的,本发明提供一种FDSOI器件结构,至少包括:
硅基底;位于所述硅基底上的埋氧层;位于所述埋氧层上的锗硅沟道,所述锗硅沟道的厚度为位于所述锗硅沟道层上的氮钝化层;位于所述氮钝化层上的金属栅极及依附于所述金属栅极侧壁的侧墙;位于氮钝化层上、所述金属栅极两侧的源漏区,所述源漏区为锗硅凸起。
优选地,所述金属栅极包括第一堆叠结构和位于所述第一堆叠结构上的第二堆叠结构;所述第一堆叠结构由自下而上依次堆叠的栅氧层结构、高K介质层结构、氮化钛层结构组成;所述第二堆叠结构由自下而上依次堆叠的TaN层、TiN层、TiAl层和铝层组成。
优选地,所述侧墙为SiCN结构或SiON结构。
本发明还提供一种FDSOI的制备方法,该方法至少包括以下步骤:
步骤一、提供硅基底01,所述硅基底01上设有埋氧层02,所述埋氧层02上设有SOI层03;
步骤二、在所述SOI层03上通过外延沉积法形成锗硅层04;
步骤四、去除所述二氧化硅层05;
步骤五、钝化所述锗硅沟道06上表面形成氮钝化层07;
步骤六、在所述氮钝化层07上依次沉积栅氧层08、高K介质层09以及氮化钛层10;
步骤七、在所述氮化钛层上形成非晶硅层,在所述非晶硅层上沉积硬掩膜层,接着通过光刻定义栅极形貌,依次刻蚀所述硬掩膜层、非晶硅层、氮化钛层、高K介质层以及栅氧层,形成由栅氧层结构、高K介质层结构、氮化钛层结构自下而上依次堆叠组成的第一堆叠结构,并且形成位于所述第一堆叠结构上的非晶硅层结构以及位于所述非晶硅层结构上的硬掩膜层结构,之后在所述第一堆叠层和所述非晶硅层结构的侧壁形成侧墙;
步骤八、在所述氮钝化层上、所述非晶硅层结构的两侧外延生长源漏区,所述源漏区为锗硅凸起;
步骤九、去除所述硬掩膜层结构和所述非晶硅层结构,在所述第一堆叠层上的所述侧墙内形成凹槽;
步骤十、在所述凹槽内依次沉积TaN层、TiN层、TiAl层和铝层将所述凹槽填充满,形成第二堆叠结构;所述第一、第二堆叠结构以及侧墙构成金属栅极;
步骤十一、平坦化所述铝层,之后进行金属互连。
优选地,步骤二中的所述SOI层的表面形成有氧化物;步骤二中采用外延沉积的方法形成所述锗硅层的步骤包括:先用包含有HF、SiCoNi、HCL以及H2中的至少一种去除所述SOI层表面的所述氧化物;接着在所述SOI层上原位生长锗浓度为20%~60%的锗硅层,所述锗硅层的厚度为
优选地,步骤三中的所述高温氧化法的反应温度为1000~2000℃,所述高温氧化法的氧化方式为氧化和退火交替进行,其中退火过程在氮气氛围中进行。
优选地,步骤四中去除所述二氧化硅层的方法包括利用氢氟酸清洗去除所述二氧化硅层或用干法刻蚀方法去除所述二氧化硅层。
优选地,步骤四中去除所述二氧化硅层05后,将所述锗硅沟道上表面暴露,所述锗硅沟道上表面被氧化形成有氧化物;步骤五中钝化所述锗硅沟道上表面形成氮钝化层之前,先去除所述锗硅沟道上表面的所述氧化物。
优选地,步骤五中钝化所述锗硅沟道上表面形成所述氮钝化层之前,利用HF、SiCoNi、HCl以及H2中的至少一种去除所述锗硅沟道上表面的所述氧化物。
优选地,步骤五中钝化所述锗硅沟道上表面形成所述氮钝化层的方法包括:利用氮气或NH3等离子体对所述锗硅沟道上表面进行钝化并退火,形成所述氮钝化层。
如上所述,本发明的FDSOI器件结构及其制备方法,具有以下有益效果:本发明在FDSOI器件制造过程中,将锗硅层以及氮钝化层堆叠结构作为沟道,避免了传统工艺中硅沟道应力低,以及传统工艺中锗硅沟道中的锗向栅介质扩散,提高了器件的可靠性和性能。
附图说明
图1显示为本发明中用于制备FDSOI的硅基底及其上的埋氧层和SOI层的结构示意图;
图2显示为本发明中在SOI层上形成锗硅层后的结构示意图;
图3显示为本发明中形成锗硅沟道及其上的二氧化硅层的结构示意图;
图4显示为本发明中去除锗硅沟道上的二氧化硅层后的结构示意图;
图5显示为本发明中在锗硅沟道上形成氮钝化层的结构示意图;
图6显示为本发明中在氮钝化层上形成栅氧层、高K介质层和氮化钛层的结构示意图;
图7显示为本发明中在氮钝化层上形成第一堆叠结构、非晶硅层结构以及硬掩膜层结构后的结构示意图;
图8显示为本发明中形成源漏区以及在非晶硅层结构侧壁形成侧墙的结构示意图;
图9显示为本发明中去除非晶硅结构形成凹槽的结构示意图;
图10显示为本发明的实施例中的FDSOI器件结构示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图10。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
本发明提供一种FDSOI器件结构,至少包括:硅基底;位于所述硅基底上的埋氧层;位于所述埋氧层上的锗硅沟道,所述锗硅沟道的厚度为位于所述锗硅沟道层上的氮钝化层;位于所述氮钝化层上的金属栅极及依附于所述金属栅极侧壁的侧墙;位于氮钝化层上、所述金属栅极两侧的源漏区,所述源漏区为锗硅凸起。如图10所示,图10显示为本发明的实施例中的FDSOI器件结构示意图。本实施例的FDSOI器件结构包括:硅基底01;位于所述硅基底01上的埋氧层02;进一步地,所述埋氧层的厚度为位于所述埋氧层02上的锗硅沟道06,所述锗硅沟道的厚度为位于所述锗硅沟道层06上的氮钝化层07;位于所述氮钝化层07上的金属栅极及依附于所述金属栅极侧壁的侧墙13;进一步地,所述金属栅极包括第一堆叠结构和位于所述第一堆叠结构上的第二堆叠结构15;所述第一堆叠结构由自下而上依次堆叠的栅氧层结构08’、高K介质层结构09’、氮化钛层结构10’组成;所述第二堆叠结构由自下而上依次堆叠的TaN层、TiN层、TiAl层和铝层组成。再进一步地,所述栅氧层结构的厚度为所述高K介质层结构的厚度为更进一步地,所述TiN层结构的厚度为本实施例中,所述侧墙为SiCN结构或SiON结构。位于氮钝化层07上、所述金属栅极两侧的源漏区14,所述源漏区为锗硅凸起。
本发明还提供所述FDSOI的制备方法,该方法至少包括以下步骤:
步骤一、提供硅基底,所述硅基底上设有埋氧层,所述埋氧层上设有SOI层;
步骤二、在所述SOI层上通过外延沉积法形成锗硅层;
步骤四、去除所述二氧化硅层;
步骤五、钝化所述锗硅沟道上表面形成氮钝化层;
步骤六、在所述氮钝化层上依次沉积栅氧层、高K介质层以及氮化钛层;
步骤七、在所述氮化钛层上形成非晶硅层,在所述非晶硅层上沉积硬掩膜层,接着通过光刻定义栅极形貌,依次刻蚀所述硬掩膜层、非晶硅层、氮化钛层、高K介质层以及栅氧层,形成由栅氧层结构、高K介质层结构、氮化钛层结构自下而上依次堆叠组成的第一堆叠结构,并且形成位于所述第一堆叠结构上的非晶硅层结构以及位于所述非晶硅层结构上的硬掩膜层结构,之后在所述第一堆叠层和所述非晶硅层结构的侧壁形成侧墙;
步骤八、在所述氮钝化层上、所述非晶硅层结构的两侧外延生长源漏区,所述源漏区为锗硅凸起;
步骤九、去除所述硬掩膜层结构和所述非晶硅层结构,在所述第一堆叠层上的所述侧墙内形成凹槽;
步骤十、在所述凹槽内依次沉积TaN层、TiN层、TiAl层和铝层将所述凹槽填充满,形成第二堆叠结构;所述第一、第二堆叠结构以及侧墙构成金属栅极;
步骤十一、平坦化所述铝层,之后进行金属互连。
如图1至图9所示,本实施例中的所述FDSOI的制备方法包括以下步骤:
步骤一、提供硅基底01,所述硅基底01上设有埋氧层02,所述埋氧层02上设有SOI层(绝缘体上硅层)03;如图1所示,图1显示为本发明中用于制备FDSOI的硅基底及其上的埋氧层和SOI层的结构示意图。
步骤二、在所述SOI层03上通过外延沉积法形成锗硅层04;如图2所示,图2显示为本发明中在SOI层上形成锗硅层后的结构示意图。本实施例中步骤一中的所述SOI层的表面形成有氧化物,由于所述SOI层的上表面暴露于空气中,因此所述SOI层的上表面被氧化形成氧化物;本实施例的步骤二形成所述锗硅层04的方法包括:先用包含有HF、SiCoNi、HCL以及H2中的至少一种去除所述SOI层表面的所述氧化物;接着在所述SOI层上原位生长锗浓度为20%~60%的锗硅层04,所述锗硅层04的厚度为
步骤三、采用高温氧化法氧化所述锗硅层04,使得所述锗硅层04中的锗扩散进入所述SOI层,形成厚度为的锗硅沟道06;所述锗硅层04被形成为二氧化硅层05;如图3所示,图3显示为本发明中形成锗硅沟道及其上的二氧化硅层的结构示意图。
本发明进一步地,本实施例中的步骤三中的所述高温氧化法的反应温度为1000~2000℃,所述高温氧化法的氧化方式为氧化和退火交替进行,其中退火过程在氮气氛围中进行。也就是说,该步骤三采用1000~2000℃的高温环境,使得所述锗硅层04被氧化,同时,所述锗硅层04中的锗在高温下、经过多次的氧化-退火交替过程扩散进入所述锗硅层04下方的所述SOI层(绝缘体上硅层)03,形成所述锗硅沟道06,当所述锗硅层中的锗全部扩散进入所述SOI层后,只剩下被氧化的硅,如图3所示,因此形成位于所述锗硅沟道上的所述二氧化硅层05。
步骤四、去除所述二氧化硅层05;如图4所示,图4显示为本发明中去除锗硅沟道上的二氧化硅层后的结构示意图。本发明进一步地,本实施例中的步骤四中去除所述二氧化硅层的方法包括利用氢氟酸(HF)清洗去除所述二氧化硅层05或用干法刻蚀方法去除所述二氧化硅层。
步骤五、钝化所述锗硅沟道上表面形成氮钝化层;如图5所示,图5显示为本发明中在锗硅沟道上形成氮钝化层的结构示意图。本发明进一步地,本实施例的步骤五中钝化所述锗硅沟道06上表面形成氮钝化层07之前,利用HF、SiCoNi、HCl以及H2中的至少一种去除所述锗硅沟道06上表面的所述氧化物。本发明进一步地,步骤四中去除所述二氧化硅层05后,将所述锗硅沟道06上表面暴露,所述锗硅沟道06上表面被氧化形成有氧化物;步骤五中钝化所述锗硅沟道上表面形成氮钝化层之前,先去除所述锗硅沟道06上表面的所述氧化物。
再进一步地,步骤五中钝化所述锗硅沟道上表面形成氮钝化层的方法包括:利用氮气或NH3等离子体对所述锗硅沟道上表面进行钝化并退火,形成所述氮钝化层。。也就是说,本实施例去除所述锗硅沟道06上表面的氧化物后接着利用氮气或NH3等离子体对所述锗硅沟道上表面进行钝化,形成所述氮钝化层07。
步骤六、在所述氮钝化层上依次沉积栅氧层、高K介质层以及氮化钛层;如图6所示,图6显示为本发明中在氮钝化层上形成栅氧层、高K介质层和氮化钛层的结构示意图。该步骤六在所述氮钝化层07上依次沉积栅氧层08、高K介质层09以及氮化钛层10。本发明进一步地,本实施例的步骤六中在所述氮钝化层07上沉积所述栅氧层08的方式为原位水汽生成法,沉积的所述栅氧层08的厚度为沉积的所述高K介质层09为HfO2或HfLaO2,所述高K介质层09的厚度为沉积的所述氮化钛层10的厚度为
步骤七、如图7所示,图7显示为本发明中在氮钝化层上形成第一堆叠结构、非晶硅层结构以及硬掩膜层结构后的结构示意图。该步骤七中在所述氮化钛层上形成非晶硅层,在所述非晶硅层上沉积硬掩膜层,接着通过光刻定义金属栅极形貌,依次刻蚀所述硬掩膜层、非晶硅层、氮化钛层、高K介质层以及栅氧层,形成由栅氧层结构08’、高K介质层结构09’、氮化钛层结构10’自下而上依次堆叠组成的第一堆叠结构,并且形成位于所述第一堆叠结构上的非晶硅层结构11以及位于所述非晶硅层结构11上的硬掩膜层结构12,之后在所述第一堆叠层和所述非晶硅层结构11的侧壁形成侧墙;如图8所示,图8显示为本发明中形成源漏区以及在非晶硅层结构侧壁形成侧墙的结构示意图。所述侧墙13依附于所述第一堆叠层和所述非晶硅层结构11的侧壁。
步骤八、在所述氮钝化层上、所述第一堆叠层和所述非晶硅层结构的两侧外延生长源漏区,所述源漏区为锗硅凸起;如图8所示,所述源漏区14为锗硅凸起,所述第一堆叠层及所述非晶硅层结构为待形成的所述金属栅极,所述源漏区位于所述待形成的所述金属栅极的两侧。
步骤九、去除所述硬掩膜层结构和所述非晶硅层结构,在所述第一堆叠层上的所述侧墙内形成凹槽;如图9所示,图9显示为本发明中去除非晶硅结构形成凹槽的结构示意图。该步骤九将位于所述第一堆叠层上的非晶硅层结构去除,形成凹槽M。本发明进一步地,本实施例中的步骤八中外延生长的所述锗硅凸起中锗的浓度占比为20%~50%,且所述锗硅凸起中含有浓度为1*1019~1*1021的硼;所述锗硅凸起的厚度为
步骤十、在所述凹槽内依次沉积TaN层、TiN层、TiAl层和铝层将所述凹槽填充满,形成第二堆叠结构;所述第一、第二堆叠结构以及侧墙构成金属栅极;如图10所示,图10显示为本发明中在凹槽内形成第二堆叠结构的结构示意图。所述第一堆叠结构由位于所述第一堆叠层上的TaN层、位于所述TaN层上的TiN层、位于所述TiN层上的TiAl层、位于所述TiAl层上的铝层构成,本发明中的所述金属栅极由所述第一堆叠层、第二堆叠结构以及侧墙构成。
步骤十一、平坦化所述铝层,之后进行金属互连。
综上所述,本发明在FDSOI器件制造过程中,将锗硅层以及氮钝化层堆叠结构作为沟道,避免了传统工艺中硅沟道应力低,以及传统工艺中锗硅沟道中的锗向栅介质扩散,提高了器件的可靠性和性能。所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (17)
4.根据权利要求1所述的FDSOI器件结构,其特征在于:所述金属栅极包括第一堆叠结构和位于所述第一堆叠结构上的第二堆叠结构;所述第一堆叠结构由自下而上依次堆叠的栅氧层结构、高K介质层结构、氮化钛层结构组成;所述第二堆叠结构由自下而上依次堆叠的TaN层、TiN层、TiAl层和铝层组成。
8.根据权利要求1所述的FDSOI器件结构,其特征在于:所述侧墙为SiCN结构或SiON结构。
9.根据权利要求1至8任意一项所述的FDSOI的制备方法,其特征在于,该方法至少包括以下步骤:
步骤一、提供硅基底01,所述硅基底01上设有埋氧层02,所述埋氧层02上设有SOI层03;
步骤二、在所述SOI层03上通过外延沉积法形成锗硅层04;
步骤四、去除所述二氧化硅层05;
步骤五、钝化所述锗硅沟道06上表面形成氮钝化层07;
步骤六、在所述氮钝化层07上依次沉积栅氧层08、高K介质层09以及氮化钛层10;
步骤七、在所述氮化钛层上形成非晶硅层,在所述非晶硅层上沉积硬掩膜层,接着通过光刻定义栅极形貌,依次刻蚀所述硬掩膜层、非晶硅层、氮化钛层、高K介质层以及栅氧层,形成由栅氧层结构、高K介质层结构、氮化钛层结构自下而上依次堆叠组成的第一堆叠结构,并且形成位于所述第一堆叠结构上的非晶硅层结构以及位于所述非晶硅层结构上的硬掩膜层结构,之后在所述第一堆叠层和所述非晶硅层结构的侧壁形成侧墙;
步骤八、在所述非晶硅层结构的两侧外延生长源漏区,所述源漏区为锗硅凸起;
步骤九、去除所述硬掩膜层结构和所述非晶硅层结构,在所述第一堆叠层上的所述侧墙内形成凹槽;
步骤十、在所述凹槽内依次沉积TaN层、TiN层、TiAl层和铝层将所述凹槽填充满,形成第二堆叠结构;所述第一、第二堆叠结构以及侧墙构成金属栅极;
步骤十一、平坦化所述铝层,之后进行金属互连。
11.根据权利要求9所述的FDSOI的制备方法,其特征在于:步骤三中的所述高温氧化法的反应温度为1000~2000℃,所述高温氧化法的氧化方式为氧化和退火交替进行,其中退火过程在氮气氛围中进行。
12.根据权利要求9所述的FDSOI的制备方法,其特征在于:步骤四中去除所述二氧化硅层的方法包括利用氢氟酸清洗去除所述二氧化硅层或用干法刻蚀方法去除所述二氧化硅层。
13.根据权利要求9所述的FDSOI的制备方法,其特征在于:步骤四中去除所述二氧化硅层05后,将所述锗硅沟道上表面暴露,所述锗硅沟道上表面被氧化形成有氧化物;步骤五中钝化所述锗硅沟道上表面形成氮钝化层之前,先去除所述锗硅沟道上表面的所述氧化物。
14.根据权利要求13所述的FDSOI的制备方法,其特征在于:步骤五中钝化所述锗硅沟道上表面形成所述氮钝化层之前,利用HF、SiCoNi、HCl以及H2中的至少一种去除所述锗硅沟道上表面的所述氧化物。
15.根据权利要求9所述的FDSOI的制备方法,其特征在于:步骤五中钝化所述锗硅沟道上表面形成所述氮钝化层的方法包括:利用氮气或NH3等离子体对所述锗硅沟道上表面进行钝化并退火,形成所述氮钝化层。。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010992679.2A CN114256345A (zh) | 2020-09-21 | 2020-09-21 | 一种fdsoi器件结构及其制备方法 |
US17/107,375 US11569385B2 (en) | 2020-09-21 | 2020-11-30 | FDSOI device structure and preparation method thereof |
US18/086,326 US11855212B2 (en) | 2020-09-21 | 2022-12-21 | FDSOI device structure and preparation method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010992679.2A CN114256345A (zh) | 2020-09-21 | 2020-09-21 | 一种fdsoi器件结构及其制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114256345A true CN114256345A (zh) | 2022-03-29 |
Family
ID=80740995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010992679.2A Pending CN114256345A (zh) | 2020-09-21 | 2020-09-21 | 一种fdsoi器件结构及其制备方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US11569385B2 (zh) |
CN (1) | CN114256345A (zh) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010147104A (ja) * | 2008-12-16 | 2010-07-01 | Toshiba Corp | 半導体装置の製造方法 |
US8828851B2 (en) * | 2012-02-01 | 2014-09-09 | Stmicroeletronics, Inc. | Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering |
US11152214B2 (en) * | 2016-04-20 | 2021-10-19 | International Business Machines Corporation | Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device |
US11282938B2 (en) * | 2018-09-28 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capping layers in metal gates of transistors |
-
2020
- 2020-09-21 CN CN202010992679.2A patent/CN114256345A/zh active Pending
- 2020-11-30 US US17/107,375 patent/US11569385B2/en active Active
-
2022
- 2022-12-21 US US18/086,326 patent/US11855212B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20230126031A1 (en) | 2023-04-27 |
US11569385B2 (en) | 2023-01-31 |
US20220093799A1 (en) | 2022-03-24 |
US11855212B2 (en) | 2023-12-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20220045214A1 (en) | Passivated and Faceted for Fin Field Effect Transistor | |
TWI458096B (zh) | 半導體裝置及其製造方法 | |
CN104218083B (zh) | 半导体器件以及形成半导体器件的方法 | |
US20060022266A1 (en) | Manufacturable recessed strained rsd structure and process for advanced cmos | |
CN112563318A (zh) | 半导体装置 | |
CN113437023A (zh) | 半导体元件及其制造方法 | |
CN114334965A (zh) | 半导体装置结构 | |
TW202006831A (zh) | 半導體裝置與其形成方法 | |
TWI848705B (zh) | 半導體裝置的製造方法 | |
CN101339902B (zh) | 高压半导体器件及其制造方法 | |
CN111933572A (zh) | 半导体结构及其制作方法 | |
CN218482246U (zh) | 半导体装置 | |
CN114256345A (zh) | 一种fdsoi器件结构及其制备方法 | |
CN114256346A (zh) | 一种fdsoi器件结构及其制备方法 | |
CN115881642A (zh) | 西格玛沟槽结构的制造方法及半导体器件的制造方法 | |
US20230040843A1 (en) | Nanostructure field-effect transistor device and method of forming | |
TWI802866B (zh) | 半導體元件及其形成方法 | |
CN110571266A (zh) | Finfet器件及其制备方法 | |
TWI798865B (zh) | 具有水平配置電容器之半導體元件的製備方法 | |
US11855140B2 (en) | Gate oxide of nanostructure transistor with increased corner thickness | |
JP4104997B2 (ja) | 半導体装置の製造方法 | |
TW202213774A (zh) | 半導體裝置及其製造方法 | |
CN117316768A (zh) | 无体积氟掺入方法 | |
TW202245263A (zh) | 半導體裝置結構 | |
KR20030053658A (ko) | 반도체소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |