ATE518256T1 - Verfahren zur herstellung eines nitrid-halbleiter-bauelements - Google Patents

Verfahren zur herstellung eines nitrid-halbleiter-bauelements

Info

Publication number
ATE518256T1
ATE518256T1 AT06254913T AT06254913T ATE518256T1 AT E518256 T1 ATE518256 T1 AT E518256T1 AT 06254913 T AT06254913 T AT 06254913T AT 06254913 T AT06254913 T AT 06254913T AT E518256 T1 ATE518256 T1 AT E518256T1
Authority
AT
Austria
Prior art keywords
nitride semiconductor
producing
semiconductor component
layer
stripping layer
Prior art date
Application number
AT06254913T
Other languages
English (en)
Inventor
Yasumitsu Kunoh
Kunio Takeuchi
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Application granted granted Critical
Publication of ATE518256T1 publication Critical patent/ATE518256T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
AT06254913T 2005-09-22 2006-09-22 Verfahren zur herstellung eines nitrid-halbleiter-bauelements ATE518256T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005276854 2005-09-22
JP2006249883A JP2007116110A (ja) 2005-09-22 2006-09-14 窒化物系半導体素子の製造方法

Publications (1)

Publication Number Publication Date
ATE518256T1 true ATE518256T1 (de) 2011-08-15

Family

ID=37429254

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06254913T ATE518256T1 (de) 2005-09-22 2006-09-22 Verfahren zur herstellung eines nitrid-halbleiter-bauelements

Country Status (5)

Country Link
US (1) US7759219B2 (de)
EP (1) EP1768194B1 (de)
JP (1) JP2007116110A (de)
CN (1) CN1937271B (de)
AT (1) ATE518256T1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11310420B2 (en) 2018-02-22 2022-04-19 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Generating panoramic images

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303033A1 (en) * 2007-06-05 2008-12-11 Cree, Inc. Formation of nitride-based optoelectronic and electronic device structures on lattice-matched substrates
JP4937025B2 (ja) * 2007-07-20 2012-05-23 三洋電機株式会社 半導体レーザ素子およびその製造方法
US7915643B2 (en) * 2007-09-17 2011-03-29 Transphorm Inc. Enhancement mode gallium nitride power devices
JP2010177390A (ja) * 2009-01-29 2010-08-12 Sony Corp 素子の移載方法および表示装置の製造方法
JP5771968B2 (ja) * 2010-04-09 2015-09-02 住友電気工業株式会社 半導体デバイスの製造方法、エピ成長用積層支持基板およびデバイス用積層支持基板
CN102699537B (zh) * 2012-05-18 2015-11-04 杭州士兰明芯科技有限公司 激光剥离led衬底的系统及方法
JP2013128150A (ja) * 2013-03-26 2013-06-27 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物半導体からなる発光素子の製造方法
FR3009644B1 (fr) * 2013-08-08 2016-12-23 Soitec Silicon On Insulator Procede, empilement et ensemble de separation d'une structure d'un substrat par irradiations electromagnetiques
CN106887505B (zh) * 2017-04-24 2019-07-16 芜湖聚飞光电科技有限公司 一种单面发光芯片级led的制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684309A (en) * 1996-07-11 1997-11-04 North Carolina State University Stacked quantum well aluminum indium gallium nitride light emitting diodes
US6071795A (en) 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
JP3525061B2 (ja) * 1998-09-25 2004-05-10 株式会社東芝 半導体発光素子の製造方法
JP2001119104A (ja) * 1999-10-21 2001-04-27 Matsushita Electric Ind Co Ltd 半導体の製造方法
JP2002319702A (ja) * 2001-04-19 2002-10-31 Sony Corp 窒化物半導体素子の製造方法、窒化物半導体素子
JP4524953B2 (ja) 2001-05-18 2010-08-18 パナソニック株式会社 窒化物半導体基板の製造方法および窒化物半導体装置の製造方法
US6455340B1 (en) * 2001-12-21 2002-09-24 Xerox Corporation Method of fabricating GaN semiconductor structures using laser-assisted epitaxial liftoff
JP4117156B2 (ja) 2002-07-02 2008-07-16 日本電気株式会社 Ｉｉｉ族窒化物半導体基板の製造方法
JP2004072052A (ja) 2002-08-09 2004-03-04 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7056810B2 (en) * 2002-12-18 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance
JP4218597B2 (ja) 2003-08-08 2009-02-04 住友電気工業株式会社 半導体発光素子の製造方法
US7341880B2 (en) 2003-09-17 2008-03-11 Luminus Devices, Inc. Light emitting device processes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11310420B2 (en) 2018-02-22 2022-04-19 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Generating panoramic images

Also Published As

Publication number Publication date
EP1768194A2 (de) 2007-03-28
US7759219B2 (en) 2010-07-20
CN1937271A (zh) 2007-03-28
CN1937271B (zh) 2011-03-09
JP2007116110A (ja) 2007-05-10
US20070066037A1 (en) 2007-03-22
EP1768194A3 (de) 2009-12-09
EP1768194B1 (de) 2011-07-27

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